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CSPRNG/Debug/csprng.list
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csprng.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000001ac 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00003abc 080001ac 080001ac 000101ac 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000018 08003c68 08003c68 00013c68 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08003c80 08003c80 000206c8 2**0
CONTENTS
4 .ARM 00000008 08003c80 08003c80 00013c80 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 08003c88 08003c88 000206c8 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000008 08003c88 08003c88 00013c88 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 08003c90 08003c90 00013c90 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 000006c8 20000000 08003c94 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .ccmram 00000000 10000000 10000000 000206c8 2**0
CONTENTS
10 .bss 00000b74 200006c8 200006c8 000206c8 2**2
ALLOC
11 ._user_heap_stack 00000604 2000123c 2000123c 000206c8 2**0
ALLOC
12 .ARM.attributes 00000030 00000000 00000000 000206c8 2**0
CONTENTS, READONLY
13 .comment 00000043 00000000 00000000 000206f8 2**0
CONTENTS, READONLY
14 .debug_info 0000ec80 00000000 00000000 0002073b 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_abbrev 00001f5a 00000000 00000000 0002f3bb 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_aranges 00000c30 00000000 00000000 00031318 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_rnglists 00000963 00000000 00000000 00031f48 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_macro 00024565 00000000 00000000 000328ab 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .debug_line 0000cef7 00000000 00000000 00056e10 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
20 .debug_str 000db955 00000000 00000000 00063d07 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_frame 0000354c 00000000 00000000 0013f65c 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
22 .debug_line_str 0000005f 00000000 00000000 00142ba8 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
080001ac <__do_global_dtors_aux>:
80001ac: b510 push {r4, lr}
80001ae: 4c05 ldr r4, [pc, #20] ; (80001c4 <__do_global_dtors_aux+0x18>)
80001b0: 7823 ldrb r3, [r4, #0]
80001b2: b933 cbnz r3, 80001c2 <__do_global_dtors_aux+0x16>
80001b4: 4b04 ldr r3, [pc, #16] ; (80001c8 <__do_global_dtors_aux+0x1c>)
80001b6: b113 cbz r3, 80001be <__do_global_dtors_aux+0x12>
80001b8: 4804 ldr r0, [pc, #16] ; (80001cc <__do_global_dtors_aux+0x20>)
80001ba: f3af 8000 nop.w
80001be: 2301 movs r3, #1
80001c0: 7023 strb r3, [r4, #0]
80001c2: bd10 pop {r4, pc}
80001c4: 200006c8 .word 0x200006c8
80001c8: 00000000 .word 0x00000000
80001cc: 08003c50 .word 0x08003c50
080001d0 <frame_dummy>:
80001d0: b508 push {r3, lr}
80001d2: 4b03 ldr r3, [pc, #12] ; (80001e0 <frame_dummy+0x10>)
80001d4: b11b cbz r3, 80001de <frame_dummy+0xe>
80001d6: 4903 ldr r1, [pc, #12] ; (80001e4 <frame_dummy+0x14>)
80001d8: 4803 ldr r0, [pc, #12] ; (80001e8 <frame_dummy+0x18>)
80001da: f3af 8000 nop.w
80001de: bd08 pop {r3, pc}
80001e0: 00000000 .word 0x00000000
80001e4: 200006cc .word 0x200006cc
80001e8: 08003c50 .word 0x08003c50
080001ec <strlen>:
80001ec: 4603 mov r3, r0
80001ee: f813 2b01 ldrb.w r2, [r3], #1
80001f2: 2a00 cmp r2, #0
80001f4: d1fb bne.n 80001ee <strlen+0x2>
80001f6: 1a18 subs r0, r3, r0
80001f8: 3801 subs r0, #1
80001fa: 4770 bx lr
080001fc <__aeabi_uldivmod>:
80001fc: b953 cbnz r3, 8000214 <__aeabi_uldivmod+0x18>
80001fe: b94a cbnz r2, 8000214 <__aeabi_uldivmod+0x18>
8000200: 2900 cmp r1, #0
8000202: bf08 it eq
8000204: 2800 cmpeq r0, #0
8000206: bf1c itt ne
8000208: f04f 31ff movne.w r1, #4294967295 ; 0xffffffff
800020c: f04f 30ff movne.w r0, #4294967295 ; 0xffffffff
8000210: f000 b970 b.w 80004f4 <__aeabi_idiv0>
8000214: f1ad 0c08 sub.w ip, sp, #8
8000218: e96d ce04 strd ip, lr, [sp, #-16]!
800021c: f000 f806 bl 800022c <__udivmoddi4>
8000220: f8dd e004 ldr.w lr, [sp, #4]
8000224: e9dd 2302 ldrd r2, r3, [sp, #8]
8000228: b004 add sp, #16
800022a: 4770 bx lr
0800022c <__udivmoddi4>:
800022c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
8000230: 9e08 ldr r6, [sp, #32]
8000232: 460d mov r5, r1
8000234: 4604 mov r4, r0
8000236: 460f mov r7, r1
8000238: 2b00 cmp r3, #0
800023a: d14a bne.n 80002d2 <__udivmoddi4+0xa6>
800023c: 428a cmp r2, r1
800023e: 4694 mov ip, r2
8000240: d965 bls.n 800030e <__udivmoddi4+0xe2>
8000242: fab2 f382 clz r3, r2
8000246: b143 cbz r3, 800025a <__udivmoddi4+0x2e>
8000248: fa02 fc03 lsl.w ip, r2, r3
800024c: f1c3 0220 rsb r2, r3, #32
8000250: 409f lsls r7, r3
8000252: fa20 f202 lsr.w r2, r0, r2
8000256: 4317 orrs r7, r2
8000258: 409c lsls r4, r3
800025a: ea4f 4e1c mov.w lr, ip, lsr #16
800025e: fa1f f58c uxth.w r5, ip
8000262: fbb7 f1fe udiv r1, r7, lr
8000266: 0c22 lsrs r2, r4, #16
8000268: fb0e 7711 mls r7, lr, r1, r7
800026c: ea42 4207 orr.w r2, r2, r7, lsl #16
8000270: fb01 f005 mul.w r0, r1, r5
8000274: 4290 cmp r0, r2
8000276: d90a bls.n 800028e <__udivmoddi4+0x62>
8000278: eb1c 0202 adds.w r2, ip, r2
800027c: f101 37ff add.w r7, r1, #4294967295 ; 0xffffffff
8000280: f080 811c bcs.w 80004bc <__udivmoddi4+0x290>
8000284: 4290 cmp r0, r2
8000286: f240 8119 bls.w 80004bc <__udivmoddi4+0x290>
800028a: 3902 subs r1, #2
800028c: 4462 add r2, ip
800028e: 1a12 subs r2, r2, r0
8000290: b2a4 uxth r4, r4
8000292: fbb2 f0fe udiv r0, r2, lr
8000296: fb0e 2210 mls r2, lr, r0, r2
800029a: ea44 4402 orr.w r4, r4, r2, lsl #16
800029e: fb00 f505 mul.w r5, r0, r5
80002a2: 42a5 cmp r5, r4
80002a4: d90a bls.n 80002bc <__udivmoddi4+0x90>
80002a6: eb1c 0404 adds.w r4, ip, r4
80002aa: f100 32ff add.w r2, r0, #4294967295 ; 0xffffffff
80002ae: f080 8107 bcs.w 80004c0 <__udivmoddi4+0x294>
80002b2: 42a5 cmp r5, r4
80002b4: f240 8104 bls.w 80004c0 <__udivmoddi4+0x294>
80002b8: 4464 add r4, ip
80002ba: 3802 subs r0, #2
80002bc: ea40 4001 orr.w r0, r0, r1, lsl #16
80002c0: 1b64 subs r4, r4, r5
80002c2: 2100 movs r1, #0
80002c4: b11e cbz r6, 80002ce <__udivmoddi4+0xa2>
80002c6: 40dc lsrs r4, r3
80002c8: 2300 movs r3, #0
80002ca: e9c6 4300 strd r4, r3, [r6]
80002ce: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
80002d2: 428b cmp r3, r1
80002d4: d908 bls.n 80002e8 <__udivmoddi4+0xbc>
80002d6: 2e00 cmp r6, #0
80002d8: f000 80ed beq.w 80004b6 <__udivmoddi4+0x28a>
80002dc: 2100 movs r1, #0
80002de: e9c6 0500 strd r0, r5, [r6]
80002e2: 4608 mov r0, r1
80002e4: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
80002e8: fab3 f183 clz r1, r3
80002ec: 2900 cmp r1, #0
80002ee: d149 bne.n 8000384 <__udivmoddi4+0x158>
80002f0: 42ab cmp r3, r5
80002f2: d302 bcc.n 80002fa <__udivmoddi4+0xce>
80002f4: 4282 cmp r2, r0
80002f6: f200 80f8 bhi.w 80004ea <__udivmoddi4+0x2be>
80002fa: 1a84 subs r4, r0, r2
80002fc: eb65 0203 sbc.w r2, r5, r3
8000300: 2001 movs r0, #1
8000302: 4617 mov r7, r2
8000304: 2e00 cmp r6, #0
8000306: d0e2 beq.n 80002ce <__udivmoddi4+0xa2>
8000308: e9c6 4700 strd r4, r7, [r6]
800030c: e7df b.n 80002ce <__udivmoddi4+0xa2>
800030e: b902 cbnz r2, 8000312 <__udivmoddi4+0xe6>
8000310: deff udf #255 ; 0xff
8000312: fab2 f382 clz r3, r2
8000316: 2b00 cmp r3, #0
8000318: f040 8090 bne.w 800043c <__udivmoddi4+0x210>
800031c: 1a8a subs r2, r1, r2
800031e: ea4f 471c mov.w r7, ip, lsr #16
8000322: fa1f fe8c uxth.w lr, ip
8000326: 2101 movs r1, #1
8000328: fbb2 f5f7 udiv r5, r2, r7
800032c: fb07 2015 mls r0, r7, r5, r2
8000330: 0c22 lsrs r2, r4, #16
8000332: ea42 4200 orr.w r2, r2, r0, lsl #16
8000336: fb0e f005 mul.w r0, lr, r5
800033a: 4290 cmp r0, r2
800033c: d908 bls.n 8000350 <__udivmoddi4+0x124>
800033e: eb1c 0202 adds.w r2, ip, r2
8000342: f105 38ff add.w r8, r5, #4294967295 ; 0xffffffff
8000346: d202 bcs.n 800034e <__udivmoddi4+0x122>
8000348: 4290 cmp r0, r2
800034a: f200 80cb bhi.w 80004e4 <__udivmoddi4+0x2b8>
800034e: 4645 mov r5, r8
8000350: 1a12 subs r2, r2, r0
8000352: b2a4 uxth r4, r4
8000354: fbb2 f0f7 udiv r0, r2, r7
8000358: fb07 2210 mls r2, r7, r0, r2
800035c: ea44 4402 orr.w r4, r4, r2, lsl #16
8000360: fb0e fe00 mul.w lr, lr, r0
8000364: 45a6 cmp lr, r4
8000366: d908 bls.n 800037a <__udivmoddi4+0x14e>
8000368: eb1c 0404 adds.w r4, ip, r4
800036c: f100 32ff add.w r2, r0, #4294967295 ; 0xffffffff
8000370: d202 bcs.n 8000378 <__udivmoddi4+0x14c>
8000372: 45a6 cmp lr, r4
8000374: f200 80bb bhi.w 80004ee <__udivmoddi4+0x2c2>
8000378: 4610 mov r0, r2
800037a: eba4 040e sub.w r4, r4, lr
800037e: ea40 4005 orr.w r0, r0, r5, lsl #16
8000382: e79f b.n 80002c4 <__udivmoddi4+0x98>
8000384: f1c1 0720 rsb r7, r1, #32
8000388: 408b lsls r3, r1
800038a: fa22 fc07 lsr.w ip, r2, r7
800038e: ea4c 0c03 orr.w ip, ip, r3
8000392: fa05 f401 lsl.w r4, r5, r1
8000396: fa20 f307 lsr.w r3, r0, r7
800039a: 40fd lsrs r5, r7
800039c: ea4f 491c mov.w r9, ip, lsr #16
80003a0: 4323 orrs r3, r4
80003a2: fbb5 f8f9 udiv r8, r5, r9
80003a6: fa1f fe8c uxth.w lr, ip
80003aa: fb09 5518 mls r5, r9, r8, r5
80003ae: 0c1c lsrs r4, r3, #16
80003b0: ea44 4405 orr.w r4, r4, r5, lsl #16
80003b4: fb08 f50e mul.w r5, r8, lr
80003b8: 42a5 cmp r5, r4
80003ba: fa02 f201 lsl.w r2, r2, r1
80003be: fa00 f001 lsl.w r0, r0, r1
80003c2: d90b bls.n 80003dc <__udivmoddi4+0x1b0>
80003c4: eb1c 0404 adds.w r4, ip, r4
80003c8: f108 3aff add.w sl, r8, #4294967295 ; 0xffffffff
80003cc: f080 8088 bcs.w 80004e0 <__udivmoddi4+0x2b4>
80003d0: 42a5 cmp r5, r4
80003d2: f240 8085 bls.w 80004e0 <__udivmoddi4+0x2b4>
80003d6: f1a8 0802 sub.w r8, r8, #2
80003da: 4464 add r4, ip
80003dc: 1b64 subs r4, r4, r5
80003de: b29d uxth r5, r3
80003e0: fbb4 f3f9 udiv r3, r4, r9
80003e4: fb09 4413 mls r4, r9, r3, r4
80003e8: ea45 4404 orr.w r4, r5, r4, lsl #16
80003ec: fb03 fe0e mul.w lr, r3, lr
80003f0: 45a6 cmp lr, r4
80003f2: d908 bls.n 8000406 <__udivmoddi4+0x1da>
80003f4: eb1c 0404 adds.w r4, ip, r4
80003f8: f103 35ff add.w r5, r3, #4294967295 ; 0xffffffff
80003fc: d26c bcs.n 80004d8 <__udivmoddi4+0x2ac>
80003fe: 45a6 cmp lr, r4
8000400: d96a bls.n 80004d8 <__udivmoddi4+0x2ac>
8000402: 3b02 subs r3, #2
8000404: 4464 add r4, ip
8000406: ea43 4308 orr.w r3, r3, r8, lsl #16
800040a: fba3 9502 umull r9, r5, r3, r2
800040e: eba4 040e sub.w r4, r4, lr
8000412: 42ac cmp r4, r5
8000414: 46c8 mov r8, r9
8000416: 46ae mov lr, r5
8000418: d356 bcc.n 80004c8 <__udivmoddi4+0x29c>
800041a: d053 beq.n 80004c4 <__udivmoddi4+0x298>
800041c: b156 cbz r6, 8000434 <__udivmoddi4+0x208>
800041e: ebb0 0208 subs.w r2, r0, r8
8000422: eb64 040e sbc.w r4, r4, lr
8000426: fa04 f707 lsl.w r7, r4, r7
800042a: 40ca lsrs r2, r1
800042c: 40cc lsrs r4, r1
800042e: 4317 orrs r7, r2
8000430: e9c6 7400 strd r7, r4, [r6]
8000434: 4618 mov r0, r3
8000436: 2100 movs r1, #0
8000438: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
800043c: f1c3 0120 rsb r1, r3, #32
8000440: fa02 fc03 lsl.w ip, r2, r3
8000444: fa20 f201 lsr.w r2, r0, r1
8000448: fa25 f101 lsr.w r1, r5, r1
800044c: 409d lsls r5, r3
800044e: 432a orrs r2, r5
8000450: ea4f 471c mov.w r7, ip, lsr #16
8000454: fa1f fe8c uxth.w lr, ip
8000458: fbb1 f0f7 udiv r0, r1, r7
800045c: fb07 1510 mls r5, r7, r0, r1
8000460: 0c11 lsrs r1, r2, #16
8000462: ea41 4105 orr.w r1, r1, r5, lsl #16
8000466: fb00 f50e mul.w r5, r0, lr
800046a: 428d cmp r5, r1
800046c: fa04 f403 lsl.w r4, r4, r3
8000470: d908 bls.n 8000484 <__udivmoddi4+0x258>
8000472: eb1c 0101 adds.w r1, ip, r1
8000476: f100 38ff add.w r8, r0, #4294967295 ; 0xffffffff
800047a: d22f bcs.n 80004dc <__udivmoddi4+0x2b0>
800047c: 428d cmp r5, r1
800047e: d92d bls.n 80004dc <__udivmoddi4+0x2b0>
8000480: 3802 subs r0, #2
8000482: 4461 add r1, ip
8000484: 1b49 subs r1, r1, r5
8000486: b292 uxth r2, r2
8000488: fbb1 f5f7 udiv r5, r1, r7
800048c: fb07 1115 mls r1, r7, r5, r1
8000490: ea42 4201 orr.w r2, r2, r1, lsl #16
8000494: fb05 f10e mul.w r1, r5, lr
8000498: 4291 cmp r1, r2
800049a: d908 bls.n 80004ae <__udivmoddi4+0x282>
800049c: eb1c 0202 adds.w r2, ip, r2
80004a0: f105 38ff add.w r8, r5, #4294967295 ; 0xffffffff
80004a4: d216 bcs.n 80004d4 <__udivmoddi4+0x2a8>
80004a6: 4291 cmp r1, r2
80004a8: d914 bls.n 80004d4 <__udivmoddi4+0x2a8>
80004aa: 3d02 subs r5, #2
80004ac: 4462 add r2, ip
80004ae: 1a52 subs r2, r2, r1
80004b0: ea45 4100 orr.w r1, r5, r0, lsl #16
80004b4: e738 b.n 8000328 <__udivmoddi4+0xfc>
80004b6: 4631 mov r1, r6
80004b8: 4630 mov r0, r6
80004ba: e708 b.n 80002ce <__udivmoddi4+0xa2>
80004bc: 4639 mov r1, r7
80004be: e6e6 b.n 800028e <__udivmoddi4+0x62>
80004c0: 4610 mov r0, r2
80004c2: e6fb b.n 80002bc <__udivmoddi4+0x90>
80004c4: 4548 cmp r0, r9
80004c6: d2a9 bcs.n 800041c <__udivmoddi4+0x1f0>
80004c8: ebb9 0802 subs.w r8, r9, r2
80004cc: eb65 0e0c sbc.w lr, r5, ip
80004d0: 3b01 subs r3, #1
80004d2: e7a3 b.n 800041c <__udivmoddi4+0x1f0>
80004d4: 4645 mov r5, r8
80004d6: e7ea b.n 80004ae <__udivmoddi4+0x282>
80004d8: 462b mov r3, r5
80004da: e794 b.n 8000406 <__udivmoddi4+0x1da>
80004dc: 4640 mov r0, r8
80004de: e7d1 b.n 8000484 <__udivmoddi4+0x258>
80004e0: 46d0 mov r8, sl
80004e2: e77b b.n 80003dc <__udivmoddi4+0x1b0>
80004e4: 3d02 subs r5, #2
80004e6: 4462 add r2, ip
80004e8: e732 b.n 8000350 <__udivmoddi4+0x124>
80004ea: 4608 mov r0, r1
80004ec: e70a b.n 8000304 <__udivmoddi4+0xd8>
80004ee: 4464 add r4, ip
80004f0: 3802 subs r0, #2
80004f2: e742 b.n 800037a <__udivmoddi4+0x14e>
080004f4 <__aeabi_idiv0>:
80004f4: 4770 bx lr
80004f6: bf00 nop
080004f8 <init_entropy>:
/* USER CODE BEGIN 0 */
/*
* Fill the entropy structure with random data
*/
void init_entropy(){
80004f8: b580 push {r7, lr}
80004fa: af00 add r7, sp, #0
// Generate entropy
memset(&s_entropy, 0, sizeof(s_entropy));
80004fc: f44f 7202 mov.w r2, #520 ; 0x208
8000500: 2100 movs r1, #0
8000502: 4810 ldr r0, [pc, #64] ; (8000544 <init_entropy+0x4c>)
8000504: f003 fb12 bl 8003b2c <memset>
while(s_entropy.pool_size < BUFSIZE){
8000508: e010 b.n 800052c <init_entropy+0x34>
generateEntropy(s_entropy.position++);
800050a: 4b0e ldr r3, [pc, #56] ; (8000544 <init_entropy+0x4c>)
800050c: f8d3 3204 ldr.w r3, [r3, #516] ; 0x204
8000510: 1c5a adds r2, r3, #1
8000512: 490c ldr r1, [pc, #48] ; (8000544 <init_entropy+0x4c>)
8000514: f8c1 2204 str.w r2, [r1, #516] ; 0x204
8000518: 4618 mov r0, r3
800051a: f000 f815 bl 8000548 <generateEntropy>
s_entropy.pool_size++;
800051e: 4b09 ldr r3, [pc, #36] ; (8000544 <init_entropy+0x4c>)
8000520: f8d3 3200 ldr.w r3, [r3, #512] ; 0x200
8000524: 3301 adds r3, #1
8000526: 4a07 ldr r2, [pc, #28] ; (8000544 <init_entropy+0x4c>)
8000528: f8c2 3200 str.w r3, [r2, #512] ; 0x200
while(s_entropy.pool_size < BUFSIZE){
800052c: 4b05 ldr r3, [pc, #20] ; (8000544 <init_entropy+0x4c>)
800052e: f8d3 3200 ldr.w r3, [r3, #512] ; 0x200
8000532: 2b7f cmp r3, #127 ; 0x7f
8000534: dde9 ble.n 800050a <init_entropy+0x12>
// Add a delay for avoiding the same value
//delay(50);
}
/* We start at 0, ready for pickup to the pool */
s_entropy.position = 0;
8000536: 4b03 ldr r3, [pc, #12] ; (8000544 <init_entropy+0x4c>)
8000538: 2200 movs r2, #0
800053a: f8c3 2204 str.w r2, [r3, #516] ; 0x204
}
800053e: bf00 nop
8000540: bd80 pop {r7, pc}
8000542: bf00 nop
8000544: 200006e4 .word 0x200006e4
08000548 <generateEntropy>:
/*
* Generate a random value from the analog input
* Store the value in the entropy structure at the position specified in argument
*/
static void generateEntropy(int position){
8000548: b580 push {r7, lr}
800054a: b084 sub sp, #16
800054c: af00 add r7, sp, #0
800054e: 6078 str r0, [r7, #4]
unsigned int sensorValue = 0;
8000550: 2300 movs r3, #0
8000552: 60fb str r3, [r7, #12]
//RNG->CR|=RNG_CR_RNGEN;
RNG->CR = RNG_CR_RNGEN; /* RNG_CR_RNGEN -> 4 */
8000554: 4b19 ldr r3, [pc, #100] ; (80005bc <generateEntropy+0x74>)
8000556: 2204 movs r2, #4
8000558: 601a str r2, [r3, #0]
while (sensorValue == 0){
800055a: e027 b.n 80005ac <generateEntropy+0x64>
HAL_GPIO_TogglePin (GPIOB, GPIO_PIN_0);
800055c: 2101 movs r1, #1
800055e: 4818 ldr r0, [pc, #96] ; (80005c0 <generateEntropy+0x78>)
8000560: f001 fd51 bl 8002006 <HAL_GPIO_TogglePin>
HAL_Delay (100); /* Insert delay 100 ms */
8000564: 2064 movs r0, #100 ; 0x64
8000566: f000 ff2f bl 80013c8 <HAL_Delay>
// Wait until the data is ready
while (RNG_SR_DRDY == 0);
800056a: bf00 nop
uint32_t random = RNG->DR;
800056c: 4b13 ldr r3, [pc, #76] ; (80005bc <generateEntropy+0x74>)
800056e: 689b ldr r3, [r3, #8]
8000570: 60bb str r3, [r7, #8]
sensorValue = abs(random);
8000572: 68bb ldr r3, [r7, #8]
8000574: 2b00 cmp r3, #0
8000576: bfb8 it lt
8000578: 425b neglt r3, r3
800057a: 60fb str r3, [r7, #12]
if (sensorValue != 0){
800057c: 68fb ldr r3, [r7, #12]
800057e: 2b00 cmp r3, #0
8000580: d014 beq.n 80005ac <generateEntropy+0x64>
if(sensorValue <= 10)
8000582: 68fb ldr r3, [r7, #12]
8000584: 2b0a cmp r3, #10
8000586: d803 bhi.n 8000590 <generateEntropy+0x48>
sensorValue = sensorValue << 5;
8000588: 68fb ldr r3, [r7, #12]
800058a: 015b lsls r3, r3, #5
800058c: 60fb str r3, [r7, #12]
800058e: e008 b.n 80005a2 <generateEntropy+0x5a>
else if(sensorValue > 10 && sensorValue <= 100)
8000590: 68fb ldr r3, [r7, #12]
8000592: 2b0a cmp r3, #10
8000594: d905 bls.n 80005a2 <generateEntropy+0x5a>
8000596: 68fb ldr r3, [r7, #12]
8000598: 2b64 cmp r3, #100 ; 0x64
800059a: d802 bhi.n 80005a2 <generateEntropy+0x5a>
sensorValue = sensorValue << 4;
800059c: 68fb ldr r3, [r7, #12]
800059e: 011b lsls r3, r3, #4
80005a0: 60fb str r3, [r7, #12]
s_entropy.buf[position] = sensorValue;
80005a2: 4908 ldr r1, [pc, #32] ; (80005c4 <generateEntropy+0x7c>)
80005a4: 687b ldr r3, [r7, #4]
80005a6: 68fa ldr r2, [r7, #12]
80005a8: f841 2023 str.w r2, [r1, r3, lsl #2]
while (sensorValue == 0){
80005ac: 68fb ldr r3, [r7, #12]
80005ae: 2b00 cmp r3, #0
80005b0: d0d4 beq.n 800055c <generateEntropy+0x14>
}
}
}
80005b2: bf00 nop
80005b4: bf00 nop
80005b6: 3710 adds r7, #16
80005b8: 46bd mov sp, r7
80005ba: bd80 pop {r7, pc}
80005bc: 50060800 .word 0x50060800
80005c0: 40020400 .word 0x40020400
80005c4: 200006e4 .word 0x200006e4
080005c8 <prng>:
/*
* Pick a random data from the entropy pool
* This function is the API function to get the random number from the pool
*/
unsigned int prng(){
80005c8: b580 push {r7, lr}
80005ca: b082 sub sp, #8
80005cc: af00 add r7, sp, #0
unsigned int p = 0;
80005ce: 2300 movs r3, #0
80005d0: 607b str r3, [r7, #4]
if (s_entropy.position == BUFSIZE)
80005d2: 4b14 ldr r3, [pc, #80] ; (8000624 <prng+0x5c>)
80005d4: f8d3 3204 ldr.w r3, [r3, #516] ; 0x204
80005d8: 2b80 cmp r3, #128 ; 0x80
80005da: d103 bne.n 80005e4 <prng+0x1c>
s_entropy.position = 0;
80005dc: 4b11 ldr r3, [pc, #68] ; (8000624 <prng+0x5c>)
80005de: 2200 movs r2, #0
80005e0: f8c3 2204 str.w r2, [r3, #516] ; 0x204
// We consume the entropy
p = s_entropy.buf[s_entropy.position];
80005e4: 4b0f ldr r3, [pc, #60] ; (8000624 <prng+0x5c>)
80005e6: f8d3 3204 ldr.w r3, [r3, #516] ; 0x204
80005ea: 4a0e ldr r2, [pc, #56] ; (8000624 <prng+0x5c>)
80005ec: f852 3023 ldr.w r3, [r2, r3, lsl #2]
80005f0: 607b str r3, [r7, #4]
s_entropy.pool_size--;
80005f2: 4b0c ldr r3, [pc, #48] ; (8000624 <prng+0x5c>)
80005f4: f8d3 3200 ldr.w r3, [r3, #512] ; 0x200
80005f8: 3b01 subs r3, #1
80005fa: 4a0a ldr r2, [pc, #40] ; (8000624 <prng+0x5c>)
80005fc: f8c2 3200 str.w r3, [r2, #512] ; 0x200
// We have consumed the entropy, we replace the value by a new one
generateEntropy(s_entropy.position);
8000600: 4b08 ldr r3, [pc, #32] ; (8000624 <prng+0x5c>)
8000602: f8d3 3204 ldr.w r3, [r3, #516] ; 0x204
8000606: 4618 mov r0, r3
8000608: f7ff ff9e bl 8000548 <generateEntropy>
s_entropy.position++;
800060c: 4b05 ldr r3, [pc, #20] ; (8000624 <prng+0x5c>)
800060e: f8d3 3204 ldr.w r3, [r3, #516] ; 0x204
8000612: 3301 adds r3, #1
8000614: 4a03 ldr r2, [pc, #12] ; (8000624 <prng+0x5c>)
8000616: f8c2 3204 str.w r3, [r2, #516] ; 0x204
return p;
800061a: 687b ldr r3, [r7, #4]
}
800061c: 4618 mov r0, r3
800061e: 3708 adds r7, #8
8000620: 46bd mov sp, r7
8000622: bd80 pop {r7, pc}
8000624: 200006e4 .word 0x200006e4
08000628 <prime_number_finder>:
/*
* For the Blum-Blum-Shub, we need to find a prime number and must be congruent 3 modulo 4
*/
static void prime_number_finder(unsigned int *p){
8000628: b580 push {r7, lr}
800062a: b082 sub sp, #8
800062c: af00 add r7, sp, #0
800062e: 6078 str r0, [r7, #4]
while(!isPrimeNumber(*p) || (*p % 4 != 3))
8000630: e004 b.n 800063c <prime_number_finder+0x14>
*p += 1;
8000632: 687b ldr r3, [r7, #4]
8000634: 681b ldr r3, [r3, #0]
8000636: 1c5a adds r2, r3, #1
8000638: 687b ldr r3, [r7, #4]
800063a: 601a str r2, [r3, #0]
while(!isPrimeNumber(*p) || (*p % 4 != 3))
800063c: 687b ldr r3, [r7, #4]
800063e: 681b ldr r3, [r3, #0]
8000640: 4618 mov r0, r3
8000642: f000 f80f bl 8000664 <isPrimeNumber>
8000646: 4603 mov r3, r0
8000648: 2b00 cmp r3, #0
800064a: d0f2 beq.n 8000632 <prime_number_finder+0xa>
800064c: 687b ldr r3, [r7, #4]
800064e: 681b ldr r3, [r3, #0]
8000650: f003 0303 and.w r3, r3, #3
8000654: 2b03 cmp r3, #3
8000656: d1ec bne.n 8000632 <prime_number_finder+0xa>
}
8000658: bf00 nop
800065a: bf00 nop
800065c: 3708 adds r7, #8
800065e: 46bd mov sp, r7
8000660: bd80 pop {r7, pc}
...
08000664 <isPrimeNumber>:
/*
* Check if the number specified is a prime number
*/
static int isPrimeNumber(unsigned int x){
8000664: b480 push {r7}
8000666: b085 sub sp, #20
8000668: af00 add r7, sp, #0
800066a: 6078 str r0, [r7, #4]
for (int i = 0; i < SIEVES_LEN; i++){
800066c: 2300 movs r3, #0
800066e: 60fb str r3, [r7, #12]
8000670: e011 b.n 8000696 <isPrimeNumber+0x32>
if (x % sieves[i] == 0)
8000672: 4a0e ldr r2, [pc, #56] ; (80006ac <isPrimeNumber+0x48>)
8000674: 68fb ldr r3, [r7, #12]
8000676: f852 3023 ldr.w r3, [r2, r3, lsl #2]
800067a: 461a mov r2, r3
800067c: 687b ldr r3, [r7, #4]
800067e: fbb3 f1f2 udiv r1, r3, r2
8000682: fb01 f202 mul.w r2, r1, r2
8000686: 1a9b subs r3, r3, r2
8000688: 2b00 cmp r3, #0
800068a: d101 bne.n 8000690 <isPrimeNumber+0x2c>
return 0;
800068c: 2300 movs r3, #0
800068e: e007 b.n 80006a0 <isPrimeNumber+0x3c>
for (int i = 0; i < SIEVES_LEN; i++){
8000690: 68fb ldr r3, [r7, #12]
8000692: 3301 adds r3, #1
8000694: 60fb str r3, [r7, #12]
8000696: 68fb ldr r3, [r7, #12]
8000698: f5b3 7fd7 cmp.w r3, #430 ; 0x1ae
800069c: dbe9 blt.n 8000672 <isPrimeNumber+0xe>
}
return 1;
800069e: 2301 movs r3, #1
}
80006a0: 4618 mov r0, r3
80006a2: 3714 adds r7, #20
80006a4: 46bd mov sp, r7
80006a6: f85d 7b04 ldr.w r7, [sp], #4
80006aa: 4770 bx lr
80006ac: 20000000 .word 0x20000000
080006b0 <gcd>:
/*
* This function find the GCD
*/
static int gcd(unsigned long a, unsigned long b){
80006b0: b580 push {r7, lr}
80006b2: b082 sub sp, #8
80006b4: af00 add r7, sp, #0
80006b6: 6078 str r0, [r7, #4]
80006b8: 6039 str r1, [r7, #0]
if (b == 0)
80006ba: 683b ldr r3, [r7, #0]
80006bc: 2b00 cmp r3, #0
80006be: d101 bne.n 80006c4 <gcd+0x14>
return a;
80006c0: 687b ldr r3, [r7, #4]
80006c2: e00c b.n 80006de <gcd+0x2e>
return gcd(b, a % b);
80006c4: 687b ldr r3, [r7, #4]
80006c6: 683a ldr r2, [r7, #0]
80006c8: fbb3 f2f2 udiv r2, r3, r2
80006cc: 6839 ldr r1, [r7, #0]
80006ce: fb01 f202 mul.w r2, r1, r2
80006d2: 1a9b subs r3, r3, r2
80006d4: 4619 mov r1, r3
80006d6: 6838 ldr r0, [r7, #0]
80006d8: f7ff ffea bl 80006b0 <gcd>
80006dc: 4603 mov r3, r0
}
80006de: 4618 mov r0, r3
80006e0: 3708 adds r7, #8
80006e2: 46bd mov sp, r7
80006e4: bd80 pop {r7, pc}
...
080006e8 <random_range>:
unsigned int random_range(int min, int max){
80006e8: b480 push {r7}
80006ea: b085 sub sp, #20
80006ec: af00 add r7, sp, #0
80006ee: 6078 str r0, [r7, #4]
80006f0: 6039 str r1, [r7, #0]
// Wait until the data is ready
while (RNG_SR_DRDY == 0);
80006f2: bf00 nop
uint32_t random = RNG->DR;
80006f4: 4b08 ldr r3, [pc, #32] ; (8000718 <random_range+0x30>)
80006f6: 689b ldr r3, [r3, #8]
80006f8: 60fb str r3, [r7, #12]
return (random % max) + 1;
80006fa: 683a ldr r2, [r7, #0]
80006fc: 68fb ldr r3, [r7, #12]
80006fe: fbb3 f1f2 udiv r1, r3, r2
8000702: fb01 f202 mul.w r2, r1, r2
8000706: 1a9b subs r3, r3, r2
8000708: 3301 adds r3, #1
}
800070a: 4618 mov r0, r3
800070c: 3714 adds r7, #20
800070e: 46bd mov sp, r7
8000710: f85d 7b04 ldr.w r7, [sp], #4
8000714: 4770 bx lr
8000716: bf00 nop
8000718: 50060800 .word 0x50060800
0800071c <bbs>:
/*
* This function implement the Blum-Blum-Shub algorithm
* Based on the algorithm described in the Chapter 5:
* https://cacr.uwaterloo.ca/hac/about/chap5.pdf
*/
static unsigned long long bbs(unsigned int *p, unsigned int *q, unsigned long long *s){
800071c: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
8000720: b0c0 sub sp, #256 ; 0x100
8000722: af00 add r7, sp, #0
8000724: 64f8 str r0, [r7, #76] ; 0x4c
8000726: 64b9 str r1, [r7, #72] ; 0x48
8000728: 647a str r2, [r7, #68] ; 0x44
/* We pickup data from the entropy pool */
unsigned int p1 = prng();
800072a: f7ff ff4d bl 80005c8 <prng>
800072e: 4603 mov r3, r0
8000730: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
unsigned int p2 = prng();
8000734: f7ff ff48 bl 80005c8 <prng>
8000738: 4603 mov r3, r0
800073a: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8
unsigned long long n = 0, seed = 0;
800073e: f04f 0200 mov.w r2, #0
8000742: f04f 0300 mov.w r3, #0
8000746: e9c7 2334 strd r2, r3, [r7, #208] ; 0xd0
800074a: f04f 0200 mov.w r2, #0
800074e: f04f 0300 mov.w r3, #0
8000752: e9c7 233e strd r2, r3, [r7, #248] ; 0xf8
// We check if they are prime numbers
prime_number_finder(&p1);
8000756: f107 03bc add.w r3, r7, #188 ; 0xbc
800075a: 4618 mov r0, r3
800075c: f7ff ff64 bl 8000628 <prime_number_finder>
prime_number_finder(&p2);
8000760: f107 03b8 add.w r3, r7, #184 ; 0xb8
8000764: 4618 mov r0, r3
8000766: f7ff ff5f bl 8000628 <prime_number_finder>
*p = p1;
800076a: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
800076e: 6cfb ldr r3, [r7, #76] ; 0x4c
8000770: 601a str r2, [r3, #0]
*q = p2;
8000772: f8d7 20b8 ldr.w r2, [r7, #184] ; 0xb8
8000776: 6cbb ldr r3, [r7, #72] ; 0x48
8000778: 601a str r2, [r3, #0]
n = (unsigned long long)p1 * (unsigned long long)p2;
800077a: f8d7 30bc ldr.w r3, [r7, #188] ; 0xbc
800077e: 2200 movs r2, #0
8000780: 469a mov sl, r3
8000782: 4693 mov fp, r2
8000784: f8d7 30b8 ldr.w r3, [r7, #184] ; 0xb8
8000788: 2200 movs r2, #0
800078a: 4698 mov r8, r3
800078c: 4691 mov r9, r2
800078e: fb08 f20b mul.w r2, r8, fp
8000792: fb0a f309 mul.w r3, sl, r9
8000796: 4413 add r3, r2
8000798: fbaa 4508 umull r4, r5, sl, r8
800079c: 442b add r3, r5
800079e: 461d mov r5, r3
80007a0: e9c7 4534 strd r4, r5, [r7, #208] ; 0xd0
80007a4: e9c7 4534 strd r4, r5, [r7, #208] ; 0xd0
/*
* We need to find the seed
* between 1 < s < n - 1 and gcd(s, n) = 1
*/
seed = random_range(1, n);
80007a8: f8d7 30d0 ldr.w r3, [r7, #208] ; 0xd0
80007ac: 4619 mov r1, r3
80007ae: 2001 movs r0, #1
80007b0: f7ff ff9a bl 80006e8 <random_range>
80007b4: 4603 mov r3, r0
80007b6: 2200 movs r2, #0
80007b8: 61bb str r3, [r7, #24]
80007ba: 61fa str r2, [r7, #28]
80007bc: e9d7 3406 ldrd r3, r4, [r7, #24]
80007c0: e9c7 343e strd r3, r4, [r7, #248] ; 0xf8
while (gcd(seed, n) != 1)
80007c4: e00a b.n 80007dc <bbs+0xc0>
seed += 1;
80007c6: e9d7 233e ldrd r2, r3, [r7, #248] ; 0xf8
80007ca: 1c51 adds r1, r2, #1
80007cc: 6139 str r1, [r7, #16]
80007ce: f143 0300 adc.w r3, r3, #0
80007d2: 617b str r3, [r7, #20]
80007d4: e9d7 3404 ldrd r3, r4, [r7, #16]
80007d8: e9c7 343e strd r3, r4, [r7, #248] ; 0xf8
while (gcd(seed, n) != 1)
80007dc: f8d7 20f8 ldr.w r2, [r7, #248] ; 0xf8
80007e0: f8d7 30d0 ldr.w r3, [r7, #208] ; 0xd0
80007e4: 4619 mov r1, r3
80007e6: 4610 mov r0, r2
80007e8: f7ff ff62 bl 80006b0 <gcd>
80007ec: 4603 mov r3, r0
80007ee: 2b01 cmp r3, #1
80007f0: d1e9 bne.n 80007c6 <bbs+0xaa>
*s = seed;
80007f2: 6c79 ldr r1, [r7, #68] ; 0x44
80007f4: e9d7 233e ldrd r2, r3, [r7, #248] ; 0xf8
80007f8: e9c1 2300 strd r2, r3, [r1]
unsigned long long x0 = (seed * seed) % n;
80007fc: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc
8000800: f8d7 20f8 ldr.w r2, [r7, #248] ; 0xf8
8000804: fb02 f103 mul.w r1, r2, r3
8000808: f8d7 20fc ldr.w r2, [r7, #252] ; 0xfc
800080c: f8d7 30f8 ldr.w r3, [r7, #248] ; 0xf8
8000810: fb02 f303 mul.w r3, r2, r3
8000814: 18ca adds r2, r1, r3
8000816: f8d7 30f8 ldr.w r3, [r7, #248] ; 0xf8
800081a: fba3 1303 umull r1, r3, r3, r3
800081e: 63fb str r3, [r7, #60] ; 0x3c
8000820: 460b mov r3, r1
8000822: 63bb str r3, [r7, #56] ; 0x38
8000824: 6bfb ldr r3, [r7, #60] ; 0x3c
8000826: 18d3 adds r3, r2, r3
8000828: 63fb str r3, [r7, #60] ; 0x3c
800082a: e9d7 2334 ldrd r2, r3, [r7, #208] ; 0xd0
800082e: e9d7 010e ldrd r0, r1, [r7, #56] ; 0x38
8000832: f7ff fce3 bl 80001fc <__aeabi_uldivmod>
8000836: e9c7 2332 strd r2, r3, [r7, #200] ; 0xc8
unsigned long long tmp = x0;
800083a: e9d7 2332 ldrd r2, r3, [r7, #200] ; 0xc8
800083e: e9c7 233c strd r2, r3, [r7, #240] ; 0xf0
char output[ITER_BBS];
memset(output, 0, ITER_BBS);
8000842: f107 0354 add.w r3, r7, #84 ; 0x54
8000846: 2264 movs r2, #100 ; 0x64
8000848: 2100 movs r1, #0
800084a: 4618 mov r0, r3
800084c: f003 f96e bl 8003b2c <memset>
int pos = 0;
8000850: 2300 movs r3, #0
8000852: f8c7 30ec str.w r3, [r7, #236] ; 0xec
for (size_t i = 1; i < ITER_BBS; i++){
8000856: 2301 movs r3, #1
8000858: f8c7 30e8 str.w r3, [r7, #232] ; 0xe8
800085c: e039 b.n 80008d2 <bbs+0x1b6>
unsigned long long x = (tmp * tmp) % n;
800085e: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8000862: f8d7 20f0 ldr.w r2, [r7, #240] ; 0xf0
8000866: fb03 f202 mul.w r2, r3, r2
800086a: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
800086e: f8d7 10f0 ldr.w r1, [r7, #240] ; 0xf0
8000872: fb01 f303 mul.w r3, r1, r3
8000876: 441a add r2, r3
8000878: f8d7 30f0 ldr.w r3, [r7, #240] ; 0xf0
800087c: fba3 1303 umull r1, r3, r3, r3
8000880: 637b str r3, [r7, #52] ; 0x34
8000882: 460b mov r3, r1
8000884: 633b str r3, [r7, #48] ; 0x30
8000886: 6b7b ldr r3, [r7, #52] ; 0x34
8000888: 18d3 adds r3, r2, r3
800088a: 637b str r3, [r7, #52] ; 0x34
800088c: e9d7 2334 ldrd r2, r3, [r7, #208] ; 0xd0
8000890: e9d7 010c ldrd r0, r1, [r7, #48] ; 0x30
8000894: f7ff fcb2 bl 80001fc <__aeabi_uldivmod>
8000898: e9c7 2330 strd r2, r3, [r7, #192] ; 0xc0
output[pos++] = (x & 1) + '0';
800089c: f897 30c0 ldrb.w r3, [r7, #192] ; 0xc0
80008a0: f003 0301 and.w r3, r3, #1
80008a4: b2da uxtb r2, r3
80008a6: f8d7 30ec ldr.w r3, [r7, #236] ; 0xec
80008aa: 1c59 adds r1, r3, #1
80008ac: f8c7 10ec str.w r1, [r7, #236] ; 0xec
80008b0: 3230 adds r2, #48 ; 0x30
80008b2: b2d2 uxtb r2, r2
80008b4: 33c0 adds r3, #192 ; 0xc0
80008b6: f107 0140 add.w r1, r7, #64 ; 0x40
80008ba: 440b add r3, r1
80008bc: f803 2cac strb.w r2, [r3, #-172]
tmp = x;
80008c0: e9d7 2330 ldrd r2, r3, [r7, #192] ; 0xc0
80008c4: e9c7 233c strd r2, r3, [r7, #240] ; 0xf0
for (size_t i = 1; i < ITER_BBS; i++){
80008c8: f8d7 30e8 ldr.w r3, [r7, #232] ; 0xe8
80008cc: 3301 adds r3, #1
80008ce: f8c7 30e8 str.w r3, [r7, #232] ; 0xe8
80008d2: f8d7 30e8 ldr.w r3, [r7, #232] ; 0xe8
80008d6: 2b63 cmp r3, #99 ; 0x63
80008d8: d9c1 bls.n 800085e <bbs+0x142>
}
/* We convert the bit sequence to unsigned long long */
unsigned long long res = 0;
80008da: f04f 0200 mov.w r2, #0
80008de: f04f 0300 mov.w r3, #0
80008e2: e9c7 2338 strd r2, r3, [r7, #224] ; 0xe0
for (int i = 0; i < strlen(output); i++)
80008e6: 2300 movs r3, #0
80008e8: f8c7 30dc str.w r3, [r7, #220] ; 0xdc
80008ec: e02b b.n 8000946 <bbs+0x22a>
res = (res << 1) + output[i] - '0';
80008ee: e9d7 2338 ldrd r2, r3, [r7, #224] ; 0xe0
80008f2: 1891 adds r1, r2, r2
80008f4: 60b9 str r1, [r7, #8]
80008f6: 415b adcs r3, r3
80008f8: 60fb str r3, [r7, #12]
80008fa: e9d7 2302 ldrd r2, r3, [r7, #8]
80008fe: f107 0054 add.w r0, r7, #84 ; 0x54
8000902: f8d7 10dc ldr.w r1, [r7, #220] ; 0xdc
8000906: 4401 add r1, r0
8000908: 7809 ldrb r1, [r1, #0]
800090a: b2c9 uxtb r1, r1
800090c: 2000 movs r0, #0
800090e: 62b9 str r1, [r7, #40] ; 0x28
8000910: 62f8 str r0, [r7, #44] ; 0x2c
8000912: e9d7 450a ldrd r4, r5, [r7, #40] ; 0x28
8000916: 4621 mov r1, r4
8000918: 1851 adds r1, r2, r1
800091a: 6239 str r1, [r7, #32]
800091c: 4629 mov r1, r5
800091e: 414b adcs r3, r1
8000920: 627b str r3, [r7, #36] ; 0x24
8000922: e9d7 1208 ldrd r1, r2, [r7, #32]
8000926: 460b mov r3, r1
8000928: 3b30 subs r3, #48 ; 0x30
800092a: 603b str r3, [r7, #0]
800092c: 4613 mov r3, r2
800092e: f143 33ff adc.w r3, r3, #4294967295 ; 0xffffffff
8000932: 607b str r3, [r7, #4]
8000934: e9d7 3400 ldrd r3, r4, [r7]
8000938: e9c7 3438 strd r3, r4, [r7, #224] ; 0xe0
for (int i = 0; i < strlen(output); i++)
800093c: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc
8000940: 3301 adds r3, #1
8000942: f8c7 30dc str.w r3, [r7, #220] ; 0xdc
8000946: f107 0354 add.w r3, r7, #84 ; 0x54
800094a: 4618 mov r0, r3
800094c: f7ff fc4e bl 80001ec <strlen>
8000950: 4602 mov r2, r0
8000952: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc
8000956: 429a cmp r2, r3
8000958: d8c9 bhi.n 80008ee <bbs+0x1d2>
return res;
800095a: e9d7 2338 ldrd r2, r3, [r7, #224] ; 0xe0
}
800095e: 4610 mov r0, r2
8000960: 4619 mov r1, r3
8000962: f507 7780 add.w r7, r7, #256 ; 0x100
8000966: 46bd mov sp, r7
8000968: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
0800096c <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
800096c: b5b0 push {r4, r5, r7, lr}
800096e: b094 sub sp, #80 ; 0x50
8000970: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
8000972: f000 fcb7 bl 80012e4 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
8000976: f000 f863 bl 8000a40 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
800097a: f000 f9af bl 8000cdc <MX_GPIO_Init>
MX_ETH_Init();
800097e: f000 f8c9 bl 8000b14 <MX_ETH_Init>
MX_USART3_UART_Init();
8000982: f000 f929 bl 8000bd8 <MX_USART3_UART_Init>
MX_USB_OTG_FS_PCD_Init();
8000986: f000 f97b bl 8000c80 <MX_USB_OTG_FS_PCD_Init>
MX_RNG_Init();
800098a: f000 f911 bl 8000bb0 <MX_RNG_Init>
MX_USART6_UART_Init();
800098e: f000 f94d bl 8000c2c <MX_USART6_UART_Init>
/* USER CODE BEGIN 2 */
init_entropy();
8000992: f7ff fdb1 bl 80004f8 <init_entropy>
while (1)
{
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
HAL_StatusTypeDef status = HAL_UART_Receive(&huart6, buf_recv, sizeof(struct cmd), 100);
8000996: f107 011c add.w r1, r7, #28
800099a: 2364 movs r3, #100 ; 0x64
800099c: 2208 movs r2, #8
800099e: 4826 ldr r0, [pc, #152] ; (8000a38 <main+0xcc>)
80009a0: f002 f9f7 bl 8002d92 <HAL_UART_Receive>
80009a4: 4603 mov r3, r0
80009a6: f887 304f strb.w r3, [r7, #79] ; 0x4f
if (status == HAL_OK){
80009aa: f897 304f ldrb.w r3, [r7, #79] ; 0x4f
80009ae: 2b00 cmp r3, #0
80009b0: d1f1 bne.n 8000996 <main+0x2a>
struct cmd *s_cmd = (struct cmd *)buf_recv;
80009b2: f107 031c add.w r3, r7, #28
80009b6: 64bb str r3, [r7, #72] ; 0x48
if (s_cmd->cmd == CSPRNG_CMD_GET_RNG){
80009b8: 6cbb ldr r3, [r7, #72] ; 0x48
80009ba: 685b ldr r3, [r3, #4]
80009bc: 2b10 cmp r3, #16
80009be: d1ea bne.n 8000996 <main+0x2a>
struct prng s_prng = {0};
80009c0: 463b mov r3, r7
80009c2: 2200 movs r2, #0
80009c4: 601a str r2, [r3, #0]
80009c6: 605a str r2, [r3, #4]
80009c8: 609a str r2, [r3, #8]
80009ca: 60da str r2, [r3, #12]
80009cc: 611a str r2, [r3, #16]
80009ce: 615a str r2, [r3, #20]
memset(buffer, 0, sizeof(struct prng));
80009d0: f107 0324 add.w r3, r7, #36 ; 0x24
80009d4: 2218 movs r2, #24
80009d6: 2100 movs r1, #0
80009d8: 4618 mov r0, r3
80009da: f003 f8a7 bl 8003b2c <memset>
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_0, GPIO_PIN_SET);
80009de: 2201 movs r2, #1
80009e0: 2101 movs r1, #1
80009e2: 4816 ldr r0, [pc, #88] ; (8000a3c <main+0xd0>)
80009e4: f001 faf6 bl 8001fd4 <HAL_GPIO_WritePin>
unsigned long long random = bbs(&s_prng.p, &s_prng.q, &s_prng.seed);
80009e8: 463b mov r3, r7
80009ea: f103 0208 add.w r2, r3, #8
80009ee: 463b mov r3, r7
80009f0: 1d19 adds r1, r3, #4
80009f2: 463b mov r3, r7
80009f4: 4618 mov r0, r3
80009f6: f7ff fe91 bl 800071c <bbs>
80009fa: e9c7 0110 strd r0, r1, [r7, #64] ; 0x40
s_prng.output = random;
80009fe: e9d7 2310 ldrd r2, r3, [r7, #64] ; 0x40
8000a02: e9c7 2304 strd r2, r3, [r7, #16]
memcpy(buffer, &s_prng, sizeof(struct prng));
8000a06: f107 0424 add.w r4, r7, #36 ; 0x24
8000a0a: 463d mov r5, r7
8000a0c: cd0f ldmia r5!, {r0, r1, r2, r3}
8000a0e: c40f stmia r4!, {r0, r1, r2, r3}
8000a10: e895 0003 ldmia.w r5, {r0, r1}
8000a14: e884 0003 stmia.w r4, {r0, r1}
HAL_StatusTypeDef s = HAL_UART_Transmit(&huart6, buffer, sizeof(struct prng), 0xF);
8000a18: f107 0124 add.w r1, r7, #36 ; 0x24
8000a1c: 230f movs r3, #15
8000a1e: 2218 movs r2, #24
8000a20: 4805 ldr r0, [pc, #20] ; (8000a38 <main+0xcc>)
8000a22: f002 f92b bl 8002c7c <HAL_UART_Transmit>
8000a26: 4603 mov r3, r0
8000a28: f887 303f strb.w r3, [r7, #63] ; 0x3f
// We have finished, we disable the pin
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_0, GPIO_PIN_RESET);
8000a2c: 2200 movs r2, #0
8000a2e: 2101 movs r1, #1
8000a30: 4802 ldr r0, [pc, #8] ; (8000a3c <main+0xd0>)
8000a32: f001 facf bl 8001fd4 <HAL_GPIO_WritePin>
{
8000a36: e7ae b.n 8000996 <main+0x2a>
8000a38: 20000b6c .word 0x20000b6c
8000a3c: 40020400 .word 0x40020400
08000a40 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8000a40: b580 push {r7, lr}
8000a42: b094 sub sp, #80 ; 0x50
8000a44: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8000a46: f107 0320 add.w r3, r7, #32
8000a4a: 2230 movs r2, #48 ; 0x30
8000a4c: 2100 movs r1, #0
8000a4e: 4618 mov r0, r3
8000a50: f003 f86c bl 8003b2c <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8000a54: f107 030c add.w r3, r7, #12
8000a58: 2200 movs r2, #0
8000a5a: 601a str r2, [r3, #0]
8000a5c: 605a str r2, [r3, #4]
8000a5e: 609a str r2, [r3, #8]
8000a60: 60da str r2, [r3, #12]
8000a62: 611a str r2, [r3, #16]
/** Configure the main internal regulator output voltage
*/
__HAL_RCC_PWR_CLK_ENABLE();
8000a64: 2300 movs r3, #0
8000a66: 60bb str r3, [r7, #8]
8000a68: 4b28 ldr r3, [pc, #160] ; (8000b0c <SystemClock_Config+0xcc>)
8000a6a: 6c1b ldr r3, [r3, #64] ; 0x40
8000a6c: 4a27 ldr r2, [pc, #156] ; (8000b0c <SystemClock_Config+0xcc>)
8000a6e: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8000a72: 6413 str r3, [r2, #64] ; 0x40
8000a74: 4b25 ldr r3, [pc, #148] ; (8000b0c <SystemClock_Config+0xcc>)
8000a76: 6c1b ldr r3, [r3, #64] ; 0x40
8000a78: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8000a7c: 60bb str r3, [r7, #8]
8000a7e: 68bb ldr r3, [r7, #8]
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
8000a80: 2300 movs r3, #0
8000a82: 607b str r3, [r7, #4]
8000a84: 4b22 ldr r3, [pc, #136] ; (8000b10 <SystemClock_Config+0xd0>)
8000a86: 681b ldr r3, [r3, #0]
8000a88: 4a21 ldr r2, [pc, #132] ; (8000b10 <SystemClock_Config+0xd0>)
8000a8a: f443 4340 orr.w r3, r3, #49152 ; 0xc000
8000a8e: 6013 str r3, [r2, #0]
8000a90: 4b1f ldr r3, [pc, #124] ; (8000b10 <SystemClock_Config+0xd0>)
8000a92: 681b ldr r3, [r3, #0]
8000a94: f403 4340 and.w r3, r3, #49152 ; 0xc000
8000a98: 607b str r3, [r7, #4]
8000a9a: 687b ldr r3, [r7, #4]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
8000a9c: 2301 movs r3, #1
8000a9e: 623b str r3, [r7, #32]
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
8000aa0: f44f 23a0 mov.w r3, #327680 ; 0x50000
8000aa4: 627b str r3, [r7, #36] ; 0x24
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
8000aa6: 2302 movs r3, #2
8000aa8: 63bb str r3, [r7, #56] ; 0x38
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
8000aaa: f44f 0380 mov.w r3, #4194304 ; 0x400000
8000aae: 63fb str r3, [r7, #60] ; 0x3c
RCC_OscInitStruct.PLL.PLLM = 4;
8000ab0: 2304 movs r3, #4
8000ab2: 643b str r3, [r7, #64] ; 0x40
RCC_OscInitStruct.PLL.PLLN = 168;
8000ab4: 23a8 movs r3, #168 ; 0xa8
8000ab6: 647b str r3, [r7, #68] ; 0x44
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
8000ab8: 2302 movs r3, #2
8000aba: 64bb str r3, [r7, #72] ; 0x48
RCC_OscInitStruct.PLL.PLLQ = 7;
8000abc: 2307 movs r3, #7
8000abe: 64fb str r3, [r7, #76] ; 0x4c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
8000ac0: f107 0320 add.w r3, r7, #32
8000ac4: 4618 mov r0, r3
8000ac6: f001 fbc7 bl 8002258 <HAL_RCC_OscConfig>
8000aca: 4603 mov r3, r0
8000acc: 2b00 cmp r3, #0
8000ace: d001 beq.n 8000ad4 <SystemClock_Config+0x94>
{
Error_Handler();
8000ad0: f000 f9b2 bl 8000e38 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
8000ad4: 230f movs r3, #15
8000ad6: 60fb str r3, [r7, #12]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
8000ad8: 2302 movs r3, #2
8000ada: 613b str r3, [r7, #16]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8000adc: 2300 movs r3, #0
8000ade: 617b str r3, [r7, #20]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
8000ae0: f44f 53a0 mov.w r3, #5120 ; 0x1400
8000ae4: 61bb str r3, [r7, #24]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
8000ae6: f44f 5380 mov.w r3, #4096 ; 0x1000
8000aea: 61fb str r3, [r7, #28]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
8000aec: f107 030c add.w r3, r7, #12
8000af0: 2105 movs r1, #5
8000af2: 4618 mov r0, r3
8000af4: f001 fe28 bl 8002748 <HAL_RCC_ClockConfig>
8000af8: 4603 mov r3, r0
8000afa: 2b00 cmp r3, #0
8000afc: d001 beq.n 8000b02 <SystemClock_Config+0xc2>
{
Error_Handler();
8000afe: f000 f99b bl 8000e38 <Error_Handler>
}
}
8000b02: bf00 nop
8000b04: 3750 adds r7, #80 ; 0x50
8000b06: 46bd mov sp, r7
8000b08: bd80 pop {r7, pc}
8000b0a: bf00 nop
8000b0c: 40023800 .word 0x40023800
8000b10: 40007000 .word 0x40007000
08000b14 <MX_ETH_Init>:
* @brief ETH Initialization Function
* @param None
* @retval None
*/
static void MX_ETH_Init(void)
{
8000b14: b580 push {r7, lr}
8000b16: af00 add r7, sp, #0
static uint8_t MACAddr[6];
/* USER CODE BEGIN ETH_Init 1 */
/* USER CODE END ETH_Init 1 */
heth.Instance = ETH;
8000b18: 4b1f ldr r3, [pc, #124] ; (8000b98 <MX_ETH_Init+0x84>)
8000b1a: 4a20 ldr r2, [pc, #128] ; (8000b9c <MX_ETH_Init+0x88>)
8000b1c: 601a str r2, [r3, #0]
MACAddr[0] = 0x00;
8000b1e: 4b20 ldr r3, [pc, #128] ; (8000ba0 <MX_ETH_Init+0x8c>)
8000b20: 2200 movs r2, #0
8000b22: 701a strb r2, [r3, #0]
MACAddr[1] = 0x80;
8000b24: 4b1e ldr r3, [pc, #120] ; (8000ba0 <MX_ETH_Init+0x8c>)
8000b26: 2280 movs r2, #128 ; 0x80
8000b28: 705a strb r2, [r3, #1]
MACAddr[2] = 0xE1;
8000b2a: 4b1d ldr r3, [pc, #116] ; (8000ba0 <MX_ETH_Init+0x8c>)
8000b2c: 22e1 movs r2, #225 ; 0xe1
8000b2e: 709a strb r2, [r3, #2]
MACAddr[3] = 0x00;
8000b30: 4b1b ldr r3, [pc, #108] ; (8000ba0 <MX_ETH_Init+0x8c>)
8000b32: 2200 movs r2, #0
8000b34: 70da strb r2, [r3, #3]
MACAddr[4] = 0x00;
8000b36: 4b1a ldr r3, [pc, #104] ; (8000ba0 <MX_ETH_Init+0x8c>)
8000b38: 2200 movs r2, #0
8000b3a: 711a strb r2, [r3, #4]
MACAddr[5] = 0x00;
8000b3c: 4b18 ldr r3, [pc, #96] ; (8000ba0 <MX_ETH_Init+0x8c>)
8000b3e: 2200 movs r2, #0
8000b40: 715a strb r2, [r3, #5]
heth.Init.MACAddr = &MACAddr[0];
8000b42: 4b15 ldr r3, [pc, #84] ; (8000b98 <MX_ETH_Init+0x84>)
8000b44: 4a16 ldr r2, [pc, #88] ; (8000ba0 <MX_ETH_Init+0x8c>)
8000b46: 605a str r2, [r3, #4]
heth.Init.MediaInterface = HAL_ETH_RMII_MODE;
8000b48: 4b13 ldr r3, [pc, #76] ; (8000b98 <MX_ETH_Init+0x84>)
8000b4a: f44f 0200 mov.w r2, #8388608 ; 0x800000
8000b4e: 609a str r2, [r3, #8]
heth.Init.TxDesc = DMATxDscrTab;
8000b50: 4b11 ldr r3, [pc, #68] ; (8000b98 <MX_ETH_Init+0x84>)
8000b52: 4a14 ldr r2, [pc, #80] ; (8000ba4 <MX_ETH_Init+0x90>)
8000b54: 60da str r2, [r3, #12]
heth.Init.RxDesc = DMARxDscrTab;
8000b56: 4b10 ldr r3, [pc, #64] ; (8000b98 <MX_ETH_Init+0x84>)
8000b58: 4a13 ldr r2, [pc, #76] ; (8000ba8 <MX_ETH_Init+0x94>)
8000b5a: 611a str r2, [r3, #16]
heth.Init.RxBuffLen = 1524;
8000b5c: 4b0e ldr r3, [pc, #56] ; (8000b98 <MX_ETH_Init+0x84>)
8000b5e: f240 52f4 movw r2, #1524 ; 0x5f4
8000b62: 615a str r2, [r3, #20]
/* USER CODE BEGIN MACADDRESS */
/* USER CODE END MACADDRESS */
if (HAL_ETH_Init(&heth) != HAL_OK)
8000b64: 480c ldr r0, [pc, #48] ; (8000b98 <MX_ETH_Init+0x84>)
8000b66: f000 fd39 bl 80015dc <HAL_ETH_Init>
8000b6a: 4603 mov r3, r0
8000b6c: 2b00 cmp r3, #0
8000b6e: d001 beq.n 8000b74 <MX_ETH_Init+0x60>
{
Error_Handler();
8000b70: f000 f962 bl 8000e38 <Error_Handler>
}
memset(&TxConfig, 0 , sizeof(ETH_TxPacketConfig));
8000b74: 2238 movs r2, #56 ; 0x38
8000b76: 2100 movs r1, #0
8000b78: 480c ldr r0, [pc, #48] ; (8000bac <MX_ETH_Init+0x98>)
8000b7a: f002 ffd7 bl 8003b2c <memset>
TxConfig.Attributes = ETH_TX_PACKETS_FEATURES_CSUM | ETH_TX_PACKETS_FEATURES_CRCPAD;
8000b7e: 4b0b ldr r3, [pc, #44] ; (8000bac <MX_ETH_Init+0x98>)
8000b80: 2221 movs r2, #33 ; 0x21
8000b82: 601a str r2, [r3, #0]
TxConfig.ChecksumCtrl = ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC;
8000b84: 4b09 ldr r3, [pc, #36] ; (8000bac <MX_ETH_Init+0x98>)
8000b86: f44f 0240 mov.w r2, #12582912 ; 0xc00000
8000b8a: 615a str r2, [r3, #20]
TxConfig.CRCPadCtrl = ETH_CRC_PAD_INSERT;
8000b8c: 4b07 ldr r3, [pc, #28] ; (8000bac <MX_ETH_Init+0x98>)
8000b8e: 2200 movs r2, #0
8000b90: 611a str r2, [r3, #16]
/* USER CODE BEGIN ETH_Init 2 */
/* USER CODE END ETH_Init 2 */
}
8000b92: bf00 nop
8000b94: bd80 pop {r7, pc}
8000b96: bf00 nop
8000b98: 20000a64 .word 0x20000a64
8000b9c: 40028000 .word 0x40028000
8000ba0: 20001098 .word 0x20001098
8000ba4: 200009c4 .word 0x200009c4
8000ba8: 20000924 .word 0x20000924
8000bac: 200008ec .word 0x200008ec
08000bb0 <MX_RNG_Init>:
* @brief RNG Initialization Function
* @param None
* @retval None
*/
static void MX_RNG_Init(void)
{
8000bb0: b580 push {r7, lr}
8000bb2: af00 add r7, sp, #0
/* USER CODE END RNG_Init 0 */
/* USER CODE BEGIN RNG_Init 1 */
/* USER CODE END RNG_Init 1 */
hrng.Instance = RNG;
8000bb4: 4b06 ldr r3, [pc, #24] ; (8000bd0 <MX_RNG_Init+0x20>)
8000bb6: 4a07 ldr r2, [pc, #28] ; (8000bd4 <MX_RNG_Init+0x24>)
8000bb8: 601a str r2, [r3, #0]
if (HAL_RNG_Init(&hrng) != HAL_OK)
8000bba: 4805 ldr r0, [pc, #20] ; (8000bd0 <MX_RNG_Init+0x20>)
8000bbc: f001 ffe4 bl 8002b88 <HAL_RNG_Init>
8000bc0: 4603 mov r3, r0
8000bc2: 2b00 cmp r3, #0
8000bc4: d001 beq.n 8000bca <MX_RNG_Init+0x1a>
{
Error_Handler();
8000bc6: f000 f937 bl 8000e38 <Error_Handler>
}
/* USER CODE BEGIN RNG_Init 2 */
/* USER CODE END RNG_Init 2 */
}
8000bca: bf00 nop
8000bcc: bd80 pop {r7, pc}
8000bce: bf00 nop
8000bd0: 20000b14 .word 0x20000b14
8000bd4: 50060800 .word 0x50060800
08000bd8 <MX_USART3_UART_Init>:
* @brief USART3 Initialization Function
* @param None
* @retval None
*/
static void MX_USART3_UART_Init(void)
{
8000bd8: b580 push {r7, lr}
8000bda: af00 add r7, sp, #0
/* USER CODE END USART3_Init 0 */
/* USER CODE BEGIN USART3_Init 1 */
/* USER CODE END USART3_Init 1 */
huart3.Instance = USART3;
8000bdc: 4b11 ldr r3, [pc, #68] ; (8000c24 <MX_USART3_UART_Init+0x4c>)
8000bde: 4a12 ldr r2, [pc, #72] ; (8000c28 <MX_USART3_UART_Init+0x50>)
8000be0: 601a str r2, [r3, #0]
huart3.Init.BaudRate = 115200;
8000be2: 4b10 ldr r3, [pc, #64] ; (8000c24 <MX_USART3_UART_Init+0x4c>)
8000be4: f44f 32e1 mov.w r2, #115200 ; 0x1c200
8000be8: 605a str r2, [r3, #4]
huart3.Init.WordLength = UART_WORDLENGTH_8B;
8000bea: 4b0e ldr r3, [pc, #56] ; (8000c24 <MX_USART3_UART_Init+0x4c>)
8000bec: 2200 movs r2, #0
8000bee: 609a str r2, [r3, #8]
huart3.Init.StopBits = UART_STOPBITS_1;
8000bf0: 4b0c ldr r3, [pc, #48] ; (8000c24 <MX_USART3_UART_Init+0x4c>)
8000bf2: 2200 movs r2, #0
8000bf4: 60da str r2, [r3, #12]
huart3.Init.Parity = UART_PARITY_NONE;
8000bf6: 4b0b ldr r3, [pc, #44] ; (8000c24 <MX_USART3_UART_Init+0x4c>)
8000bf8: 2200 movs r2, #0
8000bfa: 611a str r2, [r3, #16]
huart3.Init.Mode = UART_MODE_TX_RX;
8000bfc: 4b09 ldr r3, [pc, #36] ; (8000c24 <MX_USART3_UART_Init+0x4c>)
8000bfe: 220c movs r2, #12
8000c00: 615a str r2, [r3, #20]
huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE;
8000c02: 4b08 ldr r3, [pc, #32] ; (8000c24 <MX_USART3_UART_Init+0x4c>)
8000c04: 2200 movs r2, #0
8000c06: 619a str r2, [r3, #24]
huart3.Init.OverSampling = UART_OVERSAMPLING_16;
8000c08: 4b06 ldr r3, [pc, #24] ; (8000c24 <MX_USART3_UART_Init+0x4c>)
8000c0a: 2200 movs r2, #0
8000c0c: 61da str r2, [r3, #28]
if (HAL_UART_Init(&huart3) != HAL_OK)
8000c0e: 4805 ldr r0, [pc, #20] ; (8000c24 <MX_USART3_UART_Init+0x4c>)
8000c10: f001 ffe4 bl 8002bdc <HAL_UART_Init>
8000c14: 4603 mov r3, r0
8000c16: 2b00 cmp r3, #0
8000c18: d001 beq.n 8000c1e <MX_USART3_UART_Init+0x46>
{
Error_Handler();
8000c1a: f000 f90d bl 8000e38 <Error_Handler>
}
/* USER CODE BEGIN USART3_Init 2 */
/* USER CODE END USART3_Init 2 */
}
8000c1e: bf00 nop
8000c20: bd80 pop {r7, pc}
8000c22: bf00 nop
8000c24: 20000b24 .word 0x20000b24
8000c28: 40004800 .word 0x40004800
08000c2c <MX_USART6_UART_Init>:
* @brief USART6 Initialization Function
* @param None
* @retval None
*/
static void MX_USART6_UART_Init(void)
{
8000c2c: b580 push {r7, lr}
8000c2e: af00 add r7, sp, #0
/* USER CODE END USART6_Init 0 */
/* USER CODE BEGIN USART6_Init 1 */
/* USER CODE END USART6_Init 1 */
huart6.Instance = USART6;
8000c30: 4b11 ldr r3, [pc, #68] ; (8000c78 <MX_USART6_UART_Init+0x4c>)
8000c32: 4a12 ldr r2, [pc, #72] ; (8000c7c <MX_USART6_UART_Init+0x50>)
8000c34: 601a str r2, [r3, #0]
huart6.Init.BaudRate = 115200;
8000c36: 4b10 ldr r3, [pc, #64] ; (8000c78 <MX_USART6_UART_Init+0x4c>)
8000c38: f44f 32e1 mov.w r2, #115200 ; 0x1c200
8000c3c: 605a str r2, [r3, #4]
huart6.Init.WordLength = UART_WORDLENGTH_8B;
8000c3e: 4b0e ldr r3, [pc, #56] ; (8000c78 <MX_USART6_UART_Init+0x4c>)
8000c40: 2200 movs r2, #0
8000c42: 609a str r2, [r3, #8]
huart6.Init.StopBits = UART_STOPBITS_1;
8000c44: 4b0c ldr r3, [pc, #48] ; (8000c78 <MX_USART6_UART_Init+0x4c>)
8000c46: 2200 movs r2, #0
8000c48: 60da str r2, [r3, #12]
huart6.Init.Parity = UART_PARITY_NONE;
8000c4a: 4b0b ldr r3, [pc, #44] ; (8000c78 <MX_USART6_UART_Init+0x4c>)
8000c4c: 2200 movs r2, #0
8000c4e: 611a str r2, [r3, #16]
huart6.Init.Mode = UART_MODE_TX_RX;
8000c50: 4b09 ldr r3, [pc, #36] ; (8000c78 <MX_USART6_UART_Init+0x4c>)
8000c52: 220c movs r2, #12
8000c54: 615a str r2, [r3, #20]
huart6.Init.HwFlowCtl = UART_HWCONTROL_NONE;
8000c56: 4b08 ldr r3, [pc, #32] ; (8000c78 <MX_USART6_UART_Init+0x4c>)
8000c58: 2200 movs r2, #0
8000c5a: 619a str r2, [r3, #24]
huart6.Init.OverSampling = UART_OVERSAMPLING_16;
8000c5c: 4b06 ldr r3, [pc, #24] ; (8000c78 <MX_USART6_UART_Init+0x4c>)
8000c5e: 2200 movs r2, #0
8000c60: 61da str r2, [r3, #28]
if (HAL_UART_Init(&huart6) != HAL_OK)
8000c62: 4805 ldr r0, [pc, #20] ; (8000c78 <MX_USART6_UART_Init+0x4c>)
8000c64: f001 ffba bl 8002bdc <HAL_UART_Init>
8000c68: 4603 mov r3, r0
8000c6a: 2b00 cmp r3, #0
8000c6c: d001 beq.n 8000c72 <MX_USART6_UART_Init+0x46>
{
Error_Handler();
8000c6e: f000 f8e3 bl 8000e38 <Error_Handler>
}
/* USER CODE BEGIN USART6_Init 2 */
/* USER CODE END USART6_Init 2 */
}
8000c72: bf00 nop
8000c74: bd80 pop {r7, pc}
8000c76: bf00 nop
8000c78: 20000b6c .word 0x20000b6c
8000c7c: 40011400 .word 0x40011400
08000c80 <MX_USB_OTG_FS_PCD_Init>:
* @brief USB_OTG_FS Initialization Function
* @param None
* @retval None
*/
static void MX_USB_OTG_FS_PCD_Init(void)
{
8000c80: b580 push {r7, lr}
8000c82: af00 add r7, sp, #0
/* USER CODE END USB_OTG_FS_Init 0 */
/* USER CODE BEGIN USB_OTG_FS_Init 1 */
/* USER CODE END USB_OTG_FS_Init 1 */
hpcd_USB_OTG_FS.Instance = USB_OTG_FS;
8000c84: 4b14 ldr r3, [pc, #80] ; (8000cd8 <MX_USB_OTG_FS_PCD_Init+0x58>)
8000c86: f04f 42a0 mov.w r2, #1342177280 ; 0x50000000
8000c8a: 601a str r2, [r3, #0]
hpcd_USB_OTG_FS.Init.dev_endpoints = 4;
8000c8c: 4b12 ldr r3, [pc, #72] ; (8000cd8 <MX_USB_OTG_FS_PCD_Init+0x58>)
8000c8e: 2204 movs r2, #4
8000c90: 711a strb r2, [r3, #4]
hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL;
8000c92: 4b11 ldr r3, [pc, #68] ; (8000cd8 <MX_USB_OTG_FS_PCD_Init+0x58>)
8000c94: 2202 movs r2, #2
8000c96: 71da strb r2, [r3, #7]
hpcd_USB_OTG_FS.Init.dma_enable = DISABLE;
8000c98: 4b0f ldr r3, [pc, #60] ; (8000cd8 <MX_USB_OTG_FS_PCD_Init+0x58>)
8000c9a: 2200 movs r2, #0
8000c9c: 719a strb r2, [r3, #6]
hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED;
8000c9e: 4b0e ldr r3, [pc, #56] ; (8000cd8 <MX_USB_OTG_FS_PCD_Init+0x58>)
8000ca0: 2202 movs r2, #2
8000ca2: 725a strb r2, [r3, #9]
hpcd_USB_OTG_FS.Init.Sof_enable = ENABLE;
8000ca4: 4b0c ldr r3, [pc, #48] ; (8000cd8 <MX_USB_OTG_FS_PCD_Init+0x58>)
8000ca6: 2201 movs r2, #1
8000ca8: 729a strb r2, [r3, #10]
hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE;
8000caa: 4b0b ldr r3, [pc, #44] ; (8000cd8 <MX_USB_OTG_FS_PCD_Init+0x58>)
8000cac: 2200 movs r2, #0
8000cae: 72da strb r2, [r3, #11]
hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE;
8000cb0: 4b09 ldr r3, [pc, #36] ; (8000cd8 <MX_USB_OTG_FS_PCD_Init+0x58>)
8000cb2: 2200 movs r2, #0
8000cb4: 731a strb r2, [r3, #12]
hpcd_USB_OTG_FS.Init.vbus_sensing_enable = ENABLE;
8000cb6: 4b08 ldr r3, [pc, #32] ; (8000cd8 <MX_USB_OTG_FS_PCD_Init+0x58>)
8000cb8: 2201 movs r2, #1
8000cba: 739a strb r2, [r3, #14]
hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE;
8000cbc: 4b06 ldr r3, [pc, #24] ; (8000cd8 <MX_USB_OTG_FS_PCD_Init+0x58>)
8000cbe: 2200 movs r2, #0
8000cc0: 73da strb r2, [r3, #15]
if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK)
8000cc2: 4805 ldr r0, [pc, #20] ; (8000cd8 <MX_USB_OTG_FS_PCD_Init+0x58>)
8000cc4: f001 f9b9 bl 800203a <HAL_PCD_Init>
8000cc8: 4603 mov r3, r0
8000cca: 2b00 cmp r3, #0
8000ccc: d001 beq.n 8000cd2 <MX_USB_OTG_FS_PCD_Init+0x52>
{
Error_Handler();
8000cce: f000 f8b3 bl 8000e38 <Error_Handler>
}
/* USER CODE BEGIN USB_OTG_FS_Init 2 */
/* USER CODE END USB_OTG_FS_Init 2 */
}
8000cd2: bf00 nop
8000cd4: bd80 pop {r7, pc}
8000cd6: bf00 nop
8000cd8: 20000bb4 .word 0x20000bb4
08000cdc <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
8000cdc: b580 push {r7, lr}
8000cde: b08c sub sp, #48 ; 0x30
8000ce0: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000ce2: f107 031c add.w r3, r7, #28
8000ce6: 2200 movs r2, #0
8000ce8: 601a str r2, [r3, #0]
8000cea: 605a str r2, [r3, #4]
8000cec: 609a str r2, [r3, #8]
8000cee: 60da str r2, [r3, #12]
8000cf0: 611a str r2, [r3, #16]
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE();
8000cf2: 2300 movs r3, #0
8000cf4: 61bb str r3, [r7, #24]
8000cf6: 4b4c ldr r3, [pc, #304] ; (8000e28 <MX_GPIO_Init+0x14c>)
8000cf8: 6b1b ldr r3, [r3, #48] ; 0x30
8000cfa: 4a4b ldr r2, [pc, #300] ; (8000e28 <MX_GPIO_Init+0x14c>)
8000cfc: f043 0304 orr.w r3, r3, #4
8000d00: 6313 str r3, [r2, #48] ; 0x30
8000d02: 4b49 ldr r3, [pc, #292] ; (8000e28 <MX_GPIO_Init+0x14c>)
8000d04: 6b1b ldr r3, [r3, #48] ; 0x30
8000d06: f003 0304 and.w r3, r3, #4
8000d0a: 61bb str r3, [r7, #24]
8000d0c: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOH_CLK_ENABLE();
8000d0e: 2300 movs r3, #0
8000d10: 617b str r3, [r7, #20]
8000d12: 4b45 ldr r3, [pc, #276] ; (8000e28 <MX_GPIO_Init+0x14c>)
8000d14: 6b1b ldr r3, [r3, #48] ; 0x30
8000d16: 4a44 ldr r2, [pc, #272] ; (8000e28 <MX_GPIO_Init+0x14c>)
8000d18: f043 0380 orr.w r3, r3, #128 ; 0x80
8000d1c: 6313 str r3, [r2, #48] ; 0x30
8000d1e: 4b42 ldr r3, [pc, #264] ; (8000e28 <MX_GPIO_Init+0x14c>)
8000d20: 6b1b ldr r3, [r3, #48] ; 0x30
8000d22: f003 0380 and.w r3, r3, #128 ; 0x80
8000d26: 617b str r3, [r7, #20]
8000d28: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000d2a: 2300 movs r3, #0
8000d2c: 613b str r3, [r7, #16]
8000d2e: 4b3e ldr r3, [pc, #248] ; (8000e28 <MX_GPIO_Init+0x14c>)
8000d30: 6b1b ldr r3, [r3, #48] ; 0x30
8000d32: 4a3d ldr r2, [pc, #244] ; (8000e28 <MX_GPIO_Init+0x14c>)
8000d34: f043 0301 orr.w r3, r3, #1
8000d38: 6313 str r3, [r2, #48] ; 0x30
8000d3a: 4b3b ldr r3, [pc, #236] ; (8000e28 <MX_GPIO_Init+0x14c>)
8000d3c: 6b1b ldr r3, [r3, #48] ; 0x30
8000d3e: f003 0301 and.w r3, r3, #1
8000d42: 613b str r3, [r7, #16]
8000d44: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOB_CLK_ENABLE();
8000d46: 2300 movs r3, #0
8000d48: 60fb str r3, [r7, #12]
8000d4a: 4b37 ldr r3, [pc, #220] ; (8000e28 <MX_GPIO_Init+0x14c>)
8000d4c: 6b1b ldr r3, [r3, #48] ; 0x30
8000d4e: 4a36 ldr r2, [pc, #216] ; (8000e28 <MX_GPIO_Init+0x14c>)
8000d50: f043 0302 orr.w r3, r3, #2
8000d54: 6313 str r3, [r2, #48] ; 0x30
8000d56: 4b34 ldr r3, [pc, #208] ; (8000e28 <MX_GPIO_Init+0x14c>)
8000d58: 6b1b ldr r3, [r3, #48] ; 0x30
8000d5a: f003 0302 and.w r3, r3, #2
8000d5e: 60fb str r3, [r7, #12]
8000d60: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOD_CLK_ENABLE();
8000d62: 2300 movs r3, #0
8000d64: 60bb str r3, [r7, #8]
8000d66: 4b30 ldr r3, [pc, #192] ; (8000e28 <MX_GPIO_Init+0x14c>)
8000d68: 6b1b ldr r3, [r3, #48] ; 0x30
8000d6a: 4a2f ldr r2, [pc, #188] ; (8000e28 <MX_GPIO_Init+0x14c>)
8000d6c: f043 0308 orr.w r3, r3, #8
8000d70: 6313 str r3, [r2, #48] ; 0x30
8000d72: 4b2d ldr r3, [pc, #180] ; (8000e28 <MX_GPIO_Init+0x14c>)
8000d74: 6b1b ldr r3, [r3, #48] ; 0x30
8000d76: f003 0308 and.w r3, r3, #8
8000d7a: 60bb str r3, [r7, #8]
8000d7c: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOG_CLK_ENABLE();
8000d7e: 2300 movs r3, #0
8000d80: 607b str r3, [r7, #4]
8000d82: 4b29 ldr r3, [pc, #164] ; (8000e28 <MX_GPIO_Init+0x14c>)
8000d84: 6b1b ldr r3, [r3, #48] ; 0x30
8000d86: 4a28 ldr r2, [pc, #160] ; (8000e28 <MX_GPIO_Init+0x14c>)
8000d88: f043 0340 orr.w r3, r3, #64 ; 0x40
8000d8c: 6313 str r3, [r2, #48] ; 0x30
8000d8e: 4b26 ldr r3, [pc, #152] ; (8000e28 <MX_GPIO_Init+0x14c>)
8000d90: 6b1b ldr r3, [r3, #48] ; 0x30
8000d92: f003 0340 and.w r3, r3, #64 ; 0x40
8000d96: 607b str r3, [r7, #4]
8000d98: 687b ldr r3, [r7, #4]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOB, LD1_Pin|LD3_Pin|LD2_Pin, GPIO_PIN_RESET);
8000d9a: 2200 movs r2, #0
8000d9c: f244 0181 movw r1, #16513 ; 0x4081
8000da0: 4822 ldr r0, [pc, #136] ; (8000e2c <MX_GPIO_Init+0x150>)
8000da2: f001 f917 bl 8001fd4 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(USB_PowerSwitchOn_GPIO_Port, USB_PowerSwitchOn_Pin, GPIO_PIN_RESET);
8000da6: 2200 movs r2, #0
8000da8: 2140 movs r1, #64 ; 0x40
8000daa: 4821 ldr r0, [pc, #132] ; (8000e30 <MX_GPIO_Init+0x154>)
8000dac: f001 f912 bl 8001fd4 <HAL_GPIO_WritePin>
/*Configure GPIO pin : USER_Btn_Pin */
GPIO_InitStruct.Pin = USER_Btn_Pin;
8000db0: f44f 5300 mov.w r3, #8192 ; 0x2000
8000db4: 61fb str r3, [r7, #28]
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
8000db6: f44f 1388 mov.w r3, #1114112 ; 0x110000
8000dba: 623b str r3, [r7, #32]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000dbc: 2300 movs r3, #0
8000dbe: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(USER_Btn_GPIO_Port, &GPIO_InitStruct);
8000dc0: f107 031c add.w r3, r7, #28
8000dc4: 4619 mov r1, r3
8000dc6: 481b ldr r0, [pc, #108] ; (8000e34 <MX_GPIO_Init+0x158>)
8000dc8: f000 ff58 bl 8001c7c <HAL_GPIO_Init>
/*Configure GPIO pins : LD1_Pin LD3_Pin LD2_Pin */
GPIO_InitStruct.Pin = LD1_Pin|LD3_Pin|LD2_Pin;
8000dcc: f244 0381 movw r3, #16513 ; 0x4081
8000dd0: 61fb str r3, [r7, #28]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000dd2: 2301 movs r3, #1
8000dd4: 623b str r3, [r7, #32]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000dd6: 2300 movs r3, #0
8000dd8: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000dda: 2300 movs r3, #0
8000ddc: 62bb str r3, [r7, #40] ; 0x28
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8000dde: f107 031c add.w r3, r7, #28
8000de2: 4619 mov r1, r3
8000de4: 4811 ldr r0, [pc, #68] ; (8000e2c <MX_GPIO_Init+0x150>)
8000de6: f000 ff49 bl 8001c7c <HAL_GPIO_Init>
/*Configure GPIO pin : USB_PowerSwitchOn_Pin */
GPIO_InitStruct.Pin = USB_PowerSwitchOn_Pin;
8000dea: 2340 movs r3, #64 ; 0x40
8000dec: 61fb str r3, [r7, #28]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000dee: 2301 movs r3, #1
8000df0: 623b str r3, [r7, #32]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000df2: 2300 movs r3, #0
8000df4: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000df6: 2300 movs r3, #0
8000df8: 62bb str r3, [r7, #40] ; 0x28
HAL_GPIO_Init(USB_PowerSwitchOn_GPIO_Port, &GPIO_InitStruct);
8000dfa: f107 031c add.w r3, r7, #28
8000dfe: 4619 mov r1, r3
8000e00: 480b ldr r0, [pc, #44] ; (8000e30 <MX_GPIO_Init+0x154>)
8000e02: f000 ff3b bl 8001c7c <HAL_GPIO_Init>
/*Configure GPIO pin : USB_OverCurrent_Pin */
GPIO_InitStruct.Pin = USB_OverCurrent_Pin;
8000e06: 2380 movs r3, #128 ; 0x80
8000e08: 61fb str r3, [r7, #28]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8000e0a: 2300 movs r3, #0
8000e0c: 623b str r3, [r7, #32]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000e0e: 2300 movs r3, #0
8000e10: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(USB_OverCurrent_GPIO_Port, &GPIO_InitStruct);
8000e12: f107 031c add.w r3, r7, #28
8000e16: 4619 mov r1, r3
8000e18: 4805 ldr r0, [pc, #20] ; (8000e30 <MX_GPIO_Init+0x154>)
8000e1a: f000 ff2f bl 8001c7c <HAL_GPIO_Init>
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
8000e1e: bf00 nop
8000e20: 3730 adds r7, #48 ; 0x30
8000e22: 46bd mov sp, r7
8000e24: bd80 pop {r7, pc}
8000e26: bf00 nop
8000e28: 40023800 .word 0x40023800
8000e2c: 40020400 .word 0x40020400
8000e30: 40021800 .word 0x40021800
8000e34: 40020800 .word 0x40020800
08000e38 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
8000e38: b480 push {r7}
8000e3a: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting special-purpose register PRIMASK.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8000e3c: b672 cpsid i
}
8000e3e: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
8000e40: e7fe b.n 8000e40 <Error_Handler+0x8>
...
08000e44 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8000e44: b480 push {r7}
8000e46: b083 sub sp, #12
8000e48: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8000e4a: 2300 movs r3, #0
8000e4c: 607b str r3, [r7, #4]
8000e4e: 4b10 ldr r3, [pc, #64] ; (8000e90 <HAL_MspInit+0x4c>)
8000e50: 6c5b ldr r3, [r3, #68] ; 0x44
8000e52: 4a0f ldr r2, [pc, #60] ; (8000e90 <HAL_MspInit+0x4c>)
8000e54: f443 4380 orr.w r3, r3, #16384 ; 0x4000
8000e58: 6453 str r3, [r2, #68] ; 0x44
8000e5a: 4b0d ldr r3, [pc, #52] ; (8000e90 <HAL_MspInit+0x4c>)
8000e5c: 6c5b ldr r3, [r3, #68] ; 0x44
8000e5e: f403 4380 and.w r3, r3, #16384 ; 0x4000
8000e62: 607b str r3, [r7, #4]
8000e64: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
8000e66: 2300 movs r3, #0
8000e68: 603b str r3, [r7, #0]
8000e6a: 4b09 ldr r3, [pc, #36] ; (8000e90 <HAL_MspInit+0x4c>)
8000e6c: 6c1b ldr r3, [r3, #64] ; 0x40
8000e6e: 4a08 ldr r2, [pc, #32] ; (8000e90 <HAL_MspInit+0x4c>)
8000e70: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8000e74: 6413 str r3, [r2, #64] ; 0x40
8000e76: 4b06 ldr r3, [pc, #24] ; (8000e90 <HAL_MspInit+0x4c>)
8000e78: 6c1b ldr r3, [r3, #64] ; 0x40
8000e7a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8000e7e: 603b str r3, [r7, #0]
8000e80: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8000e82: bf00 nop
8000e84: 370c adds r7, #12
8000e86: 46bd mov sp, r7
8000e88: f85d 7b04 ldr.w r7, [sp], #4
8000e8c: 4770 bx lr
8000e8e: bf00 nop
8000e90: 40023800 .word 0x40023800
08000e94 <HAL_ETH_MspInit>:
* This function configures the hardware resources used in this example
* @param heth: ETH handle pointer
* @retval None
*/
void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
{
8000e94: b580 push {r7, lr}
8000e96: b08e sub sp, #56 ; 0x38
8000e98: af00 add r7, sp, #0
8000e9a: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000e9c: f107 0324 add.w r3, r7, #36 ; 0x24
8000ea0: 2200 movs r2, #0
8000ea2: 601a str r2, [r3, #0]
8000ea4: 605a str r2, [r3, #4]
8000ea6: 609a str r2, [r3, #8]
8000ea8: 60da str r2, [r3, #12]
8000eaa: 611a str r2, [r3, #16]
if(heth->Instance==ETH)
8000eac: 687b ldr r3, [r7, #4]
8000eae: 681b ldr r3, [r3, #0]
8000eb0: 4a55 ldr r2, [pc, #340] ; (8001008 <HAL_ETH_MspInit+0x174>)
8000eb2: 4293 cmp r3, r2
8000eb4: f040 80a4 bne.w 8001000 <HAL_ETH_MspInit+0x16c>
{
/* USER CODE BEGIN ETH_MspInit 0 */
/* USER CODE END ETH_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_ETH_CLK_ENABLE();
8000eb8: 2300 movs r3, #0
8000eba: 623b str r3, [r7, #32]
8000ebc: 4b53 ldr r3, [pc, #332] ; (800100c <HAL_ETH_MspInit+0x178>)
8000ebe: 6b1b ldr r3, [r3, #48] ; 0x30
8000ec0: 4a52 ldr r2, [pc, #328] ; (800100c <HAL_ETH_MspInit+0x178>)
8000ec2: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000
8000ec6: 6313 str r3, [r2, #48] ; 0x30
8000ec8: 4b50 ldr r3, [pc, #320] ; (800100c <HAL_ETH_MspInit+0x178>)
8000eca: 6b1b ldr r3, [r3, #48] ; 0x30
8000ecc: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8000ed0: 623b str r3, [r7, #32]
8000ed2: 6a3b ldr r3, [r7, #32]
8000ed4: 2300 movs r3, #0
8000ed6: 61fb str r3, [r7, #28]
8000ed8: 4b4c ldr r3, [pc, #304] ; (800100c <HAL_ETH_MspInit+0x178>)
8000eda: 6b1b ldr r3, [r3, #48] ; 0x30
8000edc: 4a4b ldr r2, [pc, #300] ; (800100c <HAL_ETH_MspInit+0x178>)
8000ede: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000
8000ee2: 6313 str r3, [r2, #48] ; 0x30
8000ee4: 4b49 ldr r3, [pc, #292] ; (800100c <HAL_ETH_MspInit+0x178>)
8000ee6: 6b1b ldr r3, [r3, #48] ; 0x30
8000ee8: f003 6380 and.w r3, r3, #67108864 ; 0x4000000
8000eec: 61fb str r3, [r7, #28]
8000eee: 69fb ldr r3, [r7, #28]
8000ef0: 2300 movs r3, #0
8000ef2: 61bb str r3, [r7, #24]
8000ef4: 4b45 ldr r3, [pc, #276] ; (800100c <HAL_ETH_MspInit+0x178>)
8000ef6: 6b1b ldr r3, [r3, #48] ; 0x30
8000ef8: 4a44 ldr r2, [pc, #272] ; (800100c <HAL_ETH_MspInit+0x178>)
8000efa: f043 6300 orr.w r3, r3, #134217728 ; 0x8000000
8000efe: 6313 str r3, [r2, #48] ; 0x30
8000f00: 4b42 ldr r3, [pc, #264] ; (800100c <HAL_ETH_MspInit+0x178>)
8000f02: 6b1b ldr r3, [r3, #48] ; 0x30
8000f04: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
8000f08: 61bb str r3, [r7, #24]
8000f0a: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOC_CLK_ENABLE();
8000f0c: 2300 movs r3, #0
8000f0e: 617b str r3, [r7, #20]
8000f10: 4b3e ldr r3, [pc, #248] ; (800100c <HAL_ETH_MspInit+0x178>)
8000f12: 6b1b ldr r3, [r3, #48] ; 0x30
8000f14: 4a3d ldr r2, [pc, #244] ; (800100c <HAL_ETH_MspInit+0x178>)
8000f16: f043 0304 orr.w r3, r3, #4
8000f1a: 6313 str r3, [r2, #48] ; 0x30
8000f1c: 4b3b ldr r3, [pc, #236] ; (800100c <HAL_ETH_MspInit+0x178>)
8000f1e: 6b1b ldr r3, [r3, #48] ; 0x30
8000f20: f003 0304 and.w r3, r3, #4
8000f24: 617b str r3, [r7, #20]
8000f26: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000f28: 2300 movs r3, #0
8000f2a: 613b str r3, [r7, #16]
8000f2c: 4b37 ldr r3, [pc, #220] ; (800100c <HAL_ETH_MspInit+0x178>)
8000f2e: 6b1b ldr r3, [r3, #48] ; 0x30
8000f30: 4a36 ldr r2, [pc, #216] ; (800100c <HAL_ETH_MspInit+0x178>)
8000f32: f043 0301 orr.w r3, r3, #1
8000f36: 6313 str r3, [r2, #48] ; 0x30
8000f38: 4b34 ldr r3, [pc, #208] ; (800100c <HAL_ETH_MspInit+0x178>)
8000f3a: 6b1b ldr r3, [r3, #48] ; 0x30
8000f3c: f003 0301 and.w r3, r3, #1
8000f40: 613b str r3, [r7, #16]
8000f42: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOB_CLK_ENABLE();
8000f44: 2300 movs r3, #0
8000f46: 60fb str r3, [r7, #12]
8000f48: 4b30 ldr r3, [pc, #192] ; (800100c <HAL_ETH_MspInit+0x178>)
8000f4a: 6b1b ldr r3, [r3, #48] ; 0x30
8000f4c: 4a2f ldr r2, [pc, #188] ; (800100c <HAL_ETH_MspInit+0x178>)
8000f4e: f043 0302 orr.w r3, r3, #2
8000f52: 6313 str r3, [r2, #48] ; 0x30
8000f54: 4b2d ldr r3, [pc, #180] ; (800100c <HAL_ETH_MspInit+0x178>)
8000f56: 6b1b ldr r3, [r3, #48] ; 0x30
8000f58: f003 0302 and.w r3, r3, #2
8000f5c: 60fb str r3, [r7, #12]
8000f5e: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOG_CLK_ENABLE();
8000f60: 2300 movs r3, #0
8000f62: 60bb str r3, [r7, #8]
8000f64: 4b29 ldr r3, [pc, #164] ; (800100c <HAL_ETH_MspInit+0x178>)
8000f66: 6b1b ldr r3, [r3, #48] ; 0x30
8000f68: 4a28 ldr r2, [pc, #160] ; (800100c <HAL_ETH_MspInit+0x178>)
8000f6a: f043 0340 orr.w r3, r3, #64 ; 0x40
8000f6e: 6313 str r3, [r2, #48] ; 0x30
8000f70: 4b26 ldr r3, [pc, #152] ; (800100c <HAL_ETH_MspInit+0x178>)
8000f72: 6b1b ldr r3, [r3, #48] ; 0x30
8000f74: f003 0340 and.w r3, r3, #64 ; 0x40
8000f78: 60bb str r3, [r7, #8]
8000f7a: 68bb ldr r3, [r7, #8]
PC5 ------> ETH_RXD1
PB13 ------> ETH_TXD1
PG11 ------> ETH_TX_EN
PG13 ------> ETH_TXD0
*/
GPIO_InitStruct.Pin = RMII_MDC_Pin|RMII_RXD0_Pin|RMII_RXD1_Pin;
8000f7c: 2332 movs r3, #50 ; 0x32
8000f7e: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000f80: 2302 movs r3, #2
8000f82: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000f84: 2300 movs r3, #0
8000f86: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000f88: 2303 movs r3, #3
8000f8a: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
8000f8c: 230b movs r3, #11
8000f8e: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8000f90: f107 0324 add.w r3, r7, #36 ; 0x24
8000f94: 4619 mov r1, r3
8000f96: 481e ldr r0, [pc, #120] ; (8001010 <HAL_ETH_MspInit+0x17c>)
8000f98: f000 fe70 bl 8001c7c <HAL_GPIO_Init>
GPIO_InitStruct.Pin = RMII_REF_CLK_Pin|RMII_MDIO_Pin|RMII_CRS_DV_Pin;
8000f9c: 2386 movs r3, #134 ; 0x86
8000f9e: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000fa0: 2302 movs r3, #2
8000fa2: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000fa4: 2300 movs r3, #0
8000fa6: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000fa8: 2303 movs r3, #3
8000faa: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
8000fac: 230b movs r3, #11
8000fae: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000fb0: f107 0324 add.w r3, r7, #36 ; 0x24
8000fb4: 4619 mov r1, r3
8000fb6: 4817 ldr r0, [pc, #92] ; (8001014 <HAL_ETH_MspInit+0x180>)
8000fb8: f000 fe60 bl 8001c7c <HAL_GPIO_Init>
GPIO_InitStruct.Pin = RMII_TXD1_Pin;
8000fbc: f44f 5300 mov.w r3, #8192 ; 0x2000
8000fc0: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000fc2: 2302 movs r3, #2
8000fc4: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000fc6: 2300 movs r3, #0
8000fc8: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000fca: 2303 movs r3, #3
8000fcc: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
8000fce: 230b movs r3, #11
8000fd0: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(RMII_TXD1_GPIO_Port, &GPIO_InitStruct);
8000fd2: f107 0324 add.w r3, r7, #36 ; 0x24
8000fd6: 4619 mov r1, r3
8000fd8: 480f ldr r0, [pc, #60] ; (8001018 <HAL_ETH_MspInit+0x184>)
8000fda: f000 fe4f bl 8001c7c <HAL_GPIO_Init>
GPIO_InitStruct.Pin = RMII_TX_EN_Pin|RMII_TXD0_Pin;
8000fde: f44f 5320 mov.w r3, #10240 ; 0x2800
8000fe2: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000fe4: 2302 movs r3, #2
8000fe6: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000fe8: 2300 movs r3, #0
8000fea: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000fec: 2303 movs r3, #3
8000fee: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
8000ff0: 230b movs r3, #11
8000ff2: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
8000ff4: f107 0324 add.w r3, r7, #36 ; 0x24
8000ff8: 4619 mov r1, r3
8000ffa: 4808 ldr r0, [pc, #32] ; (800101c <HAL_ETH_MspInit+0x188>)
8000ffc: f000 fe3e bl 8001c7c <HAL_GPIO_Init>
/* USER CODE END ETH_MspInit 1 */
}
}
8001000: bf00 nop
8001002: 3738 adds r7, #56 ; 0x38
8001004: 46bd mov sp, r7
8001006: bd80 pop {r7, pc}
8001008: 40028000 .word 0x40028000
800100c: 40023800 .word 0x40023800
8001010: 40020800 .word 0x40020800
8001014: 40020000 .word 0x40020000
8001018: 40020400 .word 0x40020400
800101c: 40021800 .word 0x40021800
08001020 <HAL_RNG_MspInit>:
* This function configures the hardware resources used in this example
* @param hrng: RNG handle pointer
* @retval None
*/
void HAL_RNG_MspInit(RNG_HandleTypeDef* hrng)
{
8001020: b480 push {r7}
8001022: b085 sub sp, #20
8001024: af00 add r7, sp, #0
8001026: 6078 str r0, [r7, #4]
if(hrng->Instance==RNG)
8001028: 687b ldr r3, [r7, #4]
800102a: 681b ldr r3, [r3, #0]
800102c: 4a0b ldr r2, [pc, #44] ; (800105c <HAL_RNG_MspInit+0x3c>)
800102e: 4293 cmp r3, r2
8001030: d10d bne.n 800104e <HAL_RNG_MspInit+0x2e>
{
/* USER CODE BEGIN RNG_MspInit 0 */
/* USER CODE END RNG_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_RNG_CLK_ENABLE();
8001032: 2300 movs r3, #0
8001034: 60fb str r3, [r7, #12]
8001036: 4b0a ldr r3, [pc, #40] ; (8001060 <HAL_RNG_MspInit+0x40>)
8001038: 6b5b ldr r3, [r3, #52] ; 0x34
800103a: 4a09 ldr r2, [pc, #36] ; (8001060 <HAL_RNG_MspInit+0x40>)
800103c: f043 0340 orr.w r3, r3, #64 ; 0x40
8001040: 6353 str r3, [r2, #52] ; 0x34
8001042: 4b07 ldr r3, [pc, #28] ; (8001060 <HAL_RNG_MspInit+0x40>)
8001044: 6b5b ldr r3, [r3, #52] ; 0x34
8001046: f003 0340 and.w r3, r3, #64 ; 0x40
800104a: 60fb str r3, [r7, #12]
800104c: 68fb ldr r3, [r7, #12]
/* USER CODE END RNG_MspInit 1 */
}
}
800104e: bf00 nop
8001050: 3714 adds r7, #20
8001052: 46bd mov sp, r7
8001054: f85d 7b04 ldr.w r7, [sp], #4
8001058: 4770 bx lr
800105a: bf00 nop
800105c: 50060800 .word 0x50060800
8001060: 40023800 .word 0x40023800
08001064 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
8001064: b580 push {r7, lr}
8001066: b08c sub sp, #48 ; 0x30
8001068: af00 add r7, sp, #0
800106a: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
800106c: f107 031c add.w r3, r7, #28
8001070: 2200 movs r2, #0
8001072: 601a str r2, [r3, #0]
8001074: 605a str r2, [r3, #4]
8001076: 609a str r2, [r3, #8]
8001078: 60da str r2, [r3, #12]
800107a: 611a str r2, [r3, #16]
if(huart->Instance==USART3)
800107c: 687b ldr r3, [r7, #4]
800107e: 681b ldr r3, [r3, #0]
8001080: 4a33 ldr r2, [pc, #204] ; (8001150 <HAL_UART_MspInit+0xec>)
8001082: 4293 cmp r3, r2
8001084: d12d bne.n 80010e2 <HAL_UART_MspInit+0x7e>
{
/* USER CODE BEGIN USART3_MspInit 0 */
/* USER CODE END USART3_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_USART3_CLK_ENABLE();
8001086: 2300 movs r3, #0
8001088: 61bb str r3, [r7, #24]
800108a: 4b32 ldr r3, [pc, #200] ; (8001154 <HAL_UART_MspInit+0xf0>)
800108c: 6c1b ldr r3, [r3, #64] ; 0x40
800108e: 4a31 ldr r2, [pc, #196] ; (8001154 <HAL_UART_MspInit+0xf0>)
8001090: f443 2380 orr.w r3, r3, #262144 ; 0x40000
8001094: 6413 str r3, [r2, #64] ; 0x40
8001096: 4b2f ldr r3, [pc, #188] ; (8001154 <HAL_UART_MspInit+0xf0>)
8001098: 6c1b ldr r3, [r3, #64] ; 0x40
800109a: f403 2380 and.w r3, r3, #262144 ; 0x40000
800109e: 61bb str r3, [r7, #24]
80010a0: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOD_CLK_ENABLE();
80010a2: 2300 movs r3, #0
80010a4: 617b str r3, [r7, #20]
80010a6: 4b2b ldr r3, [pc, #172] ; (8001154 <HAL_UART_MspInit+0xf0>)
80010a8: 6b1b ldr r3, [r3, #48] ; 0x30
80010aa: 4a2a ldr r2, [pc, #168] ; (8001154 <HAL_UART_MspInit+0xf0>)
80010ac: f043 0308 orr.w r3, r3, #8
80010b0: 6313 str r3, [r2, #48] ; 0x30
80010b2: 4b28 ldr r3, [pc, #160] ; (8001154 <HAL_UART_MspInit+0xf0>)
80010b4: 6b1b ldr r3, [r3, #48] ; 0x30
80010b6: f003 0308 and.w r3, r3, #8
80010ba: 617b str r3, [r7, #20]
80010bc: 697b ldr r3, [r7, #20]
/**USART3 GPIO Configuration
PD8 ------> USART3_TX
PD9 ------> USART3_RX
*/
GPIO_InitStruct.Pin = STLK_RX_Pin|STLK_TX_Pin;
80010be: f44f 7340 mov.w r3, #768 ; 0x300
80010c2: 61fb str r3, [r7, #28]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80010c4: 2302 movs r3, #2
80010c6: 623b str r3, [r7, #32]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80010c8: 2300 movs r3, #0
80010ca: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80010cc: 2303 movs r3, #3
80010ce: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
80010d0: 2307 movs r3, #7
80010d2: 62fb str r3, [r7, #44] ; 0x2c
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
80010d4: f107 031c add.w r3, r7, #28
80010d8: 4619 mov r1, r3
80010da: 481f ldr r0, [pc, #124] ; (8001158 <HAL_UART_MspInit+0xf4>)
80010dc: f000 fdce bl 8001c7c <HAL_GPIO_Init>
/* USER CODE BEGIN USART6_MspInit 1 */
/* USER CODE END USART6_MspInit 1 */
}
}
80010e0: e031 b.n 8001146 <HAL_UART_MspInit+0xe2>
else if(huart->Instance==USART6)
80010e2: 687b ldr r3, [r7, #4]
80010e4: 681b ldr r3, [r3, #0]
80010e6: 4a1d ldr r2, [pc, #116] ; (800115c <HAL_UART_MspInit+0xf8>)
80010e8: 4293 cmp r3, r2
80010ea: d12c bne.n 8001146 <HAL_UART_MspInit+0xe2>
__HAL_RCC_USART6_CLK_ENABLE();
80010ec: 2300 movs r3, #0
80010ee: 613b str r3, [r7, #16]
80010f0: 4b18 ldr r3, [pc, #96] ; (8001154 <HAL_UART_MspInit+0xf0>)
80010f2: 6c5b ldr r3, [r3, #68] ; 0x44
80010f4: 4a17 ldr r2, [pc, #92] ; (8001154 <HAL_UART_MspInit+0xf0>)
80010f6: f043 0320 orr.w r3, r3, #32
80010fa: 6453 str r3, [r2, #68] ; 0x44
80010fc: 4b15 ldr r3, [pc, #84] ; (8001154 <HAL_UART_MspInit+0xf0>)
80010fe: 6c5b ldr r3, [r3, #68] ; 0x44
8001100: f003 0320 and.w r3, r3, #32
8001104: 613b str r3, [r7, #16]
8001106: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOG_CLK_ENABLE();
8001108: 2300 movs r3, #0
800110a: 60fb str r3, [r7, #12]
800110c: 4b11 ldr r3, [pc, #68] ; (8001154 <HAL_UART_MspInit+0xf0>)
800110e: 6b1b ldr r3, [r3, #48] ; 0x30
8001110: 4a10 ldr r2, [pc, #64] ; (8001154 <HAL_UART_MspInit+0xf0>)
8001112: f043 0340 orr.w r3, r3, #64 ; 0x40
8001116: 6313 str r3, [r2, #48] ; 0x30
8001118: 4b0e ldr r3, [pc, #56] ; (8001154 <HAL_UART_MspInit+0xf0>)
800111a: 6b1b ldr r3, [r3, #48] ; 0x30
800111c: f003 0340 and.w r3, r3, #64 ; 0x40
8001120: 60fb str r3, [r7, #12]
8001122: 68fb ldr r3, [r7, #12]
GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_14;
8001124: f44f 4384 mov.w r3, #16896 ; 0x4200
8001128: 61fb str r3, [r7, #28]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800112a: 2302 movs r3, #2
800112c: 623b str r3, [r7, #32]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800112e: 2300 movs r3, #0
8001130: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001132: 2303 movs r3, #3
8001134: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Alternate = GPIO_AF8_USART6;
8001136: 2308 movs r3, #8
8001138: 62fb str r3, [r7, #44] ; 0x2c
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
800113a: f107 031c add.w r3, r7, #28
800113e: 4619 mov r1, r3
8001140: 4807 ldr r0, [pc, #28] ; (8001160 <HAL_UART_MspInit+0xfc>)
8001142: f000 fd9b bl 8001c7c <HAL_GPIO_Init>
}
8001146: bf00 nop
8001148: 3730 adds r7, #48 ; 0x30
800114a: 46bd mov sp, r7
800114c: bd80 pop {r7, pc}
800114e: bf00 nop
8001150: 40004800 .word 0x40004800
8001154: 40023800 .word 0x40023800
8001158: 40020c00 .word 0x40020c00
800115c: 40011400 .word 0x40011400
8001160: 40021800 .word 0x40021800
08001164 <HAL_PCD_MspInit>:
* This function configures the hardware resources used in this example
* @param hpcd: PCD handle pointer
* @retval None
*/
void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd)
{
8001164: b580 push {r7, lr}
8001166: b08a sub sp, #40 ; 0x28
8001168: af00 add r7, sp, #0
800116a: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
800116c: f107 0314 add.w r3, r7, #20
8001170: 2200 movs r2, #0
8001172: 601a str r2, [r3, #0]
8001174: 605a str r2, [r3, #4]
8001176: 609a str r2, [r3, #8]
8001178: 60da str r2, [r3, #12]
800117a: 611a str r2, [r3, #16]
if(hpcd->Instance==USB_OTG_FS)
800117c: 687b ldr r3, [r7, #4]
800117e: 681b ldr r3, [r3, #0]
8001180: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000
8001184: d13f bne.n 8001206 <HAL_PCD_MspInit+0xa2>
{
/* USER CODE BEGIN USB_OTG_FS_MspInit 0 */
/* USER CODE END USB_OTG_FS_MspInit 0 */
__HAL_RCC_GPIOA_CLK_ENABLE();
8001186: 2300 movs r3, #0
8001188: 613b str r3, [r7, #16]
800118a: 4b21 ldr r3, [pc, #132] ; (8001210 <HAL_PCD_MspInit+0xac>)
800118c: 6b1b ldr r3, [r3, #48] ; 0x30
800118e: 4a20 ldr r2, [pc, #128] ; (8001210 <HAL_PCD_MspInit+0xac>)
8001190: f043 0301 orr.w r3, r3, #1
8001194: 6313 str r3, [r2, #48] ; 0x30
8001196: 4b1e ldr r3, [pc, #120] ; (8001210 <HAL_PCD_MspInit+0xac>)
8001198: 6b1b ldr r3, [r3, #48] ; 0x30
800119a: f003 0301 and.w r3, r3, #1
800119e: 613b str r3, [r7, #16]
80011a0: 693b ldr r3, [r7, #16]
PA9 ------> USB_OTG_FS_VBUS
PA10 ------> USB_OTG_FS_ID
PA11 ------> USB_OTG_FS_DM
PA12 ------> USB_OTG_FS_DP
*/
GPIO_InitStruct.Pin = USB_SOF_Pin|USB_ID_Pin|USB_DM_Pin|USB_DP_Pin;
80011a2: f44f 53e8 mov.w r3, #7424 ; 0x1d00
80011a6: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80011a8: 2302 movs r3, #2
80011aa: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80011ac: 2300 movs r3, #0
80011ae: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80011b0: 2303 movs r3, #3
80011b2: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
80011b4: 230a movs r3, #10
80011b6: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80011b8: f107 0314 add.w r3, r7, #20
80011bc: 4619 mov r1, r3
80011be: 4815 ldr r0, [pc, #84] ; (8001214 <HAL_PCD_MspInit+0xb0>)
80011c0: f000 fd5c bl 8001c7c <HAL_GPIO_Init>
GPIO_InitStruct.Pin = USB_VBUS_Pin;
80011c4: f44f 7300 mov.w r3, #512 ; 0x200
80011c8: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
80011ca: 2300 movs r3, #0
80011cc: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80011ce: 2300 movs r3, #0
80011d0: 61fb str r3, [r7, #28]
HAL_GPIO_Init(USB_VBUS_GPIO_Port, &GPIO_InitStruct);
80011d2: f107 0314 add.w r3, r7, #20
80011d6: 4619 mov r1, r3
80011d8: 480e ldr r0, [pc, #56] ; (8001214 <HAL_PCD_MspInit+0xb0>)
80011da: f000 fd4f bl 8001c7c <HAL_GPIO_Init>
/* Peripheral clock enable */
__HAL_RCC_USB_OTG_FS_CLK_ENABLE();
80011de: 4b0c ldr r3, [pc, #48] ; (8001210 <HAL_PCD_MspInit+0xac>)
80011e0: 6b5b ldr r3, [r3, #52] ; 0x34
80011e2: 4a0b ldr r2, [pc, #44] ; (8001210 <HAL_PCD_MspInit+0xac>)
80011e4: f043 0380 orr.w r3, r3, #128 ; 0x80
80011e8: 6353 str r3, [r2, #52] ; 0x34
80011ea: 2300 movs r3, #0
80011ec: 60fb str r3, [r7, #12]
80011ee: 4b08 ldr r3, [pc, #32] ; (8001210 <HAL_PCD_MspInit+0xac>)
80011f0: 6c5b ldr r3, [r3, #68] ; 0x44
80011f2: 4a07 ldr r2, [pc, #28] ; (8001210 <HAL_PCD_MspInit+0xac>)
80011f4: f443 4380 orr.w r3, r3, #16384 ; 0x4000
80011f8: 6453 str r3, [r2, #68] ; 0x44
80011fa: 4b05 ldr r3, [pc, #20] ; (8001210 <HAL_PCD_MspInit+0xac>)
80011fc: 6c5b ldr r3, [r3, #68] ; 0x44
80011fe: f403 4380 and.w r3, r3, #16384 ; 0x4000
8001202: 60fb str r3, [r7, #12]
8001204: 68fb ldr r3, [r7, #12]
/* USER CODE END USB_OTG_FS_MspInit 1 */
}
}
8001206: bf00 nop
8001208: 3728 adds r7, #40 ; 0x28
800120a: 46bd mov sp, r7
800120c: bd80 pop {r7, pc}
800120e: bf00 nop
8001210: 40023800 .word 0x40023800
8001214: 40020000 .word 0x40020000
08001218 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8001218: b480 push {r7}
800121a: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
800121c: e7fe b.n 800121c <NMI_Handler+0x4>
0800121e <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
800121e: b480 push {r7}
8001220: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8001222: e7fe b.n 8001222 <HardFault_Handler+0x4>
08001224 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8001224: b480 push {r7}
8001226: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8001228: e7fe b.n 8001228 <MemManage_Handler+0x4>
0800122a <BusFault_Handler>:
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
800122a: b480 push {r7}
800122c: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
800122e: e7fe b.n 800122e <BusFault_Handler+0x4>
08001230 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8001230: b480 push {r7}
8001232: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8001234: e7fe b.n 8001234 <UsageFault_Handler+0x4>
08001236 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8001236: b480 push {r7}
8001238: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
800123a: bf00 nop
800123c: 46bd mov sp, r7
800123e: f85d 7b04 ldr.w r7, [sp], #4
8001242: 4770 bx lr
08001244 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8001244: b480 push {r7}
8001246: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8001248: bf00 nop
800124a: 46bd mov sp, r7
800124c: f85d 7b04 ldr.w r7, [sp], #4
8001250: 4770 bx lr
08001252 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8001252: b480 push {r7}
8001254: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8001256: bf00 nop
8001258: 46bd mov sp, r7
800125a: f85d 7b04 ldr.w r7, [sp], #4
800125e: 4770 bx lr
08001260 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8001260: b580 push {r7, lr}
8001262: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8001264: f000 f890 bl 8001388 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
8001268: bf00 nop
800126a: bd80 pop {r7, pc}
0800126c <SystemInit>:
* configuration.
* @param None
* @retval None
*/
void SystemInit(void)
{
800126c: b480 push {r7}
800126e: af00 add r7, sp, #0
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
8001270: 4b06 ldr r3, [pc, #24] ; (800128c <SystemInit+0x20>)
8001272: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
8001276: 4a05 ldr r2, [pc, #20] ; (800128c <SystemInit+0x20>)
8001278: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
800127c: f8c2 3088 str.w r3, [r2, #136] ; 0x88
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
8001280: bf00 nop
8001282: 46bd mov sp, r7
8001284: f85d 7b04 ldr.w r7, [sp], #4
8001288: 4770 bx lr
800128a: bf00 nop
800128c: e000ed00 .word 0xe000ed00
08001290 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
8001290: f8df d034 ldr.w sp, [pc, #52] ; 80012c8 <LoopFillZerobss+0xe>
/* Call the clock system initialization function.*/
bl SystemInit
8001294: f7ff ffea bl 800126c <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8001298: 480c ldr r0, [pc, #48] ; (80012cc <LoopFillZerobss+0x12>)
ldr r1, =_edata
800129a: 490d ldr r1, [pc, #52] ; (80012d0 <LoopFillZerobss+0x16>)
ldr r2, =_sidata
800129c: 4a0d ldr r2, [pc, #52] ; (80012d4 <LoopFillZerobss+0x1a>)
movs r3, #0
800129e: 2300 movs r3, #0
b LoopCopyDataInit
80012a0: e002 b.n 80012a8 <LoopCopyDataInit>
080012a2 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
80012a2: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
80012a4: 50c4 str r4, [r0, r3]
adds r3, r3, #4
80012a6: 3304 adds r3, #4
080012a8 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
80012a8: 18c4 adds r4, r0, r3
cmp r4, r1
80012aa: 428c cmp r4, r1
bcc CopyDataInit
80012ac: d3f9 bcc.n 80012a2 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
80012ae: 4a0a ldr r2, [pc, #40] ; (80012d8 <LoopFillZerobss+0x1e>)
ldr r4, =_ebss
80012b0: 4c0a ldr r4, [pc, #40] ; (80012dc <LoopFillZerobss+0x22>)
movs r3, #0
80012b2: 2300 movs r3, #0
b LoopFillZerobss
80012b4: e001 b.n 80012ba <LoopFillZerobss>
080012b6 <FillZerobss>:
FillZerobss:
str r3, [r2]
80012b6: 6013 str r3, [r2, #0]
adds r2, r2, #4
80012b8: 3204 adds r2, #4
080012ba <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
80012ba: 42a2 cmp r2, r4
bcc FillZerobss
80012bc: d3fb bcc.n 80012b6 <FillZerobss>
/* Call static constructors */
bl __libc_init_array
80012be: f002 fc3d bl 8003b3c <__libc_init_array>
/* Call the application's entry point.*/
bl main
80012c2: f7ff fb53 bl 800096c <main>
bx lr
80012c6: 4770 bx lr
ldr sp, =_estack /* set stack pointer */
80012c8: 20030000 .word 0x20030000
ldr r0, =_sdata
80012cc: 20000000 .word 0x20000000
ldr r1, =_edata
80012d0: 200006c8 .word 0x200006c8
ldr r2, =_sidata
80012d4: 08003c94 .word 0x08003c94
ldr r2, =_sbss
80012d8: 200006c8 .word 0x200006c8
ldr r4, =_ebss
80012dc: 2000123c .word 0x2000123c
080012e0 <ADC_IRQHandler>:
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
80012e0: e7fe b.n 80012e0 <ADC_IRQHandler>
...
080012e4 <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
80012e4: b580 push {r7, lr}
80012e6: af00 add r7, sp, #0
/* Configure Flash prefetch, Instruction cache, Data cache */
#if (INSTRUCTION_CACHE_ENABLE != 0U)
__HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
80012e8: 4b0e ldr r3, [pc, #56] ; (8001324 <HAL_Init+0x40>)
80012ea: 681b ldr r3, [r3, #0]
80012ec: 4a0d ldr r2, [pc, #52] ; (8001324 <HAL_Init+0x40>)
80012ee: f443 7300 orr.w r3, r3, #512 ; 0x200
80012f2: 6013 str r3, [r2, #0]
#endif /* INSTRUCTION_CACHE_ENABLE */
#if (DATA_CACHE_ENABLE != 0U)
__HAL_FLASH_DATA_CACHE_ENABLE();
80012f4: 4b0b ldr r3, [pc, #44] ; (8001324 <HAL_Init+0x40>)
80012f6: 681b ldr r3, [r3, #0]
80012f8: 4a0a ldr r2, [pc, #40] ; (8001324 <HAL_Init+0x40>)
80012fa: f443 6380 orr.w r3, r3, #1024 ; 0x400
80012fe: 6013 str r3, [r2, #0]
#endif /* DATA_CACHE_ENABLE */
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
8001300: 4b08 ldr r3, [pc, #32] ; (8001324 <HAL_Init+0x40>)
8001302: 681b ldr r3, [r3, #0]
8001304: 4a07 ldr r2, [pc, #28] ; (8001324 <HAL_Init+0x40>)
8001306: f443 7380 orr.w r3, r3, #256 ; 0x100
800130a: 6013 str r3, [r2, #0]
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
800130c: 2003 movs r0, #3
800130e: f000 f931 bl 8001574 <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
8001312: 2000 movs r0, #0
8001314: f000 f808 bl 8001328 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
8001318: f7ff fd94 bl 8000e44 <HAL_MspInit>
/* Return function status */
return HAL_OK;
800131c: 2300 movs r3, #0
}
800131e: 4618 mov r0, r3
8001320: bd80 pop {r7, pc}
8001322: bf00 nop
8001324: 40023c00 .word 0x40023c00
08001328 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8001328: b580 push {r7, lr}
800132a: b082 sub sp, #8
800132c: af00 add r7, sp, #0
800132e: 6078 str r0, [r7, #4]
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
8001330: 4b12 ldr r3, [pc, #72] ; (800137c <HAL_InitTick+0x54>)
8001332: 681a ldr r2, [r3, #0]
8001334: 4b12 ldr r3, [pc, #72] ; (8001380 <HAL_InitTick+0x58>)
8001336: 781b ldrb r3, [r3, #0]
8001338: 4619 mov r1, r3
800133a: f44f 737a mov.w r3, #1000 ; 0x3e8
800133e: fbb3 f3f1 udiv r3, r3, r1
8001342: fbb2 f3f3 udiv r3, r2, r3
8001346: 4618 mov r0, r3
8001348: f000 f93b bl 80015c2 <HAL_SYSTICK_Config>
800134c: 4603 mov r3, r0
800134e: 2b00 cmp r3, #0
8001350: d001 beq.n 8001356 <HAL_InitTick+0x2e>
{
return HAL_ERROR;
8001352: 2301 movs r3, #1
8001354: e00e b.n 8001374 <HAL_InitTick+0x4c>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8001356: 687b ldr r3, [r7, #4]
8001358: 2b0f cmp r3, #15
800135a: d80a bhi.n 8001372 <HAL_InitTick+0x4a>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
800135c: 2200 movs r2, #0
800135e: 6879 ldr r1, [r7, #4]
8001360: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
8001364: f000 f911 bl 800158a <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8001368: 4a06 ldr r2, [pc, #24] ; (8001384 <HAL_InitTick+0x5c>)
800136a: 687b ldr r3, [r7, #4]
800136c: 6013 str r3, [r2, #0]
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
800136e: 2300 movs r3, #0
8001370: e000 b.n 8001374 <HAL_InitTick+0x4c>
return HAL_ERROR;
8001372: 2301 movs r3, #1
}
8001374: 4618 mov r0, r3
8001376: 3708 adds r7, #8
8001378: 46bd mov sp, r7
800137a: bd80 pop {r7, pc}
800137c: 200006b8 .word 0x200006b8
8001380: 200006c0 .word 0x200006c0
8001384: 200006bc .word 0x200006bc
08001388 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8001388: b480 push {r7}
800138a: af00 add r7, sp, #0
uwTick += uwTickFreq;
800138c: 4b06 ldr r3, [pc, #24] ; (80013a8 <HAL_IncTick+0x20>)
800138e: 781b ldrb r3, [r3, #0]
8001390: 461a mov r2, r3
8001392: 4b06 ldr r3, [pc, #24] ; (80013ac <HAL_IncTick+0x24>)
8001394: 681b ldr r3, [r3, #0]
8001396: 4413 add r3, r2
8001398: 4a04 ldr r2, [pc, #16] ; (80013ac <HAL_IncTick+0x24>)
800139a: 6013 str r3, [r2, #0]
}
800139c: bf00 nop
800139e: 46bd mov sp, r7
80013a0: f85d 7b04 ldr.w r7, [sp], #4
80013a4: 4770 bx lr
80013a6: bf00 nop
80013a8: 200006c0 .word 0x200006c0
80013ac: 200010a0 .word 0x200010a0
080013b0 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
80013b0: b480 push {r7}
80013b2: af00 add r7, sp, #0
return uwTick;
80013b4: 4b03 ldr r3, [pc, #12] ; (80013c4 <HAL_GetTick+0x14>)
80013b6: 681b ldr r3, [r3, #0]
}
80013b8: 4618 mov r0, r3
80013ba: 46bd mov sp, r7
80013bc: f85d 7b04 ldr.w r7, [sp], #4
80013c0: 4770 bx lr
80013c2: bf00 nop
80013c4: 200010a0 .word 0x200010a0
080013c8 <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
80013c8: b580 push {r7, lr}
80013ca: b084 sub sp, #16
80013cc: af00 add r7, sp, #0
80013ce: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
80013d0: f7ff ffee bl 80013b0 <HAL_GetTick>
80013d4: 60b8 str r0, [r7, #8]
uint32_t wait = Delay;
80013d6: 687b ldr r3, [r7, #4]
80013d8: 60fb str r3, [r7, #12]
/* Add a freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
80013da: 68fb ldr r3, [r7, #12]
80013dc: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
80013e0: d005 beq.n 80013ee <HAL_Delay+0x26>
{
wait += (uint32_t)(uwTickFreq);
80013e2: 4b0a ldr r3, [pc, #40] ; (800140c <HAL_Delay+0x44>)
80013e4: 781b ldrb r3, [r3, #0]
80013e6: 461a mov r2, r3
80013e8: 68fb ldr r3, [r7, #12]
80013ea: 4413 add r3, r2
80013ec: 60fb str r3, [r7, #12]
}
while((HAL_GetTick() - tickstart) < wait)
80013ee: bf00 nop
80013f0: f7ff ffde bl 80013b0 <HAL_GetTick>
80013f4: 4602 mov r2, r0
80013f6: 68bb ldr r3, [r7, #8]
80013f8: 1ad3 subs r3, r2, r3
80013fa: 68fa ldr r2, [r7, #12]
80013fc: 429a cmp r2, r3
80013fe: d8f7 bhi.n 80013f0 <HAL_Delay+0x28>
{
}
}
8001400: bf00 nop
8001402: bf00 nop
8001404: 3710 adds r7, #16
8001406: 46bd mov sp, r7
8001408: bd80 pop {r7, pc}
800140a: bf00 nop
800140c: 200006c0 .word 0x200006c0
08001410 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8001410: b480 push {r7}
8001412: b085 sub sp, #20
8001414: af00 add r7, sp, #0
8001416: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8001418: 687b ldr r3, [r7, #4]
800141a: f003 0307 and.w r3, r3, #7
800141e: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8001420: 4b0c ldr r3, [pc, #48] ; (8001454 <__NVIC_SetPriorityGrouping+0x44>)
8001422: 68db ldr r3, [r3, #12]
8001424: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
8001426: 68ba ldr r2, [r7, #8]
8001428: f64f 03ff movw r3, #63743 ; 0xf8ff
800142c: 4013 ands r3, r2
800142e: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8001430: 68fb ldr r3, [r7, #12]
8001432: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8001434: 68bb ldr r3, [r7, #8]
8001436: 4313 orrs r3, r2
reg_value = (reg_value |
8001438: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000
800143c: f443 3300 orr.w r3, r3, #131072 ; 0x20000
8001440: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
8001442: 4a04 ldr r2, [pc, #16] ; (8001454 <__NVIC_SetPriorityGrouping+0x44>)
8001444: 68bb ldr r3, [r7, #8]
8001446: 60d3 str r3, [r2, #12]
}
8001448: bf00 nop
800144a: 3714 adds r7, #20
800144c: 46bd mov sp, r7
800144e: f85d 7b04 ldr.w r7, [sp], #4
8001452: 4770 bx lr
8001454: e000ed00 .word 0xe000ed00
08001458 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
8001458: b480 push {r7}
800145a: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
800145c: 4b04 ldr r3, [pc, #16] ; (8001470 <__NVIC_GetPriorityGrouping+0x18>)
800145e: 68db ldr r3, [r3, #12]
8001460: 0a1b lsrs r3, r3, #8
8001462: f003 0307 and.w r3, r3, #7
}
8001466: 4618 mov r0, r3
8001468: 46bd mov sp, r7
800146a: f85d 7b04 ldr.w r7, [sp], #4
800146e: 4770 bx lr
8001470: e000ed00 .word 0xe000ed00
08001474 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8001474: b480 push {r7}
8001476: b083 sub sp, #12
8001478: af00 add r7, sp, #0
800147a: 4603 mov r3, r0
800147c: 6039 str r1, [r7, #0]
800147e: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8001480: f997 3007 ldrsb.w r3, [r7, #7]
8001484: 2b00 cmp r3, #0
8001486: db0a blt.n 800149e <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8001488: 683b ldr r3, [r7, #0]
800148a: b2da uxtb r2, r3
800148c: 490c ldr r1, [pc, #48] ; (80014c0 <__NVIC_SetPriority+0x4c>)
800148e: f997 3007 ldrsb.w r3, [r7, #7]
8001492: 0112 lsls r2, r2, #4
8001494: b2d2 uxtb r2, r2
8001496: 440b add r3, r1
8001498: f883 2300 strb.w r2, [r3, #768] ; 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
800149c: e00a b.n 80014b4 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
800149e: 683b ldr r3, [r7, #0]
80014a0: b2da uxtb r2, r3
80014a2: 4908 ldr r1, [pc, #32] ; (80014c4 <__NVIC_SetPriority+0x50>)
80014a4: 79fb ldrb r3, [r7, #7]
80014a6: f003 030f and.w r3, r3, #15
80014aa: 3b04 subs r3, #4
80014ac: 0112 lsls r2, r2, #4
80014ae: b2d2 uxtb r2, r2
80014b0: 440b add r3, r1
80014b2: 761a strb r2, [r3, #24]
}
80014b4: bf00 nop
80014b6: 370c adds r7, #12
80014b8: 46bd mov sp, r7
80014ba: f85d 7b04 ldr.w r7, [sp], #4
80014be: 4770 bx lr
80014c0: e000e100 .word 0xe000e100
80014c4: e000ed00 .word 0xe000ed00
080014c8 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
80014c8: b480 push {r7}
80014ca: b089 sub sp, #36 ; 0x24
80014cc: af00 add r7, sp, #0
80014ce: 60f8 str r0, [r7, #12]
80014d0: 60b9 str r1, [r7, #8]
80014d2: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80014d4: 68fb ldr r3, [r7, #12]
80014d6: f003 0307 and.w r3, r3, #7
80014da: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
80014dc: 69fb ldr r3, [r7, #28]
80014de: f1c3 0307 rsb r3, r3, #7
80014e2: 2b04 cmp r3, #4
80014e4: bf28 it cs
80014e6: 2304 movcs r3, #4
80014e8: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
80014ea: 69fb ldr r3, [r7, #28]
80014ec: 3304 adds r3, #4
80014ee: 2b06 cmp r3, #6
80014f0: d902 bls.n 80014f8 <NVIC_EncodePriority+0x30>
80014f2: 69fb ldr r3, [r7, #28]
80014f4: 3b03 subs r3, #3
80014f6: e000 b.n 80014fa <NVIC_EncodePriority+0x32>
80014f8: 2300 movs r3, #0
80014fa: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80014fc: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
8001500: 69bb ldr r3, [r7, #24]
8001502: fa02 f303 lsl.w r3, r2, r3
8001506: 43da mvns r2, r3
8001508: 68bb ldr r3, [r7, #8]
800150a: 401a ands r2, r3
800150c: 697b ldr r3, [r7, #20]
800150e: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8001510: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff
8001514: 697b ldr r3, [r7, #20]
8001516: fa01 f303 lsl.w r3, r1, r3
800151a: 43d9 mvns r1, r3
800151c: 687b ldr r3, [r7, #4]
800151e: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8001520: 4313 orrs r3, r2
);
}
8001522: 4618 mov r0, r3
8001524: 3724 adds r7, #36 ; 0x24
8001526: 46bd mov sp, r7
8001528: f85d 7b04 ldr.w r7, [sp], #4
800152c: 4770 bx lr
...
08001530 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8001530: b580 push {r7, lr}
8001532: b082 sub sp, #8
8001534: af00 add r7, sp, #0
8001536: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8001538: 687b ldr r3, [r7, #4]
800153a: 3b01 subs r3, #1
800153c: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
8001540: d301 bcc.n 8001546 <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
8001542: 2301 movs r3, #1
8001544: e00f b.n 8001566 <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8001546: 4a0a ldr r2, [pc, #40] ; (8001570 <SysTick_Config+0x40>)
8001548: 687b ldr r3, [r7, #4]
800154a: 3b01 subs r3, #1
800154c: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
800154e: 210f movs r1, #15
8001550: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
8001554: f7ff ff8e bl 8001474 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8001558: 4b05 ldr r3, [pc, #20] ; (8001570 <SysTick_Config+0x40>)
800155a: 2200 movs r2, #0
800155c: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
800155e: 4b04 ldr r3, [pc, #16] ; (8001570 <SysTick_Config+0x40>)
8001560: 2207 movs r2, #7
8001562: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8001564: 2300 movs r3, #0
}
8001566: 4618 mov r0, r3
8001568: 3708 adds r7, #8
800156a: 46bd mov sp, r7
800156c: bd80 pop {r7, pc}
800156e: bf00 nop
8001570: e000e010 .word 0xe000e010
08001574 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8001574: b580 push {r7, lr}
8001576: b082 sub sp, #8
8001578: af00 add r7, sp, #0
800157a: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
800157c: 6878 ldr r0, [r7, #4]
800157e: f7ff ff47 bl 8001410 <__NVIC_SetPriorityGrouping>
}
8001582: bf00 nop
8001584: 3708 adds r7, #8
8001586: 46bd mov sp, r7
8001588: bd80 pop {r7, pc}
0800158a <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
800158a: b580 push {r7, lr}
800158c: b086 sub sp, #24
800158e: af00 add r7, sp, #0
8001590: 4603 mov r3, r0
8001592: 60b9 str r1, [r7, #8]
8001594: 607a str r2, [r7, #4]
8001596: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00U;
8001598: 2300 movs r3, #0
800159a: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
800159c: f7ff ff5c bl 8001458 <__NVIC_GetPriorityGrouping>
80015a0: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
80015a2: 687a ldr r2, [r7, #4]
80015a4: 68b9 ldr r1, [r7, #8]
80015a6: 6978 ldr r0, [r7, #20]
80015a8: f7ff ff8e bl 80014c8 <NVIC_EncodePriority>
80015ac: 4602 mov r2, r0
80015ae: f997 300f ldrsb.w r3, [r7, #15]
80015b2: 4611 mov r1, r2
80015b4: 4618 mov r0, r3
80015b6: f7ff ff5d bl 8001474 <__NVIC_SetPriority>
}
80015ba: bf00 nop
80015bc: 3718 adds r7, #24
80015be: 46bd mov sp, r7
80015c0: bd80 pop {r7, pc}
080015c2 <HAL_SYSTICK_Config>:
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
80015c2: b580 push {r7, lr}
80015c4: b082 sub sp, #8
80015c6: af00 add r7, sp, #0
80015c8: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
80015ca: 6878 ldr r0, [r7, #4]
80015cc: f7ff ffb0 bl 8001530 <SysTick_Config>
80015d0: 4603 mov r3, r0
}
80015d2: 4618 mov r0, r3
80015d4: 3708 adds r7, #8
80015d6: 46bd mov sp, r7
80015d8: bd80 pop {r7, pc}
...
080015dc <HAL_ETH_Init>:
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
{
80015dc: b580 push {r7, lr}
80015de: b084 sub sp, #16
80015e0: af00 add r7, sp, #0
80015e2: 6078 str r0, [r7, #4]
uint32_t tickstart;
if (heth == NULL)
80015e4: 687b ldr r3, [r7, #4]
80015e6: 2b00 cmp r3, #0
80015e8: d101 bne.n 80015ee <HAL_ETH_Init+0x12>
{
return HAL_ERROR;
80015ea: 2301 movs r3, #1
80015ec: e08a b.n 8001704 <HAL_ETH_Init+0x128>
}
if (heth->gState == HAL_ETH_STATE_RESET)
80015ee: 687b ldr r3, [r7, #4]
80015f0: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
80015f4: 2b00 cmp r3, #0
80015f6: d106 bne.n 8001606 <HAL_ETH_Init+0x2a>
{
heth->gState = HAL_ETH_STATE_BUSY;
80015f8: 687b ldr r3, [r7, #4]
80015fa: 2220 movs r2, #32
80015fc: f8c3 2084 str.w r2, [r3, #132] ; 0x84
/* Init the low level hardware */
heth->MspInitCallback(heth);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC. */
HAL_ETH_MspInit(heth);
8001600: 6878 ldr r0, [r7, #4]
8001602: f7ff fc47 bl 8000e94 <HAL_ETH_MspInit>
#endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */
}
__HAL_RCC_SYSCFG_CLK_ENABLE();
8001606: 2300 movs r3, #0
8001608: 60bb str r3, [r7, #8]
800160a: 4b40 ldr r3, [pc, #256] ; (800170c <HAL_ETH_Init+0x130>)
800160c: 6c5b ldr r3, [r3, #68] ; 0x44
800160e: 4a3f ldr r2, [pc, #252] ; (800170c <HAL_ETH_Init+0x130>)
8001610: f443 4380 orr.w r3, r3, #16384 ; 0x4000
8001614: 6453 str r3, [r2, #68] ; 0x44
8001616: 4b3d ldr r3, [pc, #244] ; (800170c <HAL_ETH_Init+0x130>)
8001618: 6c5b ldr r3, [r3, #68] ; 0x44
800161a: f403 4380 and.w r3, r3, #16384 ; 0x4000
800161e: 60bb str r3, [r7, #8]
8001620: 68bb ldr r3, [r7, #8]
/* Select MII or RMII Mode*/
SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
8001622: 4b3b ldr r3, [pc, #236] ; (8001710 <HAL_ETH_Init+0x134>)
8001624: 685b ldr r3, [r3, #4]
8001626: 4a3a ldr r2, [pc, #232] ; (8001710 <HAL_ETH_Init+0x134>)
8001628: f423 0300 bic.w r3, r3, #8388608 ; 0x800000
800162c: 6053 str r3, [r2, #4]
SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;
800162e: 4b38 ldr r3, [pc, #224] ; (8001710 <HAL_ETH_Init+0x134>)
8001630: 685a ldr r2, [r3, #4]
8001632: 687b ldr r3, [r7, #4]
8001634: 689b ldr r3, [r3, #8]
8001636: 4936 ldr r1, [pc, #216] ; (8001710 <HAL_ETH_Init+0x134>)
8001638: 4313 orrs r3, r2
800163a: 604b str r3, [r1, #4]
/* Dummy read to sync SYSCFG with ETH */
(void)SYSCFG->PMC;
800163c: 4b34 ldr r3, [pc, #208] ; (8001710 <HAL_ETH_Init+0x134>)
800163e: 685b ldr r3, [r3, #4]
/* Ethernet Software reset */
/* Set the SWR bit: resets all MAC subsystem internal registers and logic */
/* After reset all the registers holds their respective reset values */
SET_BIT(heth->Instance->DMABMR, ETH_DMABMR_SR);
8001640: 687b ldr r3, [r7, #4]
8001642: 681b ldr r3, [r3, #0]
8001644: f503 5380 add.w r3, r3, #4096 ; 0x1000
8001648: 681b ldr r3, [r3, #0]
800164a: 687a ldr r2, [r7, #4]
800164c: 6812 ldr r2, [r2, #0]
800164e: f043 0301 orr.w r3, r3, #1
8001652: f502 5280 add.w r2, r2, #4096 ; 0x1000
8001656: 6013 str r3, [r2, #0]
/* Get tick */
tickstart = HAL_GetTick();
8001658: f7ff feaa bl 80013b0 <HAL_GetTick>
800165c: 60f8 str r0, [r7, #12]
/* Wait for software reset */
while (READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_SR) > 0U)
800165e: e011 b.n 8001684 <HAL_ETH_Init+0xa8>
{
if (((HAL_GetTick() - tickstart) > ETH_SWRESET_TIMEOUT))
8001660: f7ff fea6 bl 80013b0 <HAL_GetTick>
8001664: 4602 mov r2, r0
8001666: 68fb ldr r3, [r7, #12]
8001668: 1ad3 subs r3, r2, r3
800166a: f5b3 7ffa cmp.w r3, #500 ; 0x1f4
800166e: d909 bls.n 8001684 <HAL_ETH_Init+0xa8>
{
/* Set Error Code */
heth->ErrorCode = HAL_ETH_ERROR_TIMEOUT;
8001670: 687b ldr r3, [r7, #4]
8001672: 2204 movs r2, #4
8001674: f8c3 2088 str.w r2, [r3, #136] ; 0x88
/* Set State as Error */
heth->gState = HAL_ETH_STATE_ERROR;
8001678: 687b ldr r3, [r7, #4]
800167a: 22e0 movs r2, #224 ; 0xe0
800167c: f8c3 2084 str.w r2, [r3, #132] ; 0x84
/* Return Error */
return HAL_ERROR;
8001680: 2301 movs r3, #1
8001682: e03f b.n 8001704 <HAL_ETH_Init+0x128>
while (READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_SR) > 0U)
8001684: 687b ldr r3, [r7, #4]
8001686: 681b ldr r3, [r3, #0]
8001688: f503 5380 add.w r3, r3, #4096 ; 0x1000
800168c: 681b ldr r3, [r3, #0]
800168e: f003 0301 and.w r3, r3, #1
8001692: 2b00 cmp r3, #0
8001694: d1e4 bne.n 8001660 <HAL_ETH_Init+0x84>
}
}
/*------------------ MAC, MTL and DMA default Configuration ----------------*/
ETH_MACDMAConfig(heth);
8001696: 6878 ldr r0, [r7, #4]
8001698: f000 f97a bl 8001990 <ETH_MACDMAConfig>
/*------------------ DMA Tx Descriptors Configuration ----------------------*/
ETH_DMATxDescListInit(heth);
800169c: 6878 ldr r0, [r7, #4]
800169e: f000 fa25 bl 8001aec <ETH_DMATxDescListInit>
/*------------------ DMA Rx Descriptors Configuration ----------------------*/
ETH_DMARxDescListInit(heth);
80016a2: 6878 ldr r0, [r7, #4]
80016a4: f000 fa7b bl 8001b9e <ETH_DMARxDescListInit>
/*--------------------- ETHERNET MAC Address Configuration ------------------*/
ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
80016a8: 687b ldr r3, [r7, #4]
80016aa: 685b ldr r3, [r3, #4]
80016ac: 461a mov r2, r3
80016ae: 2100 movs r1, #0
80016b0: 6878 ldr r0, [r7, #4]
80016b2: f000 f9e3 bl 8001a7c <ETH_MACAddressConfig>
/* Disable MMC Interrupts */
SET_BIT(heth->Instance->MACIMR, ETH_MACIMR_TSTIM | ETH_MACIMR_PMTIM);
80016b6: 687b ldr r3, [r7, #4]
80016b8: 681b ldr r3, [r3, #0]
80016ba: 6bda ldr r2, [r3, #60] ; 0x3c
80016bc: 687b ldr r3, [r7, #4]
80016be: 681b ldr r3, [r3, #0]
80016c0: f442 7202 orr.w r2, r2, #520 ; 0x208
80016c4: 63da str r2, [r3, #60] ; 0x3c
/* Disable Rx MMC Interrupts */
SET_BIT(heth->Instance->MMCRIMR, ETH_MMCRIMR_RGUFM | ETH_MMCRIMR_RFAEM | \
80016c6: 687b ldr r3, [r7, #4]
80016c8: 681b ldr r3, [r3, #0]
80016ca: f8d3 310c ldr.w r3, [r3, #268] ; 0x10c
80016ce: 687a ldr r2, [r7, #4]
80016d0: 6812 ldr r2, [r2, #0]
80016d2: f443 3300 orr.w r3, r3, #131072 ; 0x20000
80016d6: f043 0360 orr.w r3, r3, #96 ; 0x60
80016da: f8c2 310c str.w r3, [r2, #268] ; 0x10c
ETH_MMCRIMR_RFCEM);
/* Disable Tx MMC Interrupts */
SET_BIT(heth->Instance->MMCTIMR, ETH_MMCTIMR_TGFM | ETH_MMCTIMR_TGFMSCM | \
80016de: 687b ldr r3, [r7, #4]
80016e0: 681b ldr r3, [r3, #0]
80016e2: f8d3 2110 ldr.w r2, [r3, #272] ; 0x110
80016e6: 687b ldr r3, [r7, #4]
80016e8: 681b ldr r3, [r3, #0]
80016ea: f442 1203 orr.w r2, r2, #2146304 ; 0x20c000
80016ee: f8c3 2110 str.w r2, [r3, #272] ; 0x110
ETH_MMCTIMR_TGFSCM);
heth->ErrorCode = HAL_ETH_ERROR_NONE;
80016f2: 687b ldr r3, [r7, #4]
80016f4: 2200 movs r2, #0
80016f6: f8c3 2088 str.w r2, [r3, #136] ; 0x88
heth->gState = HAL_ETH_STATE_READY;
80016fa: 687b ldr r3, [r7, #4]
80016fc: 2210 movs r2, #16
80016fe: f8c3 2084 str.w r2, [r3, #132] ; 0x84
return HAL_OK;
8001702: 2300 movs r3, #0
}
8001704: 4618 mov r0, r3
8001706: 3710 adds r7, #16
8001708: 46bd mov sp, r7
800170a: bd80 pop {r7, pc}
800170c: 40023800 .word 0x40023800
8001710: 40013800 .word 0x40013800
08001714 <ETH_SetMACConfig>:
HAL_Delay(ETH_REG_WRITE_DELAY);
(heth->Instance)->DMAOMR = tmpreg;
}
static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, const ETH_MACConfigTypeDef *macconf)
{
8001714: b580 push {r7, lr}
8001716: b084 sub sp, #16
8001718: af00 add r7, sp, #0
800171a: 6078 str r0, [r7, #4]
800171c: 6039 str r1, [r7, #0]
uint32_t tmpreg1;
/*------------------------ ETHERNET MACCR Configuration --------------------*/
/* Get the ETHERNET MACCR value */
tmpreg1 = (heth->Instance)->MACCR;
800171e: 687b ldr r3, [r7, #4]
8001720: 681b ldr r3, [r3, #0]
8001722: 681b ldr r3, [r3, #0]
8001724: 60fb str r3, [r7, #12]
/* Clear CSTF, WD, PCE, PS, TE and RE bits */
tmpreg1 &= ETH_MACCR_CLEAR_MASK;
8001726: 68fa ldr r2, [r7, #12]
8001728: 4b53 ldr r3, [pc, #332] ; (8001878 <ETH_SetMACConfig+0x164>)
800172a: 4013 ands r3, r2
800172c: 60fb str r3, [r7, #12]
tmpreg1 |= (uint32_t)(((uint32_t)macconf->CRCStripTypePacket << 25U) |
800172e: 683b ldr r3, [r7, #0]
8001730: 7b9b ldrb r3, [r3, #14]
8001732: 065b lsls r3, r3, #25
((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 23U) |
8001734: 683a ldr r2, [r7, #0]
8001736: 7c12 ldrb r2, [r2, #16]
8001738: 2a00 cmp r2, #0
800173a: d102 bne.n 8001742 <ETH_SetMACConfig+0x2e>
800173c: f44f 0200 mov.w r2, #8388608 ; 0x800000
8001740: e000 b.n 8001744 <ETH_SetMACConfig+0x30>
8001742: 2200 movs r2, #0
tmpreg1 |= (uint32_t)(((uint32_t)macconf->CRCStripTypePacket << 25U) |
8001744: 4313 orrs r3, r2
((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 22U) |
8001746: 683a ldr r2, [r7, #0]
8001748: 7c52 ldrb r2, [r2, #17]
800174a: 2a00 cmp r2, #0
800174c: d102 bne.n 8001754 <ETH_SetMACConfig+0x40>
800174e: f44f 0280 mov.w r2, #4194304 ; 0x400000
8001752: e000 b.n 8001756 <ETH_SetMACConfig+0x42>
8001754: 2200 movs r2, #0
((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 23U) |
8001756: 431a orrs r2, r3
(uint32_t)macconf->InterPacketGapVal |
8001758: 683b ldr r3, [r7, #0]
800175a: 689b ldr r3, [r3, #8]
((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 22U) |
800175c: 431a orrs r2, r3
((uint32_t)macconf->CarrierSenseDuringTransmit << 16U) |
800175e: 683b ldr r3, [r7, #0]
8001760: 7fdb ldrb r3, [r3, #31]
8001762: 041b lsls r3, r3, #16
(uint32_t)macconf->InterPacketGapVal |
8001764: 431a orrs r2, r3
macconf->Speed |
8001766: 683b ldr r3, [r7, #0]
8001768: 695b ldr r3, [r3, #20]
((uint32_t)macconf->CarrierSenseDuringTransmit << 16U) |
800176a: 4313 orrs r3, r2
((uint32_t)((macconf->ReceiveOwn == DISABLE) ? 1U : 0U) << 13U) |
800176c: 683a ldr r2, [r7, #0]
800176e: 7f92 ldrb r2, [r2, #30]
8001770: 2a00 cmp r2, #0
8001772: d102 bne.n 800177a <ETH_SetMACConfig+0x66>
8001774: f44f 5200 mov.w r2, #8192 ; 0x2000
8001778: e000 b.n 800177c <ETH_SetMACConfig+0x68>
800177a: 2200 movs r2, #0
macconf->Speed |
800177c: 431a orrs r2, r3
((uint32_t)macconf->LoopbackMode << 12U) |
800177e: 683b ldr r3, [r7, #0]
8001780: 7f1b ldrb r3, [r3, #28]
8001782: 031b lsls r3, r3, #12
((uint32_t)((macconf->ReceiveOwn == DISABLE) ? 1U : 0U) << 13U) |
8001784: 431a orrs r2, r3
macconf->DuplexMode |
8001786: 683b ldr r3, [r7, #0]
8001788: 699b ldr r3, [r3, #24]
((uint32_t)macconf->LoopbackMode << 12U) |
800178a: 431a orrs r2, r3
((uint32_t)macconf->ChecksumOffload << 10U) |
800178c: 683b ldr r3, [r7, #0]
800178e: 791b ldrb r3, [r3, #4]
8001790: 029b lsls r3, r3, #10
macconf->DuplexMode |
8001792: 4313 orrs r3, r2
((uint32_t)((macconf->RetryTransmission == DISABLE) ? 1U : 0U) << 9U) |
8001794: 683a ldr r2, [r7, #0]
8001796: f892 2020 ldrb.w r2, [r2, #32]
800179a: 2a00 cmp r2, #0
800179c: d102 bne.n 80017a4 <ETH_SetMACConfig+0x90>
800179e: f44f 7200 mov.w r2, #512 ; 0x200
80017a2: e000 b.n 80017a6 <ETH_SetMACConfig+0x92>
80017a4: 2200 movs r2, #0
((uint32_t)macconf->ChecksumOffload << 10U) |
80017a6: 431a orrs r2, r3
((uint32_t)macconf->AutomaticPadCRCStrip << 7U) |
80017a8: 683b ldr r3, [r7, #0]
80017aa: 7bdb ldrb r3, [r3, #15]
80017ac: 01db lsls r3, r3, #7
((uint32_t)((macconf->RetryTransmission == DISABLE) ? 1U : 0U) << 9U) |
80017ae: 431a orrs r2, r3
macconf->BackOffLimit |
80017b0: 683b ldr r3, [r7, #0]
80017b2: 6a5b ldr r3, [r3, #36] ; 0x24
((uint32_t)macconf->AutomaticPadCRCStrip << 7U) |
80017b4: 431a orrs r2, r3
((uint32_t)macconf->DeferralCheck << 4U));
80017b6: 683b ldr r3, [r7, #0]
80017b8: f893 3028 ldrb.w r3, [r3, #40] ; 0x28
80017bc: 011b lsls r3, r3, #4
tmpreg1 |= (uint32_t)(((uint32_t)macconf->CRCStripTypePacket << 25U) |
80017be: 4313 orrs r3, r2
80017c0: 68fa ldr r2, [r7, #12]
80017c2: 4313 orrs r3, r2
80017c4: 60fb str r3, [r7, #12]
/* Write to ETHERNET MACCR */
(heth->Instance)->MACCR = (uint32_t)tmpreg1;
80017c6: 687b ldr r3, [r7, #4]
80017c8: 681b ldr r3, [r3, #0]
80017ca: 68fa ldr r2, [r7, #12]
80017cc: 601a str r2, [r3, #0]
/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
tmpreg1 = (heth->Instance)->MACCR;
80017ce: 687b ldr r3, [r7, #4]
80017d0: 681b ldr r3, [r3, #0]
80017d2: 681b ldr r3, [r3, #0]
80017d4: 60fb str r3, [r7, #12]
HAL_Delay(ETH_REG_WRITE_DELAY);
80017d6: 2001 movs r0, #1
80017d8: f7ff fdf6 bl 80013c8 <HAL_Delay>
(heth->Instance)->MACCR = tmpreg1;
80017dc: 687b ldr r3, [r7, #4]
80017de: 681b ldr r3, [r3, #0]
80017e0: 68fa ldr r2, [r7, #12]
80017e2: 601a str r2, [r3, #0]
/*----------------------- ETHERNET MACFCR Configuration --------------------*/
/* Get the ETHERNET MACFCR value */
tmpreg1 = (heth->Instance)->MACFCR;
80017e4: 687b ldr r3, [r7, #4]
80017e6: 681b ldr r3, [r3, #0]
80017e8: 699b ldr r3, [r3, #24]
80017ea: 60fb str r3, [r7, #12]
/* Clear xx bits */
tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
80017ec: 68fa ldr r2, [r7, #12]
80017ee: f64f 7341 movw r3, #65345 ; 0xff41
80017f2: 4013 ands r3, r2
80017f4: 60fb str r3, [r7, #12]
tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) |
80017f6: 683b ldr r3, [r7, #0]
80017f8: 6c9b ldr r3, [r3, #72] ; 0x48
80017fa: 041b lsls r3, r3, #16
((uint32_t)((macconf->ZeroQuantaPause == DISABLE) ? 1U : 0U) << 7U) |
80017fc: 683a ldr r2, [r7, #0]
80017fe: f892 204c ldrb.w r2, [r2, #76] ; 0x4c
8001802: 2a00 cmp r2, #0
8001804: d101 bne.n 800180a <ETH_SetMACConfig+0xf6>
8001806: 2280 movs r2, #128 ; 0x80
8001808: e000 b.n 800180c <ETH_SetMACConfig+0xf8>
800180a: 2200 movs r2, #0
tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) |
800180c: 431a orrs r2, r3
macconf->PauseLowThreshold |
800180e: 683b ldr r3, [r7, #0]
8001810: 6d1b ldr r3, [r3, #80] ; 0x50
((uint32_t)((macconf->ZeroQuantaPause == DISABLE) ? 1U : 0U) << 7U) |
8001812: 4313 orrs r3, r2
((uint32_t)((macconf->UnicastPausePacketDetect == ENABLE) ? 1U : 0U) << 3U) |
8001814: 683a ldr r2, [r7, #0]
8001816: f892 2055 ldrb.w r2, [r2, #85] ; 0x55
800181a: 2a01 cmp r2, #1
800181c: d101 bne.n 8001822 <ETH_SetMACConfig+0x10e>
800181e: 2208 movs r2, #8
8001820: e000 b.n 8001824 <ETH_SetMACConfig+0x110>
8001822: 2200 movs r2, #0
macconf->PauseLowThreshold |
8001824: 4313 orrs r3, r2
((uint32_t)((macconf->ReceiveFlowControl == ENABLE) ? 1U : 0U) << 2U) |
8001826: 683a ldr r2, [r7, #0]
8001828: f892 2056 ldrb.w r2, [r2, #86] ; 0x56
800182c: 2a01 cmp r2, #1
800182e: d101 bne.n 8001834 <ETH_SetMACConfig+0x120>
8001830: 2204 movs r2, #4
8001832: e000 b.n 8001836 <ETH_SetMACConfig+0x122>
8001834: 2200 movs r2, #0
((uint32_t)((macconf->UnicastPausePacketDetect == ENABLE) ? 1U : 0U) << 3U) |
8001836: 4313 orrs r3, r2
((uint32_t)((macconf->TransmitFlowControl == ENABLE) ? 1U : 0U) << 1U));
8001838: 683a ldr r2, [r7, #0]
800183a: f892 2054 ldrb.w r2, [r2, #84] ; 0x54
800183e: 2a01 cmp r2, #1
8001840: d101 bne.n 8001846 <ETH_SetMACConfig+0x132>
8001842: 2202 movs r2, #2
8001844: e000 b.n 8001848 <ETH_SetMACConfig+0x134>
8001846: 2200 movs r2, #0
tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) |
8001848: 4313 orrs r3, r2
800184a: 68fa ldr r2, [r7, #12]
800184c: 4313 orrs r3, r2
800184e: 60fb str r3, [r7, #12]
/* Write to ETHERNET MACFCR */
(heth->Instance)->MACFCR = (uint32_t)tmpreg1;
8001850: 687b ldr r3, [r7, #4]
8001852: 681b ldr r3, [r3, #0]
8001854: 68fa ldr r2, [r7, #12]
8001856: 619a str r2, [r3, #24]
/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
tmpreg1 = (heth->Instance)->MACFCR;
8001858: 687b ldr r3, [r7, #4]
800185a: 681b ldr r3, [r3, #0]
800185c: 699b ldr r3, [r3, #24]
800185e: 60fb str r3, [r7, #12]
HAL_Delay(ETH_REG_WRITE_DELAY);
8001860: 2001 movs r0, #1
8001862: f7ff fdb1 bl 80013c8 <HAL_Delay>
(heth->Instance)->MACFCR = tmpreg1;
8001866: 687b ldr r3, [r7, #4]
8001868: 681b ldr r3, [r3, #0]
800186a: 68fa ldr r2, [r7, #12]
800186c: 619a str r2, [r3, #24]
}
800186e: bf00 nop
8001870: 3710 adds r7, #16
8001872: 46bd mov sp, r7
8001874: bd80 pop {r7, pc}
8001876: bf00 nop
8001878: fd20810f .word 0xfd20810f
0800187c <ETH_SetDMAConfig>:
static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, const ETH_DMAConfigTypeDef *dmaconf)
{
800187c: b580 push {r7, lr}
800187e: b084 sub sp, #16
8001880: af00 add r7, sp, #0
8001882: 6078 str r0, [r7, #4]
8001884: 6039 str r1, [r7, #0]
uint32_t tmpreg1;
/*----------------------- ETHERNET DMAOMR Configuration --------------------*/
/* Get the ETHERNET DMAOMR value */
tmpreg1 = (heth->Instance)->DMAOMR;
8001886: 687b ldr r3, [r7, #4]
8001888: 681b ldr r3, [r3, #0]
800188a: f503 5380 add.w r3, r3, #4096 ; 0x1000
800188e: 699b ldr r3, [r3, #24]
8001890: 60fb str r3, [r7, #12]
/* Clear xx bits */
tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
8001892: 68fa ldr r2, [r7, #12]
8001894: 4b3d ldr r3, [pc, #244] ; (800198c <ETH_SetDMAConfig+0x110>)
8001896: 4013 ands r3, r2
8001898: 60fb str r3, [r7, #12]
tmpreg1 |= (uint32_t)(((uint32_t)((dmaconf->DropTCPIPChecksumErrorFrame == DISABLE) ? 1U : 0U) << 26U) |
800189a: 683b ldr r3, [r7, #0]
800189c: 7b1b ldrb r3, [r3, #12]
800189e: 2b00 cmp r3, #0
80018a0: d102 bne.n 80018a8 <ETH_SetDMAConfig+0x2c>
80018a2: f04f 6280 mov.w r2, #67108864 ; 0x4000000
80018a6: e000 b.n 80018aa <ETH_SetDMAConfig+0x2e>
80018a8: 2200 movs r2, #0
((uint32_t)dmaconf->ReceiveStoreForward << 25U) |
80018aa: 683b ldr r3, [r7, #0]
80018ac: 7b5b ldrb r3, [r3, #13]
80018ae: 065b lsls r3, r3, #25
tmpreg1 |= (uint32_t)(((uint32_t)((dmaconf->DropTCPIPChecksumErrorFrame == DISABLE) ? 1U : 0U) << 26U) |
80018b0: 4313 orrs r3, r2
((uint32_t)((dmaconf->FlushRxPacket == DISABLE) ? 1U : 0U) << 20U) |
80018b2: 683a ldr r2, [r7, #0]
80018b4: 7f52 ldrb r2, [r2, #29]
80018b6: 2a00 cmp r2, #0
80018b8: d102 bne.n 80018c0 <ETH_SetDMAConfig+0x44>
80018ba: f44f 1280 mov.w r2, #1048576 ; 0x100000
80018be: e000 b.n 80018c2 <ETH_SetDMAConfig+0x46>
80018c0: 2200 movs r2, #0
((uint32_t)dmaconf->ReceiveStoreForward << 25U) |
80018c2: 431a orrs r2, r3
((uint32_t)dmaconf->TransmitStoreForward << 21U) |
80018c4: 683b ldr r3, [r7, #0]
80018c6: 7b9b ldrb r3, [r3, #14]
80018c8: 055b lsls r3, r3, #21
((uint32_t)((dmaconf->FlushRxPacket == DISABLE) ? 1U : 0U) << 20U) |
80018ca: 431a orrs r2, r3
dmaconf->TransmitThresholdControl |
80018cc: 683b ldr r3, [r7, #0]
80018ce: 695b ldr r3, [r3, #20]
((uint32_t)dmaconf->TransmitStoreForward << 21U) |
80018d0: 431a orrs r2, r3
((uint32_t)dmaconf->ForwardErrorFrames << 7U) |
80018d2: 683b ldr r3, [r7, #0]
80018d4: 7f1b ldrb r3, [r3, #28]
80018d6: 01db lsls r3, r3, #7
dmaconf->TransmitThresholdControl |
80018d8: 431a orrs r2, r3
((uint32_t)dmaconf->ForwardUndersizedGoodFrames << 6U) |
80018da: 683b ldr r3, [r7, #0]
80018dc: 7f9b ldrb r3, [r3, #30]
80018de: 019b lsls r3, r3, #6
((uint32_t)dmaconf->ForwardErrorFrames << 7U) |
80018e0: 431a orrs r2, r3
dmaconf->ReceiveThresholdControl |
80018e2: 683b ldr r3, [r7, #0]
80018e4: 6a1b ldr r3, [r3, #32]
((uint32_t)dmaconf->ForwardUndersizedGoodFrames << 6U) |
80018e6: 431a orrs r2, r3
((uint32_t)dmaconf->SecondFrameOperate << 2U));
80018e8: 683b ldr r3, [r7, #0]
80018ea: f893 3024 ldrb.w r3, [r3, #36] ; 0x24
80018ee: 009b lsls r3, r3, #2
tmpreg1 |= (uint32_t)(((uint32_t)((dmaconf->DropTCPIPChecksumErrorFrame == DISABLE) ? 1U : 0U) << 26U) |
80018f0: 4313 orrs r3, r2
80018f2: 68fa ldr r2, [r7, #12]
80018f4: 4313 orrs r3, r2
80018f6: 60fb str r3, [r7, #12]
/* Write to ETHERNET DMAOMR */
(heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
80018f8: 687b ldr r3, [r7, #4]
80018fa: 681b ldr r3, [r3, #0]
80018fc: f503 5380 add.w r3, r3, #4096 ; 0x1000
8001900: 461a mov r2, r3
8001902: 68fb ldr r3, [r7, #12]
8001904: 6193 str r3, [r2, #24]
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg1 = (heth->Instance)->DMAOMR;
8001906: 687b ldr r3, [r7, #4]
8001908: 681b ldr r3, [r3, #0]
800190a: f503 5380 add.w r3, r3, #4096 ; 0x1000
800190e: 699b ldr r3, [r3, #24]
8001910: 60fb str r3, [r7, #12]
HAL_Delay(ETH_REG_WRITE_DELAY);
8001912: 2001 movs r0, #1
8001914: f7ff fd58 bl 80013c8 <HAL_Delay>
(heth->Instance)->DMAOMR = tmpreg1;
8001918: 687b ldr r3, [r7, #4]
800191a: 681b ldr r3, [r3, #0]
800191c: f503 5380 add.w r3, r3, #4096 ; 0x1000
8001920: 461a mov r2, r3
8001922: 68fb ldr r3, [r7, #12]
8001924: 6193 str r3, [r2, #24]
/*----------------------- ETHERNET DMABMR Configuration --------------------*/
(heth->Instance)->DMABMR = (uint32_t)(((uint32_t)dmaconf->AddressAlignedBeats << 25U) |
8001926: 683b ldr r3, [r7, #0]
8001928: 791b ldrb r3, [r3, #4]
800192a: 065a lsls r2, r3, #25
dmaconf->BurstMode |
800192c: 683b ldr r3, [r7, #0]
800192e: 689b ldr r3, [r3, #8]
(heth->Instance)->DMABMR = (uint32_t)(((uint32_t)dmaconf->AddressAlignedBeats << 25U) |
8001930: 431a orrs r2, r3
dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or
8001932: 683b ldr r3, [r7, #0]
8001934: 699b ldr r3, [r3, #24]
dmaconf->BurstMode |
8001936: 431a orrs r2, r3
Rx it is applied for the other */
dmaconf->TxDMABurstLength |
8001938: 683b ldr r3, [r7, #0]
800193a: 691b ldr r3, [r3, #16]
dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or
800193c: 431a orrs r2, r3
((uint32_t)dmaconf->EnhancedDescriptorFormat << 7U) |
800193e: 683b ldr r3, [r7, #0]
8001940: f893 3025 ldrb.w r3, [r3, #37] ; 0x25
8001944: 01db lsls r3, r3, #7
dmaconf->TxDMABurstLength |
8001946: 431a orrs r2, r3
(dmaconf->DescriptorSkipLength << 2U) |
8001948: 683b ldr r3, [r7, #0]
800194a: 6a9b ldr r3, [r3, #40] ; 0x28
800194c: 009b lsls r3, r3, #2
((uint32_t)dmaconf->EnhancedDescriptorFormat << 7U) |
800194e: 431a orrs r2, r3
dmaconf->DMAArbitration |
8001950: 683b ldr r3, [r7, #0]
8001952: 681b ldr r3, [r3, #0]
(dmaconf->DescriptorSkipLength << 2U) |
8001954: 4313 orrs r3, r2
(heth->Instance)->DMABMR = (uint32_t)(((uint32_t)dmaconf->AddressAlignedBeats << 25U) |
8001956: 687a ldr r2, [r7, #4]
8001958: 6812 ldr r2, [r2, #0]
800195a: f443 0300 orr.w r3, r3, #8388608 ; 0x800000
800195e: f502 5280 add.w r2, r2, #4096 ; 0x1000
8001962: 6013 str r3, [r2, #0]
ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg1 = (heth->Instance)->DMABMR;
8001964: 687b ldr r3, [r7, #4]
8001966: 681b ldr r3, [r3, #0]
8001968: f503 5380 add.w r3, r3, #4096 ; 0x1000
800196c: 681b ldr r3, [r3, #0]
800196e: 60fb str r3, [r7, #12]
HAL_Delay(ETH_REG_WRITE_DELAY);
8001970: 2001 movs r0, #1
8001972: f7ff fd29 bl 80013c8 <HAL_Delay>
(heth->Instance)->DMABMR = tmpreg1;
8001976: 687b ldr r3, [r7, #4]
8001978: 681b ldr r3, [r3, #0]
800197a: f503 5380 add.w r3, r3, #4096 ; 0x1000
800197e: 461a mov r2, r3
8001980: 68fb ldr r3, [r7, #12]
8001982: 6013 str r3, [r2, #0]
}
8001984: bf00 nop
8001986: 3710 adds r7, #16
8001988: 46bd mov sp, r7
800198a: bd80 pop {r7, pc}
800198c: f8de3f23 .word 0xf8de3f23
08001990 <ETH_MACDMAConfig>:
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL status
*/
static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth)
{
8001990: b580 push {r7, lr}
8001992: b0a6 sub sp, #152 ; 0x98
8001994: af00 add r7, sp, #0
8001996: 6078 str r0, [r7, #4]
ETH_MACConfigTypeDef macDefaultConf;
ETH_DMAConfigTypeDef dmaDefaultConf;
/*--------------- ETHERNET MAC registers default Configuration --------------*/
macDefaultConf.Watchdog = ENABLE;
8001998: 2301 movs r3, #1
800199a: f887 3044 strb.w r3, [r7, #68] ; 0x44
macDefaultConf.Jabber = ENABLE;
800199e: 2301 movs r3, #1
80019a0: f887 3045 strb.w r3, [r7, #69] ; 0x45
macDefaultConf.InterPacketGapVal = ETH_INTERFRAMEGAP_96BIT;
80019a4: 2300 movs r3, #0
80019a6: 63fb str r3, [r7, #60] ; 0x3c
macDefaultConf.CarrierSenseDuringTransmit = DISABLE;
80019a8: 2300 movs r3, #0
80019aa: f887 3053 strb.w r3, [r7, #83] ; 0x53
macDefaultConf.ReceiveOwn = ENABLE;
80019ae: 2301 movs r3, #1
80019b0: f887 3052 strb.w r3, [r7, #82] ; 0x52
macDefaultConf.LoopbackMode = DISABLE;
80019b4: 2300 movs r3, #0
80019b6: f887 3050 strb.w r3, [r7, #80] ; 0x50
macDefaultConf.CRCStripTypePacket = ENABLE;
80019ba: 2301 movs r3, #1
80019bc: f887 3042 strb.w r3, [r7, #66] ; 0x42
macDefaultConf.ChecksumOffload = ENABLE;
80019c0: 2301 movs r3, #1
80019c2: f887 3038 strb.w r3, [r7, #56] ; 0x38
macDefaultConf.RetryTransmission = DISABLE;
80019c6: 2300 movs r3, #0
80019c8: f887 3054 strb.w r3, [r7, #84] ; 0x54
macDefaultConf.AutomaticPadCRCStrip = DISABLE;
80019cc: 2300 movs r3, #0
80019ce: f887 3043 strb.w r3, [r7, #67] ; 0x43
macDefaultConf.BackOffLimit = ETH_BACKOFFLIMIT_10;
80019d2: 2300 movs r3, #0
80019d4: 65bb str r3, [r7, #88] ; 0x58
macDefaultConf.DeferralCheck = DISABLE;
80019d6: 2300 movs r3, #0
80019d8: f887 305c strb.w r3, [r7, #92] ; 0x5c
macDefaultConf.PauseTime = 0x0U;
80019dc: 2300 movs r3, #0
80019de: 67fb str r3, [r7, #124] ; 0x7c
macDefaultConf.ZeroQuantaPause = DISABLE;
80019e0: 2300 movs r3, #0
80019e2: f887 3080 strb.w r3, [r7, #128] ; 0x80
macDefaultConf.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
80019e6: 2300 movs r3, #0
80019e8: f8c7 3084 str.w r3, [r7, #132] ; 0x84
macDefaultConf.ReceiveFlowControl = DISABLE;
80019ec: 2300 movs r3, #0
80019ee: f887 308a strb.w r3, [r7, #138] ; 0x8a
macDefaultConf.TransmitFlowControl = DISABLE;
80019f2: 2300 movs r3, #0
80019f4: f887 3088 strb.w r3, [r7, #136] ; 0x88
macDefaultConf.Speed = ETH_SPEED_100M;
80019f8: f44f 4380 mov.w r3, #16384 ; 0x4000
80019fc: 64bb str r3, [r7, #72] ; 0x48
macDefaultConf.DuplexMode = ETH_FULLDUPLEX_MODE;
80019fe: f44f 6300 mov.w r3, #2048 ; 0x800
8001a02: 64fb str r3, [r7, #76] ; 0x4c
macDefaultConf.UnicastPausePacketDetect = DISABLE;
8001a04: 2300 movs r3, #0
8001a06: f887 3089 strb.w r3, [r7, #137] ; 0x89
/* MAC default configuration */
ETH_SetMACConfig(heth, &macDefaultConf);
8001a0a: f107 0334 add.w r3, r7, #52 ; 0x34
8001a0e: 4619 mov r1, r3
8001a10: 6878 ldr r0, [r7, #4]
8001a12: f7ff fe7f bl 8001714 <ETH_SetMACConfig>
/*--------------- ETHERNET DMA registers default Configuration --------------*/
dmaDefaultConf.DropTCPIPChecksumErrorFrame = ENABLE;
8001a16: 2301 movs r3, #1
8001a18: 753b strb r3, [r7, #20]
dmaDefaultConf.ReceiveStoreForward = ENABLE;
8001a1a: 2301 movs r3, #1
8001a1c: 757b strb r3, [r7, #21]
dmaDefaultConf.FlushRxPacket = ENABLE;
8001a1e: 2301 movs r3, #1
8001a20: f887 3025 strb.w r3, [r7, #37] ; 0x25
dmaDefaultConf.TransmitStoreForward = ENABLE;
8001a24: 2301 movs r3, #1
8001a26: 75bb strb r3, [r7, #22]
dmaDefaultConf.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
8001a28: 2300 movs r3, #0
8001a2a: 61fb str r3, [r7, #28]
dmaDefaultConf.ForwardErrorFrames = DISABLE;
8001a2c: 2300 movs r3, #0
8001a2e: f887 3024 strb.w r3, [r7, #36] ; 0x24
dmaDefaultConf.ForwardUndersizedGoodFrames = DISABLE;
8001a32: 2300 movs r3, #0
8001a34: f887 3026 strb.w r3, [r7, #38] ; 0x26
dmaDefaultConf.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
8001a38: 2300 movs r3, #0
8001a3a: 62bb str r3, [r7, #40] ; 0x28
dmaDefaultConf.SecondFrameOperate = ENABLE;
8001a3c: 2301 movs r3, #1
8001a3e: f887 302c strb.w r3, [r7, #44] ; 0x2c
dmaDefaultConf.AddressAlignedBeats = ENABLE;
8001a42: 2301 movs r3, #1
8001a44: 733b strb r3, [r7, #12]
dmaDefaultConf.BurstMode = ETH_BURSTLENGTH_FIXED;
8001a46: f44f 3380 mov.w r3, #65536 ; 0x10000
8001a4a: 613b str r3, [r7, #16]
dmaDefaultConf.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
8001a4c: f44f 0380 mov.w r3, #4194304 ; 0x400000
8001a50: 623b str r3, [r7, #32]
dmaDefaultConf.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
8001a52: f44f 5300 mov.w r3, #8192 ; 0x2000
8001a56: 61bb str r3, [r7, #24]
dmaDefaultConf.EnhancedDescriptorFormat = ENABLE;
8001a58: 2301 movs r3, #1
8001a5a: f887 302d strb.w r3, [r7, #45] ; 0x2d
dmaDefaultConf.DescriptorSkipLength = 0x0U;
8001a5e: 2300 movs r3, #0
8001a60: 633b str r3, [r7, #48] ; 0x30
dmaDefaultConf.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
8001a62: 2300 movs r3, #0
8001a64: 60bb str r3, [r7, #8]
/* DMA default configuration */
ETH_SetDMAConfig(heth, &dmaDefaultConf);
8001a66: f107 0308 add.w r3, r7, #8
8001a6a: 4619 mov r1, r3
8001a6c: 6878 ldr r0, [r7, #4]
8001a6e: f7ff ff05 bl 800187c <ETH_SetDMAConfig>
}
8001a72: bf00 nop
8001a74: 3798 adds r7, #152 ; 0x98
8001a76: 46bd mov sp, r7
8001a78: bd80 pop {r7, pc}
...
08001a7c <ETH_MACAddressConfig>:
* @arg ETH_MAC_Address3: MAC Address3
* @param Addr Pointer to MAC address buffer data (6 bytes)
* @retval HAL status
*/
static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
{
8001a7c: b480 push {r7}
8001a7e: b087 sub sp, #28
8001a80: af00 add r7, sp, #0
8001a82: 60f8 str r0, [r7, #12]
8001a84: 60b9 str r1, [r7, #8]
8001a86: 607a str r2, [r7, #4]
/* Prevent unused argument(s) compilation warning */
UNUSED(heth);
/* Calculate the selected MAC address high register */
tmpreg1 = ((uint32_t)Addr[5U] << 8U) | (uint32_t)Addr[4U];
8001a88: 687b ldr r3, [r7, #4]
8001a8a: 3305 adds r3, #5
8001a8c: 781b ldrb r3, [r3, #0]
8001a8e: 021b lsls r3, r3, #8
8001a90: 687a ldr r2, [r7, #4]
8001a92: 3204 adds r2, #4
8001a94: 7812 ldrb r2, [r2, #0]
8001a96: 4313 orrs r3, r2
8001a98: 617b str r3, [r7, #20]
/* Load the selected MAC address high register */
(*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg1;
8001a9a: 68ba ldr r2, [r7, #8]
8001a9c: 4b11 ldr r3, [pc, #68] ; (8001ae4 <ETH_MACAddressConfig+0x68>)
8001a9e: 4413 add r3, r2
8001aa0: 461a mov r2, r3
8001aa2: 697b ldr r3, [r7, #20]
8001aa4: 6013 str r3, [r2, #0]
/* Calculate the selected MAC address low register */
tmpreg1 = ((uint32_t)Addr[3U] << 24U) | ((uint32_t)Addr[2U] << 16U) | ((uint32_t)Addr[1U] << 8U) | Addr[0U];
8001aa6: 687b ldr r3, [r7, #4]
8001aa8: 3303 adds r3, #3
8001aaa: 781b ldrb r3, [r3, #0]
8001aac: 061a lsls r2, r3, #24
8001aae: 687b ldr r3, [r7, #4]
8001ab0: 3302 adds r3, #2
8001ab2: 781b ldrb r3, [r3, #0]
8001ab4: 041b lsls r3, r3, #16
8001ab6: 431a orrs r2, r3
8001ab8: 687b ldr r3, [r7, #4]
8001aba: 3301 adds r3, #1
8001abc: 781b ldrb r3, [r3, #0]
8001abe: 021b lsls r3, r3, #8
8001ac0: 4313 orrs r3, r2
8001ac2: 687a ldr r2, [r7, #4]
8001ac4: 7812 ldrb r2, [r2, #0]
8001ac6: 4313 orrs r3, r2
8001ac8: 617b str r3, [r7, #20]
/* Load the selected MAC address low register */
(*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg1;
8001aca: 68ba ldr r2, [r7, #8]
8001acc: 4b06 ldr r3, [pc, #24] ; (8001ae8 <ETH_MACAddressConfig+0x6c>)
8001ace: 4413 add r3, r2
8001ad0: 461a mov r2, r3
8001ad2: 697b ldr r3, [r7, #20]
8001ad4: 6013 str r3, [r2, #0]
}
8001ad6: bf00 nop
8001ad8: 371c adds r7, #28
8001ada: 46bd mov sp, r7
8001adc: f85d 7b04 ldr.w r7, [sp], #4
8001ae0: 4770 bx lr
8001ae2: bf00 nop
8001ae4: 40028040 .word 0x40028040
8001ae8: 40028044 .word 0x40028044
08001aec <ETH_DMATxDescListInit>:
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth)
{
8001aec: b480 push {r7}
8001aee: b085 sub sp, #20
8001af0: af00 add r7, sp, #0
8001af2: 6078 str r0, [r7, #4]
ETH_DMADescTypeDef *dmatxdesc;
uint32_t i;
/* Fill each DMATxDesc descriptor with the right values */
for (i = 0; i < (uint32_t)ETH_TX_DESC_CNT; i++)
8001af4: 2300 movs r3, #0
8001af6: 60fb str r3, [r7, #12]
8001af8: e03e b.n 8001b78 <ETH_DMATxDescListInit+0x8c>
{
dmatxdesc = heth->Init.TxDesc + i;
8001afa: 687b ldr r3, [r7, #4]
8001afc: 68d9 ldr r1, [r3, #12]
8001afe: 68fa ldr r2, [r7, #12]
8001b00: 4613 mov r3, r2
8001b02: 009b lsls r3, r3, #2
8001b04: 4413 add r3, r2
8001b06: 00db lsls r3, r3, #3
8001b08: 440b add r3, r1
8001b0a: 60bb str r3, [r7, #8]
WRITE_REG(dmatxdesc->DESC0, 0x0U);
8001b0c: 68bb ldr r3, [r7, #8]
8001b0e: 2200 movs r2, #0
8001b10: 601a str r2, [r3, #0]
WRITE_REG(dmatxdesc->DESC1, 0x0U);
8001b12: 68bb ldr r3, [r7, #8]
8001b14: 2200 movs r2, #0
8001b16: 605a str r2, [r3, #4]
WRITE_REG(dmatxdesc->DESC2, 0x0U);
8001b18: 68bb ldr r3, [r7, #8]
8001b1a: 2200 movs r2, #0
8001b1c: 609a str r2, [r3, #8]
WRITE_REG(dmatxdesc->DESC3, 0x0U);
8001b1e: 68bb ldr r3, [r7, #8]
8001b20: 2200 movs r2, #0
8001b22: 60da str r2, [r3, #12]
WRITE_REG(heth->TxDescList.TxDesc[i], (uint32_t)dmatxdesc);
8001b24: 68b9 ldr r1, [r7, #8]
8001b26: 687b ldr r3, [r7, #4]
8001b28: 68fa ldr r2, [r7, #12]
8001b2a: 3206 adds r2, #6
8001b2c: f843 1022 str.w r1, [r3, r2, lsl #2]
/* Set Second Address Chained bit */
SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_TCH);
8001b30: 68bb ldr r3, [r7, #8]
8001b32: 681b ldr r3, [r3, #0]
8001b34: f443 1280 orr.w r2, r3, #1048576 ; 0x100000
8001b38: 68bb ldr r3, [r7, #8]
8001b3a: 601a str r2, [r3, #0]
if (i < ((uint32_t)ETH_TX_DESC_CNT - 1U))
8001b3c: 68fb ldr r3, [r7, #12]
8001b3e: 2b02 cmp r3, #2
8001b40: d80c bhi.n 8001b5c <ETH_DMATxDescListInit+0x70>
{
WRITE_REG(dmatxdesc->DESC3, (uint32_t)(heth->Init.TxDesc + i + 1U));
8001b42: 687b ldr r3, [r7, #4]
8001b44: 68d9 ldr r1, [r3, #12]
8001b46: 68fb ldr r3, [r7, #12]
8001b48: 1c5a adds r2, r3, #1
8001b4a: 4613 mov r3, r2
8001b4c: 009b lsls r3, r3, #2
8001b4e: 4413 add r3, r2
8001b50: 00db lsls r3, r3, #3
8001b52: 440b add r3, r1
8001b54: 461a mov r2, r3
8001b56: 68bb ldr r3, [r7, #8]
8001b58: 60da str r2, [r3, #12]
8001b5a: e004 b.n 8001b66 <ETH_DMATxDescListInit+0x7a>
}
else
{
WRITE_REG(dmatxdesc->DESC3, (uint32_t)(heth->Init.TxDesc));
8001b5c: 687b ldr r3, [r7, #4]
8001b5e: 68db ldr r3, [r3, #12]
8001b60: 461a mov r2, r3
8001b62: 68bb ldr r3, [r7, #8]
8001b64: 60da str r2, [r3, #12]
}
/* Set the DMA Tx descriptors checksum insertion */
SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL);
8001b66: 68bb ldr r3, [r7, #8]
8001b68: 681b ldr r3, [r3, #0]
8001b6a: f443 0240 orr.w r2, r3, #12582912 ; 0xc00000
8001b6e: 68bb ldr r3, [r7, #8]
8001b70: 601a str r2, [r3, #0]
for (i = 0; i < (uint32_t)ETH_TX_DESC_CNT; i++)
8001b72: 68fb ldr r3, [r7, #12]
8001b74: 3301 adds r3, #1
8001b76: 60fb str r3, [r7, #12]
8001b78: 68fb ldr r3, [r7, #12]
8001b7a: 2b03 cmp r3, #3
8001b7c: d9bd bls.n 8001afa <ETH_DMATxDescListInit+0xe>
}
heth->TxDescList.CurTxDesc = 0;
8001b7e: 687b ldr r3, [r7, #4]
8001b80: 2200 movs r2, #0
8001b82: 629a str r2, [r3, #40] ; 0x28
/* Set Transmit Descriptor List Address */
WRITE_REG(heth->Instance->DMATDLAR, (uint32_t) heth->Init.TxDesc);
8001b84: 687b ldr r3, [r7, #4]
8001b86: 68da ldr r2, [r3, #12]
8001b88: 687b ldr r3, [r7, #4]
8001b8a: 681b ldr r3, [r3, #0]
8001b8c: f503 5380 add.w r3, r3, #4096 ; 0x1000
8001b90: 611a str r2, [r3, #16]
}
8001b92: bf00 nop
8001b94: 3714 adds r7, #20
8001b96: 46bd mov sp, r7
8001b98: f85d 7b04 ldr.w r7, [sp], #4
8001b9c: 4770 bx lr
08001b9e <ETH_DMARxDescListInit>:
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth)
{
8001b9e: b480 push {r7}
8001ba0: b085 sub sp, #20
8001ba2: af00 add r7, sp, #0
8001ba4: 6078 str r0, [r7, #4]
ETH_DMADescTypeDef *dmarxdesc;
uint32_t i;
for (i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++)
8001ba6: 2300 movs r3, #0
8001ba8: 60fb str r3, [r7, #12]
8001baa: e048 b.n 8001c3e <ETH_DMARxDescListInit+0xa0>
{
dmarxdesc = heth->Init.RxDesc + i;
8001bac: 687b ldr r3, [r7, #4]
8001bae: 6919 ldr r1, [r3, #16]
8001bb0: 68fa ldr r2, [r7, #12]
8001bb2: 4613 mov r3, r2
8001bb4: 009b lsls r3, r3, #2
8001bb6: 4413 add r3, r2
8001bb8: 00db lsls r3, r3, #3
8001bba: 440b add r3, r1
8001bbc: 60bb str r3, [r7, #8]
WRITE_REG(dmarxdesc->DESC0, 0x0U);
8001bbe: 68bb ldr r3, [r7, #8]
8001bc0: 2200 movs r2, #0
8001bc2: 601a str r2, [r3, #0]
WRITE_REG(dmarxdesc->DESC1, 0x0U);
8001bc4: 68bb ldr r3, [r7, #8]
8001bc6: 2200 movs r2, #0
8001bc8: 605a str r2, [r3, #4]
WRITE_REG(dmarxdesc->DESC2, 0x0U);
8001bca: 68bb ldr r3, [r7, #8]
8001bcc: 2200 movs r2, #0
8001bce: 609a str r2, [r3, #8]
WRITE_REG(dmarxdesc->DESC3, 0x0U);
8001bd0: 68bb ldr r3, [r7, #8]
8001bd2: 2200 movs r2, #0
8001bd4: 60da str r2, [r3, #12]
WRITE_REG(dmarxdesc->BackupAddr0, 0x0U);
8001bd6: 68bb ldr r3, [r7, #8]
8001bd8: 2200 movs r2, #0
8001bda: 621a str r2, [r3, #32]
WRITE_REG(dmarxdesc->BackupAddr1, 0x0U);
8001bdc: 68bb ldr r3, [r7, #8]
8001bde: 2200 movs r2, #0
8001be0: 625a str r2, [r3, #36] ; 0x24
/* Set Own bit of the Rx descriptor Status */
dmarxdesc->DESC0 = ETH_DMARXDESC_OWN;
8001be2: 68bb ldr r3, [r7, #8]
8001be4: f04f 4200 mov.w r2, #2147483648 ; 0x80000000
8001be8: 601a str r2, [r3, #0]
/* Set Buffer1 size and Second Address Chained bit */
dmarxdesc->DESC1 = heth->Init.RxBuffLen | ETH_DMARXDESC_RCH;
8001bea: 687b ldr r3, [r7, #4]
8001bec: 695b ldr r3, [r3, #20]
8001bee: f443 4280 orr.w r2, r3, #16384 ; 0x4000
8001bf2: 68bb ldr r3, [r7, #8]
8001bf4: 605a str r2, [r3, #4]
/* Enable Ethernet DMA Rx Descriptor interrupt */
dmarxdesc->DESC1 &= ~ETH_DMARXDESC_DIC;
8001bf6: 68bb ldr r3, [r7, #8]
8001bf8: 685b ldr r3, [r3, #4]
8001bfa: f023 4200 bic.w r2, r3, #2147483648 ; 0x80000000
8001bfe: 68bb ldr r3, [r7, #8]
8001c00: 605a str r2, [r3, #4]
/* Set Rx descritors addresses */
WRITE_REG(heth->RxDescList.RxDesc[i], (uint32_t)dmarxdesc);
8001c02: 68b9 ldr r1, [r7, #8]
8001c04: 687b ldr r3, [r7, #4]
8001c06: 68fa ldr r2, [r7, #12]
8001c08: 3212 adds r2, #18
8001c0a: f843 1022 str.w r1, [r3, r2, lsl #2]
if (i < ((uint32_t)ETH_RX_DESC_CNT - 1U))
8001c0e: 68fb ldr r3, [r7, #12]
8001c10: 2b02 cmp r3, #2
8001c12: d80c bhi.n 8001c2e <ETH_DMARxDescListInit+0x90>
{
WRITE_REG(dmarxdesc->DESC3, (uint32_t)(heth->Init.RxDesc + i + 1U));
8001c14: 687b ldr r3, [r7, #4]
8001c16: 6919 ldr r1, [r3, #16]
8001c18: 68fb ldr r3, [r7, #12]
8001c1a: 1c5a adds r2, r3, #1
8001c1c: 4613 mov r3, r2
8001c1e: 009b lsls r3, r3, #2
8001c20: 4413 add r3, r2
8001c22: 00db lsls r3, r3, #3
8001c24: 440b add r3, r1
8001c26: 461a mov r2, r3
8001c28: 68bb ldr r3, [r7, #8]
8001c2a: 60da str r2, [r3, #12]
8001c2c: e004 b.n 8001c38 <ETH_DMARxDescListInit+0x9a>
}
else
{
WRITE_REG(dmarxdesc->DESC3, (uint32_t)(heth->Init.RxDesc));
8001c2e: 687b ldr r3, [r7, #4]
8001c30: 691b ldr r3, [r3, #16]
8001c32: 461a mov r2, r3
8001c34: 68bb ldr r3, [r7, #8]
8001c36: 60da str r2, [r3, #12]
for (i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++)
8001c38: 68fb ldr r3, [r7, #12]
8001c3a: 3301 adds r3, #1
8001c3c: 60fb str r3, [r7, #12]
8001c3e: 68fb ldr r3, [r7, #12]
8001c40: 2b03 cmp r3, #3
8001c42: d9b3 bls.n 8001bac <ETH_DMARxDescListInit+0xe>
}
}
WRITE_REG(heth->RxDescList.RxDescIdx, 0U);
8001c44: 687b ldr r3, [r7, #4]
8001c46: 2200 movs r2, #0
8001c48: 65da str r2, [r3, #92] ; 0x5c
WRITE_REG(heth->RxDescList.RxDescCnt, 0U);
8001c4a: 687b ldr r3, [r7, #4]
8001c4c: 2200 movs r2, #0
8001c4e: 661a str r2, [r3, #96] ; 0x60
WRITE_REG(heth->RxDescList.RxBuildDescIdx, 0U);
8001c50: 687b ldr r3, [r7, #4]
8001c52: 2200 movs r2, #0
8001c54: 669a str r2, [r3, #104] ; 0x68
WRITE_REG(heth->RxDescList.RxBuildDescCnt, 0U);
8001c56: 687b ldr r3, [r7, #4]
8001c58: 2200 movs r2, #0
8001c5a: 66da str r2, [r3, #108] ; 0x6c
WRITE_REG(heth->RxDescList.ItMode, 0U);
8001c5c: 687b ldr r3, [r7, #4]
8001c5e: 2200 movs r2, #0
8001c60: 659a str r2, [r3, #88] ; 0x58
/* Set Receive Descriptor List Address */
WRITE_REG(heth->Instance->DMARDLAR, (uint32_t) heth->Init.RxDesc);
8001c62: 687b ldr r3, [r7, #4]
8001c64: 691a ldr r2, [r3, #16]
8001c66: 687b ldr r3, [r7, #4]
8001c68: 681b ldr r3, [r3, #0]
8001c6a: f503 5380 add.w r3, r3, #4096 ; 0x1000
8001c6e: 60da str r2, [r3, #12]
}
8001c70: bf00 nop
8001c72: 3714 adds r7, #20
8001c74: 46bd mov sp, r7
8001c76: f85d 7b04 ldr.w r7, [sp], #4
8001c7a: 4770 bx lr
08001c7c <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8001c7c: b480 push {r7}
8001c7e: b089 sub sp, #36 ; 0x24
8001c80: af00 add r7, sp, #0
8001c82: 6078 str r0, [r7, #4]
8001c84: 6039 str r1, [r7, #0]
uint32_t position;
uint32_t ioposition = 0x00U;
8001c86: 2300 movs r3, #0
8001c88: 617b str r3, [r7, #20]
uint32_t iocurrent = 0x00U;
8001c8a: 2300 movs r3, #0
8001c8c: 613b str r3, [r7, #16]
uint32_t temp = 0x00U;
8001c8e: 2300 movs r3, #0
8001c90: 61bb str r3, [r7, #24]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
for(position = 0U; position < GPIO_NUMBER; position++)
8001c92: 2300 movs r3, #0
8001c94: 61fb str r3, [r7, #28]
8001c96: e177 b.n 8001f88 <HAL_GPIO_Init+0x30c>
{
/* Get the IO position */
ioposition = 0x01U << position;
8001c98: 2201 movs r2, #1
8001c9a: 69fb ldr r3, [r7, #28]
8001c9c: fa02 f303 lsl.w r3, r2, r3
8001ca0: 617b str r3, [r7, #20]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
8001ca2: 683b ldr r3, [r7, #0]
8001ca4: 681b ldr r3, [r3, #0]
8001ca6: 697a ldr r2, [r7, #20]
8001ca8: 4013 ands r3, r2
8001caa: 613b str r3, [r7, #16]
if(iocurrent == ioposition)
8001cac: 693a ldr r2, [r7, #16]
8001cae: 697b ldr r3, [r7, #20]
8001cb0: 429a cmp r2, r3
8001cb2: f040 8166 bne.w 8001f82 <HAL_GPIO_Init+0x306>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
8001cb6: 683b ldr r3, [r7, #0]
8001cb8: 685b ldr r3, [r3, #4]
8001cba: f003 0303 and.w r3, r3, #3
8001cbe: 2b01 cmp r3, #1
8001cc0: d005 beq.n 8001cce <HAL_GPIO_Init+0x52>
(GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8001cc2: 683b ldr r3, [r7, #0]
8001cc4: 685b ldr r3, [r3, #4]
8001cc6: f003 0303 and.w r3, r3, #3
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
8001cca: 2b02 cmp r3, #2
8001ccc: d130 bne.n 8001d30 <HAL_GPIO_Init+0xb4>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8001cce: 687b ldr r3, [r7, #4]
8001cd0: 689b ldr r3, [r3, #8]
8001cd2: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
8001cd4: 69fb ldr r3, [r7, #28]
8001cd6: 005b lsls r3, r3, #1
8001cd8: 2203 movs r2, #3
8001cda: fa02 f303 lsl.w r3, r2, r3
8001cde: 43db mvns r3, r3
8001ce0: 69ba ldr r2, [r7, #24]
8001ce2: 4013 ands r3, r2
8001ce4: 61bb str r3, [r7, #24]
temp |= (GPIO_Init->Speed << (position * 2U));
8001ce6: 683b ldr r3, [r7, #0]
8001ce8: 68da ldr r2, [r3, #12]
8001cea: 69fb ldr r3, [r7, #28]
8001cec: 005b lsls r3, r3, #1
8001cee: fa02 f303 lsl.w r3, r2, r3
8001cf2: 69ba ldr r2, [r7, #24]
8001cf4: 4313 orrs r3, r2
8001cf6: 61bb str r3, [r7, #24]
GPIOx->OSPEEDR = temp;
8001cf8: 687b ldr r3, [r7, #4]
8001cfa: 69ba ldr r2, [r7, #24]
8001cfc: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8001cfe: 687b ldr r3, [r7, #4]
8001d00: 685b ldr r3, [r3, #4]
8001d02: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
8001d04: 2201 movs r2, #1
8001d06: 69fb ldr r3, [r7, #28]
8001d08: fa02 f303 lsl.w r3, r2, r3
8001d0c: 43db mvns r3, r3
8001d0e: 69ba ldr r2, [r7, #24]
8001d10: 4013 ands r3, r2
8001d12: 61bb str r3, [r7, #24]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
8001d14: 683b ldr r3, [r7, #0]
8001d16: 685b ldr r3, [r3, #4]
8001d18: 091b lsrs r3, r3, #4
8001d1a: f003 0201 and.w r2, r3, #1
8001d1e: 69fb ldr r3, [r7, #28]
8001d20: fa02 f303 lsl.w r3, r2, r3
8001d24: 69ba ldr r2, [r7, #24]
8001d26: 4313 orrs r3, r2
8001d28: 61bb str r3, [r7, #24]
GPIOx->OTYPER = temp;
8001d2a: 687b ldr r3, [r7, #4]
8001d2c: 69ba ldr r2, [r7, #24]
8001d2e: 605a str r2, [r3, #4]
}
if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
8001d30: 683b ldr r3, [r7, #0]
8001d32: 685b ldr r3, [r3, #4]
8001d34: f003 0303 and.w r3, r3, #3
8001d38: 2b03 cmp r3, #3
8001d3a: d017 beq.n 8001d6c <HAL_GPIO_Init+0xf0>
{
/* Check the parameters */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
8001d3c: 687b ldr r3, [r7, #4]
8001d3e: 68db ldr r3, [r3, #12]
8001d40: 61bb str r3, [r7, #24]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
8001d42: 69fb ldr r3, [r7, #28]
8001d44: 005b lsls r3, r3, #1
8001d46: 2203 movs r2, #3
8001d48: fa02 f303 lsl.w r3, r2, r3
8001d4c: 43db mvns r3, r3
8001d4e: 69ba ldr r2, [r7, #24]
8001d50: 4013 ands r3, r2
8001d52: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Pull) << (position * 2U));
8001d54: 683b ldr r3, [r7, #0]
8001d56: 689a ldr r2, [r3, #8]
8001d58: 69fb ldr r3, [r7, #28]
8001d5a: 005b lsls r3, r3, #1
8001d5c: fa02 f303 lsl.w r3, r2, r3
8001d60: 69ba ldr r2, [r7, #24]
8001d62: 4313 orrs r3, r2
8001d64: 61bb str r3, [r7, #24]
GPIOx->PUPDR = temp;
8001d66: 687b ldr r3, [r7, #4]
8001d68: 69ba ldr r2, [r7, #24]
8001d6a: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8001d6c: 683b ldr r3, [r7, #0]
8001d6e: 685b ldr r3, [r3, #4]
8001d70: f003 0303 and.w r3, r3, #3
8001d74: 2b02 cmp r3, #2
8001d76: d123 bne.n 8001dc0 <HAL_GPIO_Init+0x144>
{
/* Check the Alternate function parameter */
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3U];
8001d78: 69fb ldr r3, [r7, #28]
8001d7a: 08da lsrs r2, r3, #3
8001d7c: 687b ldr r3, [r7, #4]
8001d7e: 3208 adds r2, #8
8001d80: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8001d84: 61bb str r3, [r7, #24]
temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
8001d86: 69fb ldr r3, [r7, #28]
8001d88: f003 0307 and.w r3, r3, #7
8001d8c: 009b lsls r3, r3, #2
8001d8e: 220f movs r2, #15
8001d90: fa02 f303 lsl.w r3, r2, r3
8001d94: 43db mvns r3, r3
8001d96: 69ba ldr r2, [r7, #24]
8001d98: 4013 ands r3, r2
8001d9a: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
8001d9c: 683b ldr r3, [r7, #0]
8001d9e: 691a ldr r2, [r3, #16]
8001da0: 69fb ldr r3, [r7, #28]
8001da2: f003 0307 and.w r3, r3, #7
8001da6: 009b lsls r3, r3, #2
8001da8: fa02 f303 lsl.w r3, r2, r3
8001dac: 69ba ldr r2, [r7, #24]
8001dae: 4313 orrs r3, r2
8001db0: 61bb str r3, [r7, #24]
GPIOx->AFR[position >> 3U] = temp;
8001db2: 69fb ldr r3, [r7, #28]
8001db4: 08da lsrs r2, r3, #3
8001db6: 687b ldr r3, [r7, #4]
8001db8: 3208 adds r2, #8
8001dba: 69b9 ldr r1, [r7, #24]
8001dbc: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8001dc0: 687b ldr r3, [r7, #4]
8001dc2: 681b ldr r3, [r3, #0]
8001dc4: 61bb str r3, [r7, #24]
temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
8001dc6: 69fb ldr r3, [r7, #28]
8001dc8: 005b lsls r3, r3, #1
8001dca: 2203 movs r2, #3
8001dcc: fa02 f303 lsl.w r3, r2, r3
8001dd0: 43db mvns r3, r3
8001dd2: 69ba ldr r2, [r7, #24]
8001dd4: 4013 ands r3, r2
8001dd6: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
8001dd8: 683b ldr r3, [r7, #0]
8001dda: 685b ldr r3, [r3, #4]
8001ddc: f003 0203 and.w r2, r3, #3
8001de0: 69fb ldr r3, [r7, #28]
8001de2: 005b lsls r3, r3, #1
8001de4: fa02 f303 lsl.w r3, r2, r3
8001de8: 69ba ldr r2, [r7, #24]
8001dea: 4313 orrs r3, r2
8001dec: 61bb str r3, [r7, #24]
GPIOx->MODER = temp;
8001dee: 687b ldr r3, [r7, #4]
8001df0: 69ba ldr r2, [r7, #24]
8001df2: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
8001df4: 683b ldr r3, [r7, #0]
8001df6: 685b ldr r3, [r3, #4]
8001df8: f403 3340 and.w r3, r3, #196608 ; 0x30000
8001dfc: 2b00 cmp r3, #0
8001dfe: f000 80c0 beq.w 8001f82 <HAL_GPIO_Init+0x306>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8001e02: 2300 movs r3, #0
8001e04: 60fb str r3, [r7, #12]
8001e06: 4b66 ldr r3, [pc, #408] ; (8001fa0 <HAL_GPIO_Init+0x324>)
8001e08: 6c5b ldr r3, [r3, #68] ; 0x44
8001e0a: 4a65 ldr r2, [pc, #404] ; (8001fa0 <HAL_GPIO_Init+0x324>)
8001e0c: f443 4380 orr.w r3, r3, #16384 ; 0x4000
8001e10: 6453 str r3, [r2, #68] ; 0x44
8001e12: 4b63 ldr r3, [pc, #396] ; (8001fa0 <HAL_GPIO_Init+0x324>)
8001e14: 6c5b ldr r3, [r3, #68] ; 0x44
8001e16: f403 4380 and.w r3, r3, #16384 ; 0x4000
8001e1a: 60fb str r3, [r7, #12]
8001e1c: 68fb ldr r3, [r7, #12]
temp = SYSCFG->EXTICR[position >> 2U];
8001e1e: 4a61 ldr r2, [pc, #388] ; (8001fa4 <HAL_GPIO_Init+0x328>)
8001e20: 69fb ldr r3, [r7, #28]
8001e22: 089b lsrs r3, r3, #2
8001e24: 3302 adds r3, #2
8001e26: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8001e2a: 61bb str r3, [r7, #24]
temp &= ~(0x0FU << (4U * (position & 0x03U)));
8001e2c: 69fb ldr r3, [r7, #28]
8001e2e: f003 0303 and.w r3, r3, #3
8001e32: 009b lsls r3, r3, #2
8001e34: 220f movs r2, #15
8001e36: fa02 f303 lsl.w r3, r2, r3
8001e3a: 43db mvns r3, r3
8001e3c: 69ba ldr r2, [r7, #24]
8001e3e: 4013 ands r3, r2
8001e40: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
8001e42: 687b ldr r3, [r7, #4]
8001e44: 4a58 ldr r2, [pc, #352] ; (8001fa8 <HAL_GPIO_Init+0x32c>)
8001e46: 4293 cmp r3, r2
8001e48: d037 beq.n 8001eba <HAL_GPIO_Init+0x23e>
8001e4a: 687b ldr r3, [r7, #4]
8001e4c: 4a57 ldr r2, [pc, #348] ; (8001fac <HAL_GPIO_Init+0x330>)
8001e4e: 4293 cmp r3, r2
8001e50: d031 beq.n 8001eb6 <HAL_GPIO_Init+0x23a>
8001e52: 687b ldr r3, [r7, #4]
8001e54: 4a56 ldr r2, [pc, #344] ; (8001fb0 <HAL_GPIO_Init+0x334>)
8001e56: 4293 cmp r3, r2
8001e58: d02b beq.n 8001eb2 <HAL_GPIO_Init+0x236>
8001e5a: 687b ldr r3, [r7, #4]
8001e5c: 4a55 ldr r2, [pc, #340] ; (8001fb4 <HAL_GPIO_Init+0x338>)
8001e5e: 4293 cmp r3, r2
8001e60: d025 beq.n 8001eae <HAL_GPIO_Init+0x232>
8001e62: 687b ldr r3, [r7, #4]
8001e64: 4a54 ldr r2, [pc, #336] ; (8001fb8 <HAL_GPIO_Init+0x33c>)
8001e66: 4293 cmp r3, r2
8001e68: d01f beq.n 8001eaa <HAL_GPIO_Init+0x22e>
8001e6a: 687b ldr r3, [r7, #4]
8001e6c: 4a53 ldr r2, [pc, #332] ; (8001fbc <HAL_GPIO_Init+0x340>)
8001e6e: 4293 cmp r3, r2
8001e70: d019 beq.n 8001ea6 <HAL_GPIO_Init+0x22a>
8001e72: 687b ldr r3, [r7, #4]
8001e74: 4a52 ldr r2, [pc, #328] ; (8001fc0 <HAL_GPIO_Init+0x344>)
8001e76: 4293 cmp r3, r2
8001e78: d013 beq.n 8001ea2 <HAL_GPIO_Init+0x226>
8001e7a: 687b ldr r3, [r7, #4]
8001e7c: 4a51 ldr r2, [pc, #324] ; (8001fc4 <HAL_GPIO_Init+0x348>)
8001e7e: 4293 cmp r3, r2
8001e80: d00d beq.n 8001e9e <HAL_GPIO_Init+0x222>
8001e82: 687b ldr r3, [r7, #4]
8001e84: 4a50 ldr r2, [pc, #320] ; (8001fc8 <HAL_GPIO_Init+0x34c>)
8001e86: 4293 cmp r3, r2
8001e88: d007 beq.n 8001e9a <HAL_GPIO_Init+0x21e>
8001e8a: 687b ldr r3, [r7, #4]
8001e8c: 4a4f ldr r2, [pc, #316] ; (8001fcc <HAL_GPIO_Init+0x350>)
8001e8e: 4293 cmp r3, r2
8001e90: d101 bne.n 8001e96 <HAL_GPIO_Init+0x21a>
8001e92: 2309 movs r3, #9
8001e94: e012 b.n 8001ebc <HAL_GPIO_Init+0x240>
8001e96: 230a movs r3, #10
8001e98: e010 b.n 8001ebc <HAL_GPIO_Init+0x240>
8001e9a: 2308 movs r3, #8
8001e9c: e00e b.n 8001ebc <HAL_GPIO_Init+0x240>
8001e9e: 2307 movs r3, #7
8001ea0: e00c b.n 8001ebc <HAL_GPIO_Init+0x240>
8001ea2: 2306 movs r3, #6
8001ea4: e00a b.n 8001ebc <HAL_GPIO_Init+0x240>
8001ea6: 2305 movs r3, #5
8001ea8: e008 b.n 8001ebc <HAL_GPIO_Init+0x240>
8001eaa: 2304 movs r3, #4
8001eac: e006 b.n 8001ebc <HAL_GPIO_Init+0x240>
8001eae: 2303 movs r3, #3
8001eb0: e004 b.n 8001ebc <HAL_GPIO_Init+0x240>
8001eb2: 2302 movs r3, #2
8001eb4: e002 b.n 8001ebc <HAL_GPIO_Init+0x240>
8001eb6: 2301 movs r3, #1
8001eb8: e000 b.n 8001ebc <HAL_GPIO_Init+0x240>
8001eba: 2300 movs r3, #0
8001ebc: 69fa ldr r2, [r7, #28]
8001ebe: f002 0203 and.w r2, r2, #3
8001ec2: 0092 lsls r2, r2, #2
8001ec4: 4093 lsls r3, r2
8001ec6: 69ba ldr r2, [r7, #24]
8001ec8: 4313 orrs r3, r2
8001eca: 61bb str r3, [r7, #24]
SYSCFG->EXTICR[position >> 2U] = temp;
8001ecc: 4935 ldr r1, [pc, #212] ; (8001fa4 <HAL_GPIO_Init+0x328>)
8001ece: 69fb ldr r3, [r7, #28]
8001ed0: 089b lsrs r3, r3, #2
8001ed2: 3302 adds r3, #2
8001ed4: 69ba ldr r2, [r7, #24]
8001ed6: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
8001eda: 4b3d ldr r3, [pc, #244] ; (8001fd0 <HAL_GPIO_Init+0x354>)
8001edc: 689b ldr r3, [r3, #8]
8001ede: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8001ee0: 693b ldr r3, [r7, #16]
8001ee2: 43db mvns r3, r3
8001ee4: 69ba ldr r2, [r7, #24]
8001ee6: 4013 ands r3, r2
8001ee8: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
8001eea: 683b ldr r3, [r7, #0]
8001eec: 685b ldr r3, [r3, #4]
8001eee: f403 1380 and.w r3, r3, #1048576 ; 0x100000
8001ef2: 2b00 cmp r3, #0
8001ef4: d003 beq.n 8001efe <HAL_GPIO_Init+0x282>
{
temp |= iocurrent;
8001ef6: 69ba ldr r2, [r7, #24]
8001ef8: 693b ldr r3, [r7, #16]
8001efa: 4313 orrs r3, r2
8001efc: 61bb str r3, [r7, #24]
}
EXTI->RTSR = temp;
8001efe: 4a34 ldr r2, [pc, #208] ; (8001fd0 <HAL_GPIO_Init+0x354>)
8001f00: 69bb ldr r3, [r7, #24]
8001f02: 6093 str r3, [r2, #8]
temp = EXTI->FTSR;
8001f04: 4b32 ldr r3, [pc, #200] ; (8001fd0 <HAL_GPIO_Init+0x354>)
8001f06: 68db ldr r3, [r3, #12]
8001f08: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8001f0a: 693b ldr r3, [r7, #16]
8001f0c: 43db mvns r3, r3
8001f0e: 69ba ldr r2, [r7, #24]
8001f10: 4013 ands r3, r2
8001f12: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
8001f14: 683b ldr r3, [r7, #0]
8001f16: 685b ldr r3, [r3, #4]
8001f18: f403 1300 and.w r3, r3, #2097152 ; 0x200000
8001f1c: 2b00 cmp r3, #0
8001f1e: d003 beq.n 8001f28 <HAL_GPIO_Init+0x2ac>
{
temp |= iocurrent;
8001f20: 69ba ldr r2, [r7, #24]
8001f22: 693b ldr r3, [r7, #16]
8001f24: 4313 orrs r3, r2
8001f26: 61bb str r3, [r7, #24]
}
EXTI->FTSR = temp;
8001f28: 4a29 ldr r2, [pc, #164] ; (8001fd0 <HAL_GPIO_Init+0x354>)
8001f2a: 69bb ldr r3, [r7, #24]
8001f2c: 60d3 str r3, [r2, #12]
temp = EXTI->EMR;
8001f2e: 4b28 ldr r3, [pc, #160] ; (8001fd0 <HAL_GPIO_Init+0x354>)
8001f30: 685b ldr r3, [r3, #4]
8001f32: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8001f34: 693b ldr r3, [r7, #16]
8001f36: 43db mvns r3, r3
8001f38: 69ba ldr r2, [r7, #24]
8001f3a: 4013 ands r3, r2
8001f3c: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
8001f3e: 683b ldr r3, [r7, #0]
8001f40: 685b ldr r3, [r3, #4]
8001f42: f403 3300 and.w r3, r3, #131072 ; 0x20000
8001f46: 2b00 cmp r3, #0
8001f48: d003 beq.n 8001f52 <HAL_GPIO_Init+0x2d6>
{
temp |= iocurrent;
8001f4a: 69ba ldr r2, [r7, #24]
8001f4c: 693b ldr r3, [r7, #16]
8001f4e: 4313 orrs r3, r2
8001f50: 61bb str r3, [r7, #24]
}
EXTI->EMR = temp;
8001f52: 4a1f ldr r2, [pc, #124] ; (8001fd0 <HAL_GPIO_Init+0x354>)
8001f54: 69bb ldr r3, [r7, #24]
8001f56: 6053 str r3, [r2, #4]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
8001f58: 4b1d ldr r3, [pc, #116] ; (8001fd0 <HAL_GPIO_Init+0x354>)
8001f5a: 681b ldr r3, [r3, #0]
8001f5c: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8001f5e: 693b ldr r3, [r7, #16]
8001f60: 43db mvns r3, r3
8001f62: 69ba ldr r2, [r7, #24]
8001f64: 4013 ands r3, r2
8001f66: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & EXTI_IT) != 0x00U)
8001f68: 683b ldr r3, [r7, #0]
8001f6a: 685b ldr r3, [r3, #4]
8001f6c: f403 3380 and.w r3, r3, #65536 ; 0x10000
8001f70: 2b00 cmp r3, #0
8001f72: d003 beq.n 8001f7c <HAL_GPIO_Init+0x300>
{
temp |= iocurrent;
8001f74: 69ba ldr r2, [r7, #24]
8001f76: 693b ldr r3, [r7, #16]
8001f78: 4313 orrs r3, r2
8001f7a: 61bb str r3, [r7, #24]
}
EXTI->IMR = temp;
8001f7c: 4a14 ldr r2, [pc, #80] ; (8001fd0 <HAL_GPIO_Init+0x354>)
8001f7e: 69bb ldr r3, [r7, #24]
8001f80: 6013 str r3, [r2, #0]
for(position = 0U; position < GPIO_NUMBER; position++)
8001f82: 69fb ldr r3, [r7, #28]
8001f84: 3301 adds r3, #1
8001f86: 61fb str r3, [r7, #28]
8001f88: 69fb ldr r3, [r7, #28]
8001f8a: 2b0f cmp r3, #15
8001f8c: f67f ae84 bls.w 8001c98 <HAL_GPIO_Init+0x1c>
}
}
}
}
8001f90: bf00 nop
8001f92: bf00 nop
8001f94: 3724 adds r7, #36 ; 0x24
8001f96: 46bd mov sp, r7
8001f98: f85d 7b04 ldr.w r7, [sp], #4
8001f9c: 4770 bx lr
8001f9e: bf00 nop
8001fa0: 40023800 .word 0x40023800
8001fa4: 40013800 .word 0x40013800
8001fa8: 40020000 .word 0x40020000
8001fac: 40020400 .word 0x40020400
8001fb0: 40020800 .word 0x40020800
8001fb4: 40020c00 .word 0x40020c00
8001fb8: 40021000 .word 0x40021000
8001fbc: 40021400 .word 0x40021400
8001fc0: 40021800 .word 0x40021800
8001fc4: 40021c00 .word 0x40021c00
8001fc8: 40022000 .word 0x40022000
8001fcc: 40022400 .word 0x40022400
8001fd0: 40013c00 .word 0x40013c00
08001fd4 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8001fd4: b480 push {r7}
8001fd6: b083 sub sp, #12
8001fd8: af00 add r7, sp, #0
8001fda: 6078 str r0, [r7, #4]
8001fdc: 460b mov r3, r1
8001fde: 807b strh r3, [r7, #2]
8001fe0: 4613 mov r3, r2
8001fe2: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if(PinState != GPIO_PIN_RESET)
8001fe4: 787b ldrb r3, [r7, #1]
8001fe6: 2b00 cmp r3, #0
8001fe8: d003 beq.n 8001ff2 <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = GPIO_Pin;
8001fea: 887a ldrh r2, [r7, #2]
8001fec: 687b ldr r3, [r7, #4]
8001fee: 619a str r2, [r3, #24]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
}
}
8001ff0: e003 b.n 8001ffa <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
8001ff2: 887b ldrh r3, [r7, #2]
8001ff4: 041a lsls r2, r3, #16
8001ff6: 687b ldr r3, [r7, #4]
8001ff8: 619a str r2, [r3, #24]
}
8001ffa: bf00 nop
8001ffc: 370c adds r7, #12
8001ffe: 46bd mov sp, r7
8002000: f85d 7b04 ldr.w r7, [sp], #4
8002004: 4770 bx lr
08002006 <HAL_GPIO_TogglePin>:
* x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
* @param GPIO_Pin Specifies the pins to be toggled.
* @retval None
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
8002006: b480 push {r7}
8002008: b085 sub sp, #20
800200a: af00 add r7, sp, #0
800200c: 6078 str r0, [r7, #4]
800200e: 460b mov r3, r1
8002010: 807b strh r3, [r7, #2]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* get current Output Data Register value */
odr = GPIOx->ODR;
8002012: 687b ldr r3, [r7, #4]
8002014: 695b ldr r3, [r3, #20]
8002016: 60fb str r3, [r7, #12]
/* Set selected pins that were at low level, and reset ones that were high */
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
8002018: 887a ldrh r2, [r7, #2]
800201a: 68fb ldr r3, [r7, #12]
800201c: 4013 ands r3, r2
800201e: 041a lsls r2, r3, #16
8002020: 68fb ldr r3, [r7, #12]
8002022: 43d9 mvns r1, r3
8002024: 887b ldrh r3, [r7, #2]
8002026: 400b ands r3, r1
8002028: 431a orrs r2, r3
800202a: 687b ldr r3, [r7, #4]
800202c: 619a str r2, [r3, #24]
}
800202e: bf00 nop
8002030: 3714 adds r7, #20
8002032: 46bd mov sp, r7
8002034: f85d 7b04 ldr.w r7, [sp], #4
8002038: 4770 bx lr
0800203a <HAL_PCD_Init>:
* parameters in the PCD_InitTypeDef and initialize the associated handle.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
{
800203a: b580 push {r7, lr}
800203c: b086 sub sp, #24
800203e: af02 add r7, sp, #8
8002040: 6078 str r0, [r7, #4]
const USB_OTG_GlobalTypeDef *USBx;
#endif /* defined (USB_OTG_FS) */
uint8_t i;
/* Check the PCD handle allocation */
if (hpcd == NULL)
8002042: 687b ldr r3, [r7, #4]
8002044: 2b00 cmp r3, #0
8002046: d101 bne.n 800204c <HAL_PCD_Init+0x12>
{
return HAL_ERROR;
8002048: 2301 movs r3, #1
800204a: e101 b.n 8002250 <HAL_PCD_Init+0x216>
/* Check the parameters */
assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
#if defined (USB_OTG_FS)
USBx = hpcd->Instance;
800204c: 687b ldr r3, [r7, #4]
800204e: 681b ldr r3, [r3, #0]
8002050: 60bb str r3, [r7, #8]
#endif /* defined (USB_OTG_FS) */
if (hpcd->State == HAL_PCD_STATE_RESET)
8002052: 687b ldr r3, [r7, #4]
8002054: f893 3495 ldrb.w r3, [r3, #1173] ; 0x495
8002058: b2db uxtb r3, r3
800205a: 2b00 cmp r3, #0
800205c: d106 bne.n 800206c <HAL_PCD_Init+0x32>
{
/* Allocate lock resource and initialize it */
hpcd->Lock = HAL_UNLOCKED;
800205e: 687b ldr r3, [r7, #4]
8002060: 2200 movs r2, #0
8002062: f883 2494 strb.w r2, [r3, #1172] ; 0x494
/* Init the low level hardware */
hpcd->MspInitCallback(hpcd);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_PCD_MspInit(hpcd);
8002066: 6878 ldr r0, [r7, #4]
8002068: f7ff f87c bl 8001164 <HAL_PCD_MspInit>
#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
}
hpcd->State = HAL_PCD_STATE_BUSY;
800206c: 687b ldr r3, [r7, #4]
800206e: 2203 movs r2, #3
8002070: f883 2495 strb.w r2, [r3, #1173] ; 0x495
#if defined (USB_OTG_FS)
/* Disable DMA mode for FS instance */
if (USBx == USB_OTG_FS)
8002074: 68bb ldr r3, [r7, #8]
8002076: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000
800207a: d102 bne.n 8002082 <HAL_PCD_Init+0x48>
{
hpcd->Init.dma_enable = 0U;
800207c: 687b ldr r3, [r7, #4]
800207e: 2200 movs r2, #0
8002080: 719a strb r2, [r3, #6]
}
#endif /* defined (USB_OTG_FS) */
/* Disable the Interrupts */
__HAL_PCD_DISABLE(hpcd);
8002082: 687b ldr r3, [r7, #4]
8002084: 681b ldr r3, [r3, #0]
8002086: 4618 mov r0, r3
8002088: f001 faae bl 80035e8 <USB_DisableGlobalInt>
/*Init the Core (common init.) */
if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK)
800208c: 687b ldr r3, [r7, #4]
800208e: 6818 ldr r0, [r3, #0]
8002090: 687b ldr r3, [r7, #4]
8002092: 7c1a ldrb r2, [r3, #16]
8002094: f88d 2000 strb.w r2, [sp]
8002098: 3304 adds r3, #4
800209a: cb0e ldmia r3, {r1, r2, r3}
800209c: f001 fa40 bl 8003520 <USB_CoreInit>
80020a0: 4603 mov r3, r0
80020a2: 2b00 cmp r3, #0
80020a4: d005 beq.n 80020b2 <HAL_PCD_Init+0x78>
{
hpcd->State = HAL_PCD_STATE_ERROR;
80020a6: 687b ldr r3, [r7, #4]
80020a8: 2202 movs r2, #2
80020aa: f883 2495 strb.w r2, [r3, #1173] ; 0x495
return HAL_ERROR;
80020ae: 2301 movs r3, #1
80020b0: e0ce b.n 8002250 <HAL_PCD_Init+0x216>
}
/* Force Device Mode */
if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK)
80020b2: 687b ldr r3, [r7, #4]
80020b4: 681b ldr r3, [r3, #0]
80020b6: 2100 movs r1, #0
80020b8: 4618 mov r0, r3
80020ba: f001 faa6 bl 800360a <USB_SetCurrentMode>
80020be: 4603 mov r3, r0
80020c0: 2b00 cmp r3, #0
80020c2: d005 beq.n 80020d0 <HAL_PCD_Init+0x96>
{
hpcd->State = HAL_PCD_STATE_ERROR;
80020c4: 687b ldr r3, [r7, #4]
80020c6: 2202 movs r2, #2
80020c8: f883 2495 strb.w r2, [r3, #1173] ; 0x495
return HAL_ERROR;
80020cc: 2301 movs r3, #1
80020ce: e0bf b.n 8002250 <HAL_PCD_Init+0x216>
}
/* Init endpoints structures */
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
80020d0: 2300 movs r3, #0
80020d2: 73fb strb r3, [r7, #15]
80020d4: e04a b.n 800216c <HAL_PCD_Init+0x132>
{
/* Init ep structure */
hpcd->IN_ep[i].is_in = 1U;
80020d6: 7bfa ldrb r2, [r7, #15]
80020d8: 6879 ldr r1, [r7, #4]
80020da: 4613 mov r3, r2
80020dc: 00db lsls r3, r3, #3
80020de: 4413 add r3, r2
80020e0: 009b lsls r3, r3, #2
80020e2: 440b add r3, r1
80020e4: 3315 adds r3, #21
80020e6: 2201 movs r2, #1
80020e8: 701a strb r2, [r3, #0]
hpcd->IN_ep[i].num = i;
80020ea: 7bfa ldrb r2, [r7, #15]
80020ec: 6879 ldr r1, [r7, #4]
80020ee: 4613 mov r3, r2
80020f0: 00db lsls r3, r3, #3
80020f2: 4413 add r3, r2
80020f4: 009b lsls r3, r3, #2
80020f6: 440b add r3, r1
80020f8: 3314 adds r3, #20
80020fa: 7bfa ldrb r2, [r7, #15]
80020fc: 701a strb r2, [r3, #0]
hpcd->IN_ep[i].tx_fifo_num = i;
80020fe: 7bfa ldrb r2, [r7, #15]
8002100: 7bfb ldrb r3, [r7, #15]
8002102: b298 uxth r0, r3
8002104: 6879 ldr r1, [r7, #4]
8002106: 4613 mov r3, r2
8002108: 00db lsls r3, r3, #3
800210a: 4413 add r3, r2
800210c: 009b lsls r3, r3, #2
800210e: 440b add r3, r1
8002110: 332e adds r3, #46 ; 0x2e
8002112: 4602 mov r2, r0
8002114: 801a strh r2, [r3, #0]
/* Control until ep is activated */
hpcd->IN_ep[i].type = EP_TYPE_CTRL;
8002116: 7bfa ldrb r2, [r7, #15]
8002118: 6879 ldr r1, [r7, #4]
800211a: 4613 mov r3, r2
800211c: 00db lsls r3, r3, #3
800211e: 4413 add r3, r2
8002120: 009b lsls r3, r3, #2
8002122: 440b add r3, r1
8002124: 3318 adds r3, #24
8002126: 2200 movs r2, #0
8002128: 701a strb r2, [r3, #0]
hpcd->IN_ep[i].maxpacket = 0U;
800212a: 7bfa ldrb r2, [r7, #15]
800212c: 6879 ldr r1, [r7, #4]
800212e: 4613 mov r3, r2
8002130: 00db lsls r3, r3, #3
8002132: 4413 add r3, r2
8002134: 009b lsls r3, r3, #2
8002136: 440b add r3, r1
8002138: 331c adds r3, #28
800213a: 2200 movs r2, #0
800213c: 601a str r2, [r3, #0]
hpcd->IN_ep[i].xfer_buff = 0U;
800213e: 7bfa ldrb r2, [r7, #15]
8002140: 6879 ldr r1, [r7, #4]
8002142: 4613 mov r3, r2
8002144: 00db lsls r3, r3, #3
8002146: 4413 add r3, r2
8002148: 009b lsls r3, r3, #2
800214a: 440b add r3, r1
800214c: 3320 adds r3, #32
800214e: 2200 movs r2, #0
8002150: 601a str r2, [r3, #0]
hpcd->IN_ep[i].xfer_len = 0U;
8002152: 7bfa ldrb r2, [r7, #15]
8002154: 6879 ldr r1, [r7, #4]
8002156: 4613 mov r3, r2
8002158: 00db lsls r3, r3, #3
800215a: 4413 add r3, r2
800215c: 009b lsls r3, r3, #2
800215e: 440b add r3, r1
8002160: 3324 adds r3, #36 ; 0x24
8002162: 2200 movs r2, #0
8002164: 601a str r2, [r3, #0]
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
8002166: 7bfb ldrb r3, [r7, #15]
8002168: 3301 adds r3, #1
800216a: 73fb strb r3, [r7, #15]
800216c: 687b ldr r3, [r7, #4]
800216e: 791b ldrb r3, [r3, #4]
8002170: 7bfa ldrb r2, [r7, #15]
8002172: 429a cmp r2, r3
8002174: d3af bcc.n 80020d6 <HAL_PCD_Init+0x9c>
}
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
8002176: 2300 movs r3, #0
8002178: 73fb strb r3, [r7, #15]
800217a: e044 b.n 8002206 <HAL_PCD_Init+0x1cc>
{
hpcd->OUT_ep[i].is_in = 0U;
800217c: 7bfa ldrb r2, [r7, #15]
800217e: 6879 ldr r1, [r7, #4]
8002180: 4613 mov r3, r2
8002182: 00db lsls r3, r3, #3
8002184: 4413 add r3, r2
8002186: 009b lsls r3, r3, #2
8002188: 440b add r3, r1
800218a: f203 2355 addw r3, r3, #597 ; 0x255
800218e: 2200 movs r2, #0
8002190: 701a strb r2, [r3, #0]
hpcd->OUT_ep[i].num = i;
8002192: 7bfa ldrb r2, [r7, #15]
8002194: 6879 ldr r1, [r7, #4]
8002196: 4613 mov r3, r2
8002198: 00db lsls r3, r3, #3
800219a: 4413 add r3, r2
800219c: 009b lsls r3, r3, #2
800219e: 440b add r3, r1
80021a0: f503 7315 add.w r3, r3, #596 ; 0x254
80021a4: 7bfa ldrb r2, [r7, #15]
80021a6: 701a strb r2, [r3, #0]
/* Control until ep is activated */
hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
80021a8: 7bfa ldrb r2, [r7, #15]
80021aa: 6879 ldr r1, [r7, #4]
80021ac: 4613 mov r3, r2
80021ae: 00db lsls r3, r3, #3
80021b0: 4413 add r3, r2
80021b2: 009b lsls r3, r3, #2
80021b4: 440b add r3, r1
80021b6: f503 7316 add.w r3, r3, #600 ; 0x258
80021ba: 2200 movs r2, #0
80021bc: 701a strb r2, [r3, #0]
hpcd->OUT_ep[i].maxpacket = 0U;
80021be: 7bfa ldrb r2, [r7, #15]
80021c0: 6879 ldr r1, [r7, #4]
80021c2: 4613 mov r3, r2
80021c4: 00db lsls r3, r3, #3
80021c6: 4413 add r3, r2
80021c8: 009b lsls r3, r3, #2
80021ca: 440b add r3, r1
80021cc: f503 7317 add.w r3, r3, #604 ; 0x25c
80021d0: 2200 movs r2, #0
80021d2: 601a str r2, [r3, #0]
hpcd->OUT_ep[i].xfer_buff = 0U;
80021d4: 7bfa ldrb r2, [r7, #15]
80021d6: 6879 ldr r1, [r7, #4]
80021d8: 4613 mov r3, r2
80021da: 00db lsls r3, r3, #3
80021dc: 4413 add r3, r2
80021de: 009b lsls r3, r3, #2
80021e0: 440b add r3, r1
80021e2: f503 7318 add.w r3, r3, #608 ; 0x260
80021e6: 2200 movs r2, #0
80021e8: 601a str r2, [r3, #0]
hpcd->OUT_ep[i].xfer_len = 0U;
80021ea: 7bfa ldrb r2, [r7, #15]
80021ec: 6879 ldr r1, [r7, #4]
80021ee: 4613 mov r3, r2
80021f0: 00db lsls r3, r3, #3
80021f2: 4413 add r3, r2
80021f4: 009b lsls r3, r3, #2
80021f6: 440b add r3, r1
80021f8: f503 7319 add.w r3, r3, #612 ; 0x264
80021fc: 2200 movs r2, #0
80021fe: 601a str r2, [r3, #0]
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
8002200: 7bfb ldrb r3, [r7, #15]
8002202: 3301 adds r3, #1
8002204: 73fb strb r3, [r7, #15]
8002206: 687b ldr r3, [r7, #4]
8002208: 791b ldrb r3, [r3, #4]
800220a: 7bfa ldrb r2, [r7, #15]
800220c: 429a cmp r2, r3
800220e: d3b5 bcc.n 800217c <HAL_PCD_Init+0x142>
}
/* Init Device */
if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK)
8002210: 687b ldr r3, [r7, #4]
8002212: 6818 ldr r0, [r3, #0]
8002214: 687b ldr r3, [r7, #4]
8002216: 7c1a ldrb r2, [r3, #16]
8002218: f88d 2000 strb.w r2, [sp]
800221c: 3304 adds r3, #4
800221e: cb0e ldmia r3, {r1, r2, r3}
8002220: f001 fa40 bl 80036a4 <USB_DevInit>
8002224: 4603 mov r3, r0
8002226: 2b00 cmp r3, #0
8002228: d005 beq.n 8002236 <HAL_PCD_Init+0x1fc>
{
hpcd->State = HAL_PCD_STATE_ERROR;
800222a: 687b ldr r3, [r7, #4]
800222c: 2202 movs r2, #2
800222e: f883 2495 strb.w r2, [r3, #1173] ; 0x495
return HAL_ERROR;
8002232: 2301 movs r3, #1
8002234: e00c b.n 8002250 <HAL_PCD_Init+0x216>
}
hpcd->USB_Address = 0U;
8002236: 687b ldr r3, [r7, #4]
8002238: 2200 movs r2, #0
800223a: 745a strb r2, [r3, #17]
hpcd->State = HAL_PCD_STATE_READY;
800223c: 687b ldr r3, [r7, #4]
800223e: 2201 movs r2, #1
8002240: f883 2495 strb.w r2, [r3, #1173] ; 0x495
(void)HAL_PCDEx_ActivateLPM(hpcd);
}
#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||
defined(STM32F423xx) */
(void)USB_DevDisconnect(hpcd->Instance);
8002244: 687b ldr r3, [r7, #4]
8002246: 681b ldr r3, [r3, #0]
8002248: 4618 mov r0, r3
800224a: f001 fc08 bl 8003a5e <USB_DevDisconnect>
return HAL_OK;
800224e: 2300 movs r3, #0
}
8002250: 4618 mov r0, r3
8002252: 3710 adds r7, #16
8002254: 46bd mov sp, r7
8002256: bd80 pop {r7, pc}
08002258 <HAL_RCC_OscConfig>:
* supported by this API. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8002258: b580 push {r7, lr}
800225a: b086 sub sp, #24
800225c: af00 add r7, sp, #0
800225e: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t pll_config;
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
8002260: 687b ldr r3, [r7, #4]
8002262: 2b00 cmp r3, #0
8002264: d101 bne.n 800226a <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
8002266: 2301 movs r3, #1
8002268: e267 b.n 800273a <HAL_RCC_OscConfig+0x4e2>
}
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
800226a: 687b ldr r3, [r7, #4]
800226c: 681b ldr r3, [r3, #0]
800226e: f003 0301 and.w r3, r3, #1
8002272: 2b00 cmp r3, #0
8002274: d075 beq.n 8002362 <HAL_RCC_OscConfig+0x10a>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || \
8002276: 4b88 ldr r3, [pc, #544] ; (8002498 <HAL_RCC_OscConfig+0x240>)
8002278: 689b ldr r3, [r3, #8]
800227a: f003 030c and.w r3, r3, #12
800227e: 2b04 cmp r3, #4
8002280: d00c beq.n 800229c <HAL_RCC_OscConfig+0x44>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
8002282: 4b85 ldr r3, [pc, #532] ; (8002498 <HAL_RCC_OscConfig+0x240>)
8002284: 689b ldr r3, [r3, #8]
8002286: f003 030c and.w r3, r3, #12
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || \
800228a: 2b08 cmp r3, #8
800228c: d112 bne.n 80022b4 <HAL_RCC_OscConfig+0x5c>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
800228e: 4b82 ldr r3, [pc, #520] ; (8002498 <HAL_RCC_OscConfig+0x240>)
8002290: 685b ldr r3, [r3, #4]
8002292: f403 0380 and.w r3, r3, #4194304 ; 0x400000
8002296: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
800229a: d10b bne.n 80022b4 <HAL_RCC_OscConfig+0x5c>
{
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
800229c: 4b7e ldr r3, [pc, #504] ; (8002498 <HAL_RCC_OscConfig+0x240>)
800229e: 681b ldr r3, [r3, #0]
80022a0: f403 3300 and.w r3, r3, #131072 ; 0x20000
80022a4: 2b00 cmp r3, #0
80022a6: d05b beq.n 8002360 <HAL_RCC_OscConfig+0x108>
80022a8: 687b ldr r3, [r7, #4]
80022aa: 685b ldr r3, [r3, #4]
80022ac: 2b00 cmp r3, #0
80022ae: d157 bne.n 8002360 <HAL_RCC_OscConfig+0x108>
{
return HAL_ERROR;
80022b0: 2301 movs r3, #1
80022b2: e242 b.n 800273a <HAL_RCC_OscConfig+0x4e2>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
80022b4: 687b ldr r3, [r7, #4]
80022b6: 685b ldr r3, [r3, #4]
80022b8: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
80022bc: d106 bne.n 80022cc <HAL_RCC_OscConfig+0x74>
80022be: 4b76 ldr r3, [pc, #472] ; (8002498 <HAL_RCC_OscConfig+0x240>)
80022c0: 681b ldr r3, [r3, #0]
80022c2: 4a75 ldr r2, [pc, #468] ; (8002498 <HAL_RCC_OscConfig+0x240>)
80022c4: f443 3380 orr.w r3, r3, #65536 ; 0x10000
80022c8: 6013 str r3, [r2, #0]
80022ca: e01d b.n 8002308 <HAL_RCC_OscConfig+0xb0>
80022cc: 687b ldr r3, [r7, #4]
80022ce: 685b ldr r3, [r3, #4]
80022d0: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
80022d4: d10c bne.n 80022f0 <HAL_RCC_OscConfig+0x98>
80022d6: 4b70 ldr r3, [pc, #448] ; (8002498 <HAL_RCC_OscConfig+0x240>)
80022d8: 681b ldr r3, [r3, #0]
80022da: 4a6f ldr r2, [pc, #444] ; (8002498 <HAL_RCC_OscConfig+0x240>)
80022dc: f443 2380 orr.w r3, r3, #262144 ; 0x40000
80022e0: 6013 str r3, [r2, #0]
80022e2: 4b6d ldr r3, [pc, #436] ; (8002498 <HAL_RCC_OscConfig+0x240>)
80022e4: 681b ldr r3, [r3, #0]
80022e6: 4a6c ldr r2, [pc, #432] ; (8002498 <HAL_RCC_OscConfig+0x240>)
80022e8: f443 3380 orr.w r3, r3, #65536 ; 0x10000
80022ec: 6013 str r3, [r2, #0]
80022ee: e00b b.n 8002308 <HAL_RCC_OscConfig+0xb0>
80022f0: 4b69 ldr r3, [pc, #420] ; (8002498 <HAL_RCC_OscConfig+0x240>)
80022f2: 681b ldr r3, [r3, #0]
80022f4: 4a68 ldr r2, [pc, #416] ; (8002498 <HAL_RCC_OscConfig+0x240>)
80022f6: f423 3380 bic.w r3, r3, #65536 ; 0x10000
80022fa: 6013 str r3, [r2, #0]
80022fc: 4b66 ldr r3, [pc, #408] ; (8002498 <HAL_RCC_OscConfig+0x240>)
80022fe: 681b ldr r3, [r3, #0]
8002300: 4a65 ldr r2, [pc, #404] ; (8002498 <HAL_RCC_OscConfig+0x240>)
8002302: f423 2380 bic.w r3, r3, #262144 ; 0x40000
8002306: 6013 str r3, [r2, #0]
/* Check the HSE State */
if ((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
8002308: 687b ldr r3, [r7, #4]
800230a: 685b ldr r3, [r3, #4]
800230c: 2b00 cmp r3, #0
800230e: d013 beq.n 8002338 <HAL_RCC_OscConfig+0xe0>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8002310: f7ff f84e bl 80013b0 <HAL_GetTick>
8002314: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8002316: e008 b.n 800232a <HAL_RCC_OscConfig+0xd2>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8002318: f7ff f84a bl 80013b0 <HAL_GetTick>
800231c: 4602 mov r2, r0
800231e: 693b ldr r3, [r7, #16]
8002320: 1ad3 subs r3, r2, r3
8002322: 2b64 cmp r3, #100 ; 0x64
8002324: d901 bls.n 800232a <HAL_RCC_OscConfig+0xd2>
{
return HAL_TIMEOUT;
8002326: 2303 movs r3, #3
8002328: e207 b.n 800273a <HAL_RCC_OscConfig+0x4e2>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
800232a: 4b5b ldr r3, [pc, #364] ; (8002498 <HAL_RCC_OscConfig+0x240>)
800232c: 681b ldr r3, [r3, #0]
800232e: f403 3300 and.w r3, r3, #131072 ; 0x20000
8002332: 2b00 cmp r3, #0
8002334: d0f0 beq.n 8002318 <HAL_RCC_OscConfig+0xc0>
8002336: e014 b.n 8002362 <HAL_RCC_OscConfig+0x10a>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8002338: f7ff f83a bl 80013b0 <HAL_GetTick>
800233c: 6138 str r0, [r7, #16]
/* Wait till HSE is bypassed or disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
800233e: e008 b.n 8002352 <HAL_RCC_OscConfig+0xfa>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8002340: f7ff f836 bl 80013b0 <HAL_GetTick>
8002344: 4602 mov r2, r0
8002346: 693b ldr r3, [r7, #16]
8002348: 1ad3 subs r3, r2, r3
800234a: 2b64 cmp r3, #100 ; 0x64
800234c: d901 bls.n 8002352 <HAL_RCC_OscConfig+0xfa>
{
return HAL_TIMEOUT;
800234e: 2303 movs r3, #3
8002350: e1f3 b.n 800273a <HAL_RCC_OscConfig+0x4e2>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8002352: 4b51 ldr r3, [pc, #324] ; (8002498 <HAL_RCC_OscConfig+0x240>)
8002354: 681b ldr r3, [r3, #0]
8002356: f403 3300 and.w r3, r3, #131072 ; 0x20000
800235a: 2b00 cmp r3, #0
800235c: d1f0 bne.n 8002340 <HAL_RCC_OscConfig+0xe8>
800235e: e000 b.n 8002362 <HAL_RCC_OscConfig+0x10a>
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8002360: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8002362: 687b ldr r3, [r7, #4]
8002364: 681b ldr r3, [r3, #0]
8002366: f003 0302 and.w r3, r3, #2
800236a: 2b00 cmp r3, #0
800236c: d063 beq.n 8002436 <HAL_RCC_OscConfig+0x1de>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || \
800236e: 4b4a ldr r3, [pc, #296] ; (8002498 <HAL_RCC_OscConfig+0x240>)
8002370: 689b ldr r3, [r3, #8]
8002372: f003 030c and.w r3, r3, #12
8002376: 2b00 cmp r3, #0
8002378: d00b beq.n 8002392 <HAL_RCC_OscConfig+0x13a>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
800237a: 4b47 ldr r3, [pc, #284] ; (8002498 <HAL_RCC_OscConfig+0x240>)
800237c: 689b ldr r3, [r3, #8]
800237e: f003 030c and.w r3, r3, #12
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || \
8002382: 2b08 cmp r3, #8
8002384: d11c bne.n 80023c0 <HAL_RCC_OscConfig+0x168>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
8002386: 4b44 ldr r3, [pc, #272] ; (8002498 <HAL_RCC_OscConfig+0x240>)
8002388: 685b ldr r3, [r3, #4]
800238a: f403 0380 and.w r3, r3, #4194304 ; 0x400000
800238e: 2b00 cmp r3, #0
8002390: d116 bne.n 80023c0 <HAL_RCC_OscConfig+0x168>
{
/* When HSI is used as system clock it will not disabled */
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8002392: 4b41 ldr r3, [pc, #260] ; (8002498 <HAL_RCC_OscConfig+0x240>)
8002394: 681b ldr r3, [r3, #0]
8002396: f003 0302 and.w r3, r3, #2
800239a: 2b00 cmp r3, #0
800239c: d005 beq.n 80023aa <HAL_RCC_OscConfig+0x152>
800239e: 687b ldr r3, [r7, #4]
80023a0: 68db ldr r3, [r3, #12]
80023a2: 2b01 cmp r3, #1
80023a4: d001 beq.n 80023aa <HAL_RCC_OscConfig+0x152>
{
return HAL_ERROR;
80023a6: 2301 movs r3, #1
80023a8: e1c7 b.n 800273a <HAL_RCC_OscConfig+0x4e2>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
80023aa: 4b3b ldr r3, [pc, #236] ; (8002498 <HAL_RCC_OscConfig+0x240>)
80023ac: 681b ldr r3, [r3, #0]
80023ae: f023 02f8 bic.w r2, r3, #248 ; 0xf8
80023b2: 687b ldr r3, [r7, #4]
80023b4: 691b ldr r3, [r3, #16]
80023b6: 00db lsls r3, r3, #3
80023b8: 4937 ldr r1, [pc, #220] ; (8002498 <HAL_RCC_OscConfig+0x240>)
80023ba: 4313 orrs r3, r2
80023bc: 600b str r3, [r1, #0]
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
80023be: e03a b.n 8002436 <HAL_RCC_OscConfig+0x1de>
}
}
else
{
/* Check the HSI State */
if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
80023c0: 687b ldr r3, [r7, #4]
80023c2: 68db ldr r3, [r3, #12]
80023c4: 2b00 cmp r3, #0
80023c6: d020 beq.n 800240a <HAL_RCC_OscConfig+0x1b2>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
80023c8: 4b34 ldr r3, [pc, #208] ; (800249c <HAL_RCC_OscConfig+0x244>)
80023ca: 2201 movs r2, #1
80023cc: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80023ce: f7fe ffef bl 80013b0 <HAL_GetTick>
80023d2: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
80023d4: e008 b.n 80023e8 <HAL_RCC_OscConfig+0x190>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
80023d6: f7fe ffeb bl 80013b0 <HAL_GetTick>
80023da: 4602 mov r2, r0
80023dc: 693b ldr r3, [r7, #16]
80023de: 1ad3 subs r3, r2, r3
80023e0: 2b02 cmp r3, #2
80023e2: d901 bls.n 80023e8 <HAL_RCC_OscConfig+0x190>
{
return HAL_TIMEOUT;
80023e4: 2303 movs r3, #3
80023e6: e1a8 b.n 800273a <HAL_RCC_OscConfig+0x4e2>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
80023e8: 4b2b ldr r3, [pc, #172] ; (8002498 <HAL_RCC_OscConfig+0x240>)
80023ea: 681b ldr r3, [r3, #0]
80023ec: f003 0302 and.w r3, r3, #2
80023f0: 2b00 cmp r3, #0
80023f2: d0f0 beq.n 80023d6 <HAL_RCC_OscConfig+0x17e>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value. */
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
80023f4: 4b28 ldr r3, [pc, #160] ; (8002498 <HAL_RCC_OscConfig+0x240>)
80023f6: 681b ldr r3, [r3, #0]
80023f8: f023 02f8 bic.w r2, r3, #248 ; 0xf8
80023fc: 687b ldr r3, [r7, #4]
80023fe: 691b ldr r3, [r3, #16]
8002400: 00db lsls r3, r3, #3
8002402: 4925 ldr r1, [pc, #148] ; (8002498 <HAL_RCC_OscConfig+0x240>)
8002404: 4313 orrs r3, r2
8002406: 600b str r3, [r1, #0]
8002408: e015 b.n 8002436 <HAL_RCC_OscConfig+0x1de>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
800240a: 4b24 ldr r3, [pc, #144] ; (800249c <HAL_RCC_OscConfig+0x244>)
800240c: 2200 movs r2, #0
800240e: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002410: f7fe ffce bl 80013b0 <HAL_GetTick>
8002414: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8002416: e008 b.n 800242a <HAL_RCC_OscConfig+0x1d2>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8002418: f7fe ffca bl 80013b0 <HAL_GetTick>
800241c: 4602 mov r2, r0
800241e: 693b ldr r3, [r7, #16]
8002420: 1ad3 subs r3, r2, r3
8002422: 2b02 cmp r3, #2
8002424: d901 bls.n 800242a <HAL_RCC_OscConfig+0x1d2>
{
return HAL_TIMEOUT;
8002426: 2303 movs r3, #3
8002428: e187 b.n 800273a <HAL_RCC_OscConfig+0x4e2>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
800242a: 4b1b ldr r3, [pc, #108] ; (8002498 <HAL_RCC_OscConfig+0x240>)
800242c: 681b ldr r3, [r3, #0]
800242e: f003 0302 and.w r3, r3, #2
8002432: 2b00 cmp r3, #0
8002434: d1f0 bne.n 8002418 <HAL_RCC_OscConfig+0x1c0>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8002436: 687b ldr r3, [r7, #4]
8002438: 681b ldr r3, [r3, #0]
800243a: f003 0308 and.w r3, r3, #8
800243e: 2b00 cmp r3, #0
8002440: d036 beq.n 80024b0 <HAL_RCC_OscConfig+0x258>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
8002442: 687b ldr r3, [r7, #4]
8002444: 695b ldr r3, [r3, #20]
8002446: 2b00 cmp r3, #0
8002448: d016 beq.n 8002478 <HAL_RCC_OscConfig+0x220>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
800244a: 4b15 ldr r3, [pc, #84] ; (80024a0 <HAL_RCC_OscConfig+0x248>)
800244c: 2201 movs r2, #1
800244e: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002450: f7fe ffae bl 80013b0 <HAL_GetTick>
8002454: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8002456: e008 b.n 800246a <HAL_RCC_OscConfig+0x212>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8002458: f7fe ffaa bl 80013b0 <HAL_GetTick>
800245c: 4602 mov r2, r0
800245e: 693b ldr r3, [r7, #16]
8002460: 1ad3 subs r3, r2, r3
8002462: 2b02 cmp r3, #2
8002464: d901 bls.n 800246a <HAL_RCC_OscConfig+0x212>
{
return HAL_TIMEOUT;
8002466: 2303 movs r3, #3
8002468: e167 b.n 800273a <HAL_RCC_OscConfig+0x4e2>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
800246a: 4b0b ldr r3, [pc, #44] ; (8002498 <HAL_RCC_OscConfig+0x240>)
800246c: 6f5b ldr r3, [r3, #116] ; 0x74
800246e: f003 0302 and.w r3, r3, #2
8002472: 2b00 cmp r3, #0
8002474: d0f0 beq.n 8002458 <HAL_RCC_OscConfig+0x200>
8002476: e01b b.n 80024b0 <HAL_RCC_OscConfig+0x258>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8002478: 4b09 ldr r3, [pc, #36] ; (80024a0 <HAL_RCC_OscConfig+0x248>)
800247a: 2200 movs r2, #0
800247c: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
800247e: f7fe ff97 bl 80013b0 <HAL_GetTick>
8002482: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8002484: e00e b.n 80024a4 <HAL_RCC_OscConfig+0x24c>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8002486: f7fe ff93 bl 80013b0 <HAL_GetTick>
800248a: 4602 mov r2, r0
800248c: 693b ldr r3, [r7, #16]
800248e: 1ad3 subs r3, r2, r3
8002490: 2b02 cmp r3, #2
8002492: d907 bls.n 80024a4 <HAL_RCC_OscConfig+0x24c>
{
return HAL_TIMEOUT;
8002494: 2303 movs r3, #3
8002496: e150 b.n 800273a <HAL_RCC_OscConfig+0x4e2>
8002498: 40023800 .word 0x40023800
800249c: 42470000 .word 0x42470000
80024a0: 42470e80 .word 0x42470e80
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
80024a4: 4b88 ldr r3, [pc, #544] ; (80026c8 <HAL_RCC_OscConfig+0x470>)
80024a6: 6f5b ldr r3, [r3, #116] ; 0x74
80024a8: f003 0302 and.w r3, r3, #2
80024ac: 2b00 cmp r3, #0
80024ae: d1ea bne.n 8002486 <HAL_RCC_OscConfig+0x22e>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
80024b0: 687b ldr r3, [r7, #4]
80024b2: 681b ldr r3, [r3, #0]
80024b4: f003 0304 and.w r3, r3, #4
80024b8: 2b00 cmp r3, #0
80024ba: f000 8097 beq.w 80025ec <HAL_RCC_OscConfig+0x394>
{
FlagStatus pwrclkchanged = RESET;
80024be: 2300 movs r3, #0
80024c0: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
80024c2: 4b81 ldr r3, [pc, #516] ; (80026c8 <HAL_RCC_OscConfig+0x470>)
80024c4: 6c1b ldr r3, [r3, #64] ; 0x40
80024c6: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
80024ca: 2b00 cmp r3, #0
80024cc: d10f bne.n 80024ee <HAL_RCC_OscConfig+0x296>
{
__HAL_RCC_PWR_CLK_ENABLE();
80024ce: 2300 movs r3, #0
80024d0: 60bb str r3, [r7, #8]
80024d2: 4b7d ldr r3, [pc, #500] ; (80026c8 <HAL_RCC_OscConfig+0x470>)
80024d4: 6c1b ldr r3, [r3, #64] ; 0x40
80024d6: 4a7c ldr r2, [pc, #496] ; (80026c8 <HAL_RCC_OscConfig+0x470>)
80024d8: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
80024dc: 6413 str r3, [r2, #64] ; 0x40
80024de: 4b7a ldr r3, [pc, #488] ; (80026c8 <HAL_RCC_OscConfig+0x470>)
80024e0: 6c1b ldr r3, [r3, #64] ; 0x40
80024e2: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
80024e6: 60bb str r3, [r7, #8]
80024e8: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
80024ea: 2301 movs r3, #1
80024ec: 75fb strb r3, [r7, #23]
}
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80024ee: 4b77 ldr r3, [pc, #476] ; (80026cc <HAL_RCC_OscConfig+0x474>)
80024f0: 681b ldr r3, [r3, #0]
80024f2: f403 7380 and.w r3, r3, #256 ; 0x100
80024f6: 2b00 cmp r3, #0
80024f8: d118 bne.n 800252c <HAL_RCC_OscConfig+0x2d4>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
80024fa: 4b74 ldr r3, [pc, #464] ; (80026cc <HAL_RCC_OscConfig+0x474>)
80024fc: 681b ldr r3, [r3, #0]
80024fe: 4a73 ldr r2, [pc, #460] ; (80026cc <HAL_RCC_OscConfig+0x474>)
8002500: f443 7380 orr.w r3, r3, #256 ; 0x100
8002504: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8002506: f7fe ff53 bl 80013b0 <HAL_GetTick>
800250a: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
800250c: e008 b.n 8002520 <HAL_RCC_OscConfig+0x2c8>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
800250e: f7fe ff4f bl 80013b0 <HAL_GetTick>
8002512: 4602 mov r2, r0
8002514: 693b ldr r3, [r7, #16]
8002516: 1ad3 subs r3, r2, r3
8002518: 2b02 cmp r3, #2
800251a: d901 bls.n 8002520 <HAL_RCC_OscConfig+0x2c8>
{
return HAL_TIMEOUT;
800251c: 2303 movs r3, #3
800251e: e10c b.n 800273a <HAL_RCC_OscConfig+0x4e2>
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8002520: 4b6a ldr r3, [pc, #424] ; (80026cc <HAL_RCC_OscConfig+0x474>)
8002522: 681b ldr r3, [r3, #0]
8002524: f403 7380 and.w r3, r3, #256 ; 0x100
8002528: 2b00 cmp r3, #0
800252a: d0f0 beq.n 800250e <HAL_RCC_OscConfig+0x2b6>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
800252c: 687b ldr r3, [r7, #4]
800252e: 689b ldr r3, [r3, #8]
8002530: 2b01 cmp r3, #1
8002532: d106 bne.n 8002542 <HAL_RCC_OscConfig+0x2ea>
8002534: 4b64 ldr r3, [pc, #400] ; (80026c8 <HAL_RCC_OscConfig+0x470>)
8002536: 6f1b ldr r3, [r3, #112] ; 0x70
8002538: 4a63 ldr r2, [pc, #396] ; (80026c8 <HAL_RCC_OscConfig+0x470>)
800253a: f043 0301 orr.w r3, r3, #1
800253e: 6713 str r3, [r2, #112] ; 0x70
8002540: e01c b.n 800257c <HAL_RCC_OscConfig+0x324>
8002542: 687b ldr r3, [r7, #4]
8002544: 689b ldr r3, [r3, #8]
8002546: 2b05 cmp r3, #5
8002548: d10c bne.n 8002564 <HAL_RCC_OscConfig+0x30c>
800254a: 4b5f ldr r3, [pc, #380] ; (80026c8 <HAL_RCC_OscConfig+0x470>)
800254c: 6f1b ldr r3, [r3, #112] ; 0x70
800254e: 4a5e ldr r2, [pc, #376] ; (80026c8 <HAL_RCC_OscConfig+0x470>)
8002550: f043 0304 orr.w r3, r3, #4
8002554: 6713 str r3, [r2, #112] ; 0x70
8002556: 4b5c ldr r3, [pc, #368] ; (80026c8 <HAL_RCC_OscConfig+0x470>)
8002558: 6f1b ldr r3, [r3, #112] ; 0x70
800255a: 4a5b ldr r2, [pc, #364] ; (80026c8 <HAL_RCC_OscConfig+0x470>)
800255c: f043 0301 orr.w r3, r3, #1
8002560: 6713 str r3, [r2, #112] ; 0x70
8002562: e00b b.n 800257c <HAL_RCC_OscConfig+0x324>
8002564: 4b58 ldr r3, [pc, #352] ; (80026c8 <HAL_RCC_OscConfig+0x470>)
8002566: 6f1b ldr r3, [r3, #112] ; 0x70
8002568: 4a57 ldr r2, [pc, #348] ; (80026c8 <HAL_RCC_OscConfig+0x470>)
800256a: f023 0301 bic.w r3, r3, #1
800256e: 6713 str r3, [r2, #112] ; 0x70
8002570: 4b55 ldr r3, [pc, #340] ; (80026c8 <HAL_RCC_OscConfig+0x470>)
8002572: 6f1b ldr r3, [r3, #112] ; 0x70
8002574: 4a54 ldr r2, [pc, #336] ; (80026c8 <HAL_RCC_OscConfig+0x470>)
8002576: f023 0304 bic.w r3, r3, #4
800257a: 6713 str r3, [r2, #112] ; 0x70
/* Check the LSE State */
if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
800257c: 687b ldr r3, [r7, #4]
800257e: 689b ldr r3, [r3, #8]
8002580: 2b00 cmp r3, #0
8002582: d015 beq.n 80025b0 <HAL_RCC_OscConfig+0x358>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002584: f7fe ff14 bl 80013b0 <HAL_GetTick>
8002588: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
800258a: e00a b.n 80025a2 <HAL_RCC_OscConfig+0x34a>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
800258c: f7fe ff10 bl 80013b0 <HAL_GetTick>
8002590: 4602 mov r2, r0
8002592: 693b ldr r3, [r7, #16]
8002594: 1ad3 subs r3, r2, r3
8002596: f241 3288 movw r2, #5000 ; 0x1388
800259a: 4293 cmp r3, r2
800259c: d901 bls.n 80025a2 <HAL_RCC_OscConfig+0x34a>
{
return HAL_TIMEOUT;
800259e: 2303 movs r3, #3
80025a0: e0cb b.n 800273a <HAL_RCC_OscConfig+0x4e2>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
80025a2: 4b49 ldr r3, [pc, #292] ; (80026c8 <HAL_RCC_OscConfig+0x470>)
80025a4: 6f1b ldr r3, [r3, #112] ; 0x70
80025a6: f003 0302 and.w r3, r3, #2
80025aa: 2b00 cmp r3, #0
80025ac: d0ee beq.n 800258c <HAL_RCC_OscConfig+0x334>
80025ae: e014 b.n 80025da <HAL_RCC_OscConfig+0x382>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80025b0: f7fe fefe bl 80013b0 <HAL_GetTick>
80025b4: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
80025b6: e00a b.n 80025ce <HAL_RCC_OscConfig+0x376>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
80025b8: f7fe fefa bl 80013b0 <HAL_GetTick>
80025bc: 4602 mov r2, r0
80025be: 693b ldr r3, [r7, #16]
80025c0: 1ad3 subs r3, r2, r3
80025c2: f241 3288 movw r2, #5000 ; 0x1388
80025c6: 4293 cmp r3, r2
80025c8: d901 bls.n 80025ce <HAL_RCC_OscConfig+0x376>
{
return HAL_TIMEOUT;
80025ca: 2303 movs r3, #3
80025cc: e0b5 b.n 800273a <HAL_RCC_OscConfig+0x4e2>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
80025ce: 4b3e ldr r3, [pc, #248] ; (80026c8 <HAL_RCC_OscConfig+0x470>)
80025d0: 6f1b ldr r3, [r3, #112] ; 0x70
80025d2: f003 0302 and.w r3, r3, #2
80025d6: 2b00 cmp r3, #0
80025d8: d1ee bne.n 80025b8 <HAL_RCC_OscConfig+0x360>
}
}
}
/* Restore clock configuration if changed */
if (pwrclkchanged == SET)
80025da: 7dfb ldrb r3, [r7, #23]
80025dc: 2b01 cmp r3, #1
80025de: d105 bne.n 80025ec <HAL_RCC_OscConfig+0x394>
{
__HAL_RCC_PWR_CLK_DISABLE();
80025e0: 4b39 ldr r3, [pc, #228] ; (80026c8 <HAL_RCC_OscConfig+0x470>)
80025e2: 6c1b ldr r3, [r3, #64] ; 0x40
80025e4: 4a38 ldr r2, [pc, #224] ; (80026c8 <HAL_RCC_OscConfig+0x470>)
80025e6: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
80025ea: 6413 str r3, [r2, #64] ; 0x40
}
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
80025ec: 687b ldr r3, [r7, #4]
80025ee: 699b ldr r3, [r3, #24]
80025f0: 2b00 cmp r3, #0
80025f2: f000 80a1 beq.w 8002738 <HAL_RCC_OscConfig+0x4e0>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
80025f6: 4b34 ldr r3, [pc, #208] ; (80026c8 <HAL_RCC_OscConfig+0x470>)
80025f8: 689b ldr r3, [r3, #8]
80025fa: f003 030c and.w r3, r3, #12
80025fe: 2b08 cmp r3, #8
8002600: d05c beq.n 80026bc <HAL_RCC_OscConfig+0x464>
{
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
8002602: 687b ldr r3, [r7, #4]
8002604: 699b ldr r3, [r3, #24]
8002606: 2b02 cmp r3, #2
8002608: d141 bne.n 800268e <HAL_RCC_OscConfig+0x436>
assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
800260a: 4b31 ldr r3, [pc, #196] ; (80026d0 <HAL_RCC_OscConfig+0x478>)
800260c: 2200 movs r2, #0
800260e: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002610: f7fe fece bl 80013b0 <HAL_GetTick>
8002614: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8002616: e008 b.n 800262a <HAL_RCC_OscConfig+0x3d2>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8002618: f7fe feca bl 80013b0 <HAL_GetTick>
800261c: 4602 mov r2, r0
800261e: 693b ldr r3, [r7, #16]
8002620: 1ad3 subs r3, r2, r3
8002622: 2b02 cmp r3, #2
8002624: d901 bls.n 800262a <HAL_RCC_OscConfig+0x3d2>
{
return HAL_TIMEOUT;
8002626: 2303 movs r3, #3
8002628: e087 b.n 800273a <HAL_RCC_OscConfig+0x4e2>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
800262a: 4b27 ldr r3, [pc, #156] ; (80026c8 <HAL_RCC_OscConfig+0x470>)
800262c: 681b ldr r3, [r3, #0]
800262e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8002632: 2b00 cmp r3, #0
8002634: d1f0 bne.n 8002618 <HAL_RCC_OscConfig+0x3c0>
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
8002636: 687b ldr r3, [r7, #4]
8002638: 69da ldr r2, [r3, #28]
800263a: 687b ldr r3, [r7, #4]
800263c: 6a1b ldr r3, [r3, #32]
800263e: 431a orrs r2, r3
8002640: 687b ldr r3, [r7, #4]
8002642: 6a5b ldr r3, [r3, #36] ; 0x24
8002644: 019b lsls r3, r3, #6
8002646: 431a orrs r2, r3
8002648: 687b ldr r3, [r7, #4]
800264a: 6a9b ldr r3, [r3, #40] ; 0x28
800264c: 085b lsrs r3, r3, #1
800264e: 3b01 subs r3, #1
8002650: 041b lsls r3, r3, #16
8002652: 431a orrs r2, r3
8002654: 687b ldr r3, [r7, #4]
8002656: 6adb ldr r3, [r3, #44] ; 0x2c
8002658: 061b lsls r3, r3, #24
800265a: 491b ldr r1, [pc, #108] ; (80026c8 <HAL_RCC_OscConfig+0x470>)
800265c: 4313 orrs r3, r2
800265e: 604b str r3, [r1, #4]
RCC_OscInitStruct->PLL.PLLM | \
(RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \
(((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \
(RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)));
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8002660: 4b1b ldr r3, [pc, #108] ; (80026d0 <HAL_RCC_OscConfig+0x478>)
8002662: 2201 movs r2, #1
8002664: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002666: f7fe fea3 bl 80013b0 <HAL_GetTick>
800266a: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
800266c: e008 b.n 8002680 <HAL_RCC_OscConfig+0x428>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
800266e: f7fe fe9f bl 80013b0 <HAL_GetTick>
8002672: 4602 mov r2, r0
8002674: 693b ldr r3, [r7, #16]
8002676: 1ad3 subs r3, r2, r3
8002678: 2b02 cmp r3, #2
800267a: d901 bls.n 8002680 <HAL_RCC_OscConfig+0x428>
{
return HAL_TIMEOUT;
800267c: 2303 movs r3, #3
800267e: e05c b.n 800273a <HAL_RCC_OscConfig+0x4e2>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8002680: 4b11 ldr r3, [pc, #68] ; (80026c8 <HAL_RCC_OscConfig+0x470>)
8002682: 681b ldr r3, [r3, #0]
8002684: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8002688: 2b00 cmp r3, #0
800268a: d0f0 beq.n 800266e <HAL_RCC_OscConfig+0x416>
800268c: e054 b.n 8002738 <HAL_RCC_OscConfig+0x4e0>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
800268e: 4b10 ldr r3, [pc, #64] ; (80026d0 <HAL_RCC_OscConfig+0x478>)
8002690: 2200 movs r2, #0
8002692: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002694: f7fe fe8c bl 80013b0 <HAL_GetTick>
8002698: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
800269a: e008 b.n 80026ae <HAL_RCC_OscConfig+0x456>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
800269c: f7fe fe88 bl 80013b0 <HAL_GetTick>
80026a0: 4602 mov r2, r0
80026a2: 693b ldr r3, [r7, #16]
80026a4: 1ad3 subs r3, r2, r3
80026a6: 2b02 cmp r3, #2
80026a8: d901 bls.n 80026ae <HAL_RCC_OscConfig+0x456>
{
return HAL_TIMEOUT;
80026aa: 2303 movs r3, #3
80026ac: e045 b.n 800273a <HAL_RCC_OscConfig+0x4e2>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80026ae: 4b06 ldr r3, [pc, #24] ; (80026c8 <HAL_RCC_OscConfig+0x470>)
80026b0: 681b ldr r3, [r3, #0]
80026b2: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
80026b6: 2b00 cmp r3, #0
80026b8: d1f0 bne.n 800269c <HAL_RCC_OscConfig+0x444>
80026ba: e03d b.n 8002738 <HAL_RCC_OscConfig+0x4e0>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
80026bc: 687b ldr r3, [r7, #4]
80026be: 699b ldr r3, [r3, #24]
80026c0: 2b01 cmp r3, #1
80026c2: d107 bne.n 80026d4 <HAL_RCC_OscConfig+0x47c>
{
return HAL_ERROR;
80026c4: 2301 movs r3, #1
80026c6: e038 b.n 800273a <HAL_RCC_OscConfig+0x4e2>
80026c8: 40023800 .word 0x40023800
80026cc: 40007000 .word 0x40007000
80026d0: 42470060 .word 0x42470060
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->PLLCFGR;
80026d4: 4b1b ldr r3, [pc, #108] ; (8002744 <HAL_RCC_OscConfig+0x4ec>)
80026d6: 685b ldr r3, [r3, #4]
80026d8: 60fb str r3, [r7, #12]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
#else
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
80026da: 687b ldr r3, [r7, #4]
80026dc: 699b ldr r3, [r3, #24]
80026de: 2b01 cmp r3, #1
80026e0: d028 beq.n 8002734 <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80026e2: 68fb ldr r3, [r7, #12]
80026e4: f403 0280 and.w r2, r3, #4194304 ; 0x400000
80026e8: 687b ldr r3, [r7, #4]
80026ea: 69db ldr r3, [r3, #28]
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
80026ec: 429a cmp r2, r3
80026ee: d121 bne.n 8002734 <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
80026f0: 68fb ldr r3, [r7, #12]
80026f2: f003 023f and.w r2, r3, #63 ; 0x3f
80026f6: 687b ldr r3, [r7, #4]
80026f8: 6a1b ldr r3, [r3, #32]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80026fa: 429a cmp r2, r3
80026fc: d11a bne.n 8002734 <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
80026fe: 68fa ldr r2, [r7, #12]
8002700: f647 73c0 movw r3, #32704 ; 0x7fc0
8002704: 4013 ands r3, r2
8002706: 687a ldr r2, [r7, #4]
8002708: 6a52 ldr r2, [r2, #36] ; 0x24
800270a: 0192 lsls r2, r2, #6
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
800270c: 4293 cmp r3, r2
800270e: d111 bne.n 8002734 <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
8002710: 68fb ldr r3, [r7, #12]
8002712: f403 3240 and.w r2, r3, #196608 ; 0x30000
8002716: 687b ldr r3, [r7, #4]
8002718: 6a9b ldr r3, [r3, #40] ; 0x28
800271a: 085b lsrs r3, r3, #1
800271c: 3b01 subs r3, #1
800271e: 041b lsls r3, r3, #16
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
8002720: 429a cmp r2, r3
8002722: d107 bne.n 8002734 <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
8002724: 68fb ldr r3, [r7, #12]
8002726: f003 6270 and.w r2, r3, #251658240 ; 0xf000000
800272a: 687b ldr r3, [r7, #4]
800272c: 6adb ldr r3, [r3, #44] ; 0x2c
800272e: 061b lsls r3, r3, #24
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
8002730: 429a cmp r2, r3
8002732: d001 beq.n 8002738 <HAL_RCC_OscConfig+0x4e0>
#endif /* RCC_PLLCFGR_PLLR */
{
return HAL_ERROR;
8002734: 2301 movs r3, #1
8002736: e000 b.n 800273a <HAL_RCC_OscConfig+0x4e2>
}
}
}
}
return HAL_OK;
8002738: 2300 movs r3, #0
}
800273a: 4618 mov r0, r3
800273c: 3718 adds r7, #24
800273e: 46bd mov sp, r7
8002740: bd80 pop {r7, pc}
8002742: bf00 nop
8002744: 40023800 .word 0x40023800
08002748 <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8002748: b580 push {r7, lr}
800274a: b084 sub sp, #16
800274c: af00 add r7, sp, #0
800274e: 6078 str r0, [r7, #4]
8002750: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
8002752: 687b ldr r3, [r7, #4]
8002754: 2b00 cmp r3, #0
8002756: d101 bne.n 800275c <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
8002758: 2301 movs r3, #1
800275a: e0cc b.n 80028f6 <HAL_RCC_ClockConfig+0x1ae>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
800275c: 4b68 ldr r3, [pc, #416] ; (8002900 <HAL_RCC_ClockConfig+0x1b8>)
800275e: 681b ldr r3, [r3, #0]
8002760: f003 030f and.w r3, r3, #15
8002764: 683a ldr r2, [r7, #0]
8002766: 429a cmp r2, r3
8002768: d90c bls.n 8002784 <HAL_RCC_ClockConfig+0x3c>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
800276a: 4b65 ldr r3, [pc, #404] ; (8002900 <HAL_RCC_ClockConfig+0x1b8>)
800276c: 683a ldr r2, [r7, #0]
800276e: b2d2 uxtb r2, r2
8002770: 701a strb r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
8002772: 4b63 ldr r3, [pc, #396] ; (8002900 <HAL_RCC_ClockConfig+0x1b8>)
8002774: 681b ldr r3, [r3, #0]
8002776: f003 030f and.w r3, r3, #15
800277a: 683a ldr r2, [r7, #0]
800277c: 429a cmp r2, r3
800277e: d001 beq.n 8002784 <HAL_RCC_ClockConfig+0x3c>
{
return HAL_ERROR;
8002780: 2301 movs r3, #1
8002782: e0b8 b.n 80028f6 <HAL_RCC_ClockConfig+0x1ae>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8002784: 687b ldr r3, [r7, #4]
8002786: 681b ldr r3, [r3, #0]
8002788: f003 0302 and.w r3, r3, #2
800278c: 2b00 cmp r3, #0
800278e: d020 beq.n 80027d2 <HAL_RCC_ClockConfig+0x8a>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8002790: 687b ldr r3, [r7, #4]
8002792: 681b ldr r3, [r3, #0]
8002794: f003 0304 and.w r3, r3, #4
8002798: 2b00 cmp r3, #0
800279a: d005 beq.n 80027a8 <HAL_RCC_ClockConfig+0x60>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
800279c: 4b59 ldr r3, [pc, #356] ; (8002904 <HAL_RCC_ClockConfig+0x1bc>)
800279e: 689b ldr r3, [r3, #8]
80027a0: 4a58 ldr r2, [pc, #352] ; (8002904 <HAL_RCC_ClockConfig+0x1bc>)
80027a2: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00
80027a6: 6093 str r3, [r2, #8]
}
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
80027a8: 687b ldr r3, [r7, #4]
80027aa: 681b ldr r3, [r3, #0]
80027ac: f003 0308 and.w r3, r3, #8
80027b0: 2b00 cmp r3, #0
80027b2: d005 beq.n 80027c0 <HAL_RCC_ClockConfig+0x78>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
80027b4: 4b53 ldr r3, [pc, #332] ; (8002904 <HAL_RCC_ClockConfig+0x1bc>)
80027b6: 689b ldr r3, [r3, #8]
80027b8: 4a52 ldr r2, [pc, #328] ; (8002904 <HAL_RCC_ClockConfig+0x1bc>)
80027ba: f443 4360 orr.w r3, r3, #57344 ; 0xe000
80027be: 6093 str r3, [r2, #8]
}
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
80027c0: 4b50 ldr r3, [pc, #320] ; (8002904 <HAL_RCC_ClockConfig+0x1bc>)
80027c2: 689b ldr r3, [r3, #8]
80027c4: f023 02f0 bic.w r2, r3, #240 ; 0xf0
80027c8: 687b ldr r3, [r7, #4]
80027ca: 689b ldr r3, [r3, #8]
80027cc: 494d ldr r1, [pc, #308] ; (8002904 <HAL_RCC_ClockConfig+0x1bc>)
80027ce: 4313 orrs r3, r2
80027d0: 608b str r3, [r1, #8]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
80027d2: 687b ldr r3, [r7, #4]
80027d4: 681b ldr r3, [r3, #0]
80027d6: f003 0301 and.w r3, r3, #1
80027da: 2b00 cmp r3, #0
80027dc: d044 beq.n 8002868 <HAL_RCC_ClockConfig+0x120>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
80027de: 687b ldr r3, [r7, #4]
80027e0: 685b ldr r3, [r3, #4]
80027e2: 2b01 cmp r3, #1
80027e4: d107 bne.n 80027f6 <HAL_RCC_ClockConfig+0xae>
{
/* Check the HSE ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
80027e6: 4b47 ldr r3, [pc, #284] ; (8002904 <HAL_RCC_ClockConfig+0x1bc>)
80027e8: 681b ldr r3, [r3, #0]
80027ea: f403 3300 and.w r3, r3, #131072 ; 0x20000
80027ee: 2b00 cmp r3, #0
80027f0: d119 bne.n 8002826 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
80027f2: 2301 movs r3, #1
80027f4: e07f b.n 80028f6 <HAL_RCC_ClockConfig+0x1ae>
}
}
/* PLL is selected as System Clock Source */
else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
80027f6: 687b ldr r3, [r7, #4]
80027f8: 685b ldr r3, [r3, #4]
80027fa: 2b02 cmp r3, #2
80027fc: d003 beq.n 8002806 <HAL_RCC_ClockConfig+0xbe>
(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
80027fe: 687b ldr r3, [r7, #4]
8002800: 685b ldr r3, [r3, #4]
else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
8002802: 2b03 cmp r3, #3
8002804: d107 bne.n 8002816 <HAL_RCC_ClockConfig+0xce>
{
/* Check the PLL ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8002806: 4b3f ldr r3, [pc, #252] ; (8002904 <HAL_RCC_ClockConfig+0x1bc>)
8002808: 681b ldr r3, [r3, #0]
800280a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
800280e: 2b00 cmp r3, #0
8002810: d109 bne.n 8002826 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8002812: 2301 movs r3, #1
8002814: e06f b.n 80028f6 <HAL_RCC_ClockConfig+0x1ae>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8002816: 4b3b ldr r3, [pc, #236] ; (8002904 <HAL_RCC_ClockConfig+0x1bc>)
8002818: 681b ldr r3, [r3, #0]
800281a: f003 0302 and.w r3, r3, #2
800281e: 2b00 cmp r3, #0
8002820: d101 bne.n 8002826 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8002822: 2301 movs r3, #1
8002824: e067 b.n 80028f6 <HAL_RCC_ClockConfig+0x1ae>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
8002826: 4b37 ldr r3, [pc, #220] ; (8002904 <HAL_RCC_ClockConfig+0x1bc>)
8002828: 689b ldr r3, [r3, #8]
800282a: f023 0203 bic.w r2, r3, #3
800282e: 687b ldr r3, [r7, #4]
8002830: 685b ldr r3, [r3, #4]
8002832: 4934 ldr r1, [pc, #208] ; (8002904 <HAL_RCC_ClockConfig+0x1bc>)
8002834: 4313 orrs r3, r2
8002836: 608b str r3, [r1, #8]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002838: f7fe fdba bl 80013b0 <HAL_GetTick>
800283c: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
800283e: e00a b.n 8002856 <HAL_RCC_ClockConfig+0x10e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8002840: f7fe fdb6 bl 80013b0 <HAL_GetTick>
8002844: 4602 mov r2, r0
8002846: 68fb ldr r3, [r7, #12]
8002848: 1ad3 subs r3, r2, r3
800284a: f241 3288 movw r2, #5000 ; 0x1388
800284e: 4293 cmp r3, r2
8002850: d901 bls.n 8002856 <HAL_RCC_ClockConfig+0x10e>
{
return HAL_TIMEOUT;
8002852: 2303 movs r3, #3
8002854: e04f b.n 80028f6 <HAL_RCC_ClockConfig+0x1ae>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8002856: 4b2b ldr r3, [pc, #172] ; (8002904 <HAL_RCC_ClockConfig+0x1bc>)
8002858: 689b ldr r3, [r3, #8]
800285a: f003 020c and.w r2, r3, #12
800285e: 687b ldr r3, [r7, #4]
8002860: 685b ldr r3, [r3, #4]
8002862: 009b lsls r3, r3, #2
8002864: 429a cmp r2, r3
8002866: d1eb bne.n 8002840 <HAL_RCC_ClockConfig+0xf8>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
8002868: 4b25 ldr r3, [pc, #148] ; (8002900 <HAL_RCC_ClockConfig+0x1b8>)
800286a: 681b ldr r3, [r3, #0]
800286c: f003 030f and.w r3, r3, #15
8002870: 683a ldr r2, [r7, #0]
8002872: 429a cmp r2, r3
8002874: d20c bcs.n 8002890 <HAL_RCC_ClockConfig+0x148>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8002876: 4b22 ldr r3, [pc, #136] ; (8002900 <HAL_RCC_ClockConfig+0x1b8>)
8002878: 683a ldr r2, [r7, #0]
800287a: b2d2 uxtb r2, r2
800287c: 701a strb r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
800287e: 4b20 ldr r3, [pc, #128] ; (8002900 <HAL_RCC_ClockConfig+0x1b8>)
8002880: 681b ldr r3, [r3, #0]
8002882: f003 030f and.w r3, r3, #15
8002886: 683a ldr r2, [r7, #0]
8002888: 429a cmp r2, r3
800288a: d001 beq.n 8002890 <HAL_RCC_ClockConfig+0x148>
{
return HAL_ERROR;
800288c: 2301 movs r3, #1
800288e: e032 b.n 80028f6 <HAL_RCC_ClockConfig+0x1ae>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8002890: 687b ldr r3, [r7, #4]
8002892: 681b ldr r3, [r3, #0]
8002894: f003 0304 and.w r3, r3, #4
8002898: 2b00 cmp r3, #0
800289a: d008 beq.n 80028ae <HAL_RCC_ClockConfig+0x166>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
800289c: 4b19 ldr r3, [pc, #100] ; (8002904 <HAL_RCC_ClockConfig+0x1bc>)
800289e: 689b ldr r3, [r3, #8]
80028a0: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00
80028a4: 687b ldr r3, [r7, #4]
80028a6: 68db ldr r3, [r3, #12]
80028a8: 4916 ldr r1, [pc, #88] ; (8002904 <HAL_RCC_ClockConfig+0x1bc>)
80028aa: 4313 orrs r3, r2
80028ac: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
80028ae: 687b ldr r3, [r7, #4]
80028b0: 681b ldr r3, [r3, #0]
80028b2: f003 0308 and.w r3, r3, #8
80028b6: 2b00 cmp r3, #0
80028b8: d009 beq.n 80028ce <HAL_RCC_ClockConfig+0x186>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
80028ba: 4b12 ldr r3, [pc, #72] ; (8002904 <HAL_RCC_ClockConfig+0x1bc>)
80028bc: 689b ldr r3, [r3, #8]
80028be: f423 4260 bic.w r2, r3, #57344 ; 0xe000
80028c2: 687b ldr r3, [r7, #4]
80028c4: 691b ldr r3, [r3, #16]
80028c6: 00db lsls r3, r3, #3
80028c8: 490e ldr r1, [pc, #56] ; (8002904 <HAL_RCC_ClockConfig+0x1bc>)
80028ca: 4313 orrs r3, r2
80028cc: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
80028ce: f000 f821 bl 8002914 <HAL_RCC_GetSysClockFreq>
80028d2: 4602 mov r2, r0
80028d4: 4b0b ldr r3, [pc, #44] ; (8002904 <HAL_RCC_ClockConfig+0x1bc>)
80028d6: 689b ldr r3, [r3, #8]
80028d8: 091b lsrs r3, r3, #4
80028da: f003 030f and.w r3, r3, #15
80028de: 490a ldr r1, [pc, #40] ; (8002908 <HAL_RCC_ClockConfig+0x1c0>)
80028e0: 5ccb ldrb r3, [r1, r3]
80028e2: fa22 f303 lsr.w r3, r2, r3
80028e6: 4a09 ldr r2, [pc, #36] ; (800290c <HAL_RCC_ClockConfig+0x1c4>)
80028e8: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings */
HAL_InitTick(uwTickPrio);
80028ea: 4b09 ldr r3, [pc, #36] ; (8002910 <HAL_RCC_ClockConfig+0x1c8>)
80028ec: 681b ldr r3, [r3, #0]
80028ee: 4618 mov r0, r3
80028f0: f7fe fd1a bl 8001328 <HAL_InitTick>
return HAL_OK;
80028f4: 2300 movs r3, #0
}
80028f6: 4618 mov r0, r3
80028f8: 3710 adds r7, #16
80028fa: 46bd mov sp, r7
80028fc: bd80 pop {r7, pc}
80028fe: bf00 nop
8002900: 40023c00 .word 0x40023c00
8002904: 40023800 .word 0x40023800
8002908: 08003c68 .word 0x08003c68
800290c: 200006b8 .word 0x200006b8
8002910: 200006bc .word 0x200006bc
08002914 <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
__weak uint32_t HAL_RCC_GetSysClockFreq(void)
{
8002914: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
8002918: b094 sub sp, #80 ; 0x50
800291a: af00 add r7, sp, #0
uint32_t pllm = 0U;
800291c: 2300 movs r3, #0
800291e: 647b str r3, [r7, #68] ; 0x44
uint32_t pllvco = 0U;
8002920: 2300 movs r3, #0
8002922: 64fb str r3, [r7, #76] ; 0x4c
uint32_t pllp = 0U;
8002924: 2300 movs r3, #0
8002926: 643b str r3, [r7, #64] ; 0x40
uint32_t sysclockfreq = 0U;
8002928: 2300 movs r3, #0
800292a: 64bb str r3, [r7, #72] ; 0x48
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
800292c: 4b79 ldr r3, [pc, #484] ; (8002b14 <HAL_RCC_GetSysClockFreq+0x200>)
800292e: 689b ldr r3, [r3, #8]
8002930: f003 030c and.w r3, r3, #12
8002934: 2b08 cmp r3, #8
8002936: d00d beq.n 8002954 <HAL_RCC_GetSysClockFreq+0x40>
8002938: 2b08 cmp r3, #8
800293a: f200 80e1 bhi.w 8002b00 <HAL_RCC_GetSysClockFreq+0x1ec>
800293e: 2b00 cmp r3, #0
8002940: d002 beq.n 8002948 <HAL_RCC_GetSysClockFreq+0x34>
8002942: 2b04 cmp r3, #4
8002944: d003 beq.n 800294e <HAL_RCC_GetSysClockFreq+0x3a>
8002946: e0db b.n 8002b00 <HAL_RCC_GetSysClockFreq+0x1ec>
{
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
{
sysclockfreq = HSI_VALUE;
8002948: 4b73 ldr r3, [pc, #460] ; (8002b18 <HAL_RCC_GetSysClockFreq+0x204>)
800294a: 64bb str r3, [r7, #72] ; 0x48
break;
800294c: e0db b.n 8002b06 <HAL_RCC_GetSysClockFreq+0x1f2>
}
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
{
sysclockfreq = HSE_VALUE;
800294e: 4b73 ldr r3, [pc, #460] ; (8002b1c <HAL_RCC_GetSysClockFreq+0x208>)
8002950: 64bb str r3, [r7, #72] ; 0x48
break;
8002952: e0d8 b.n 8002b06 <HAL_RCC_GetSysClockFreq+0x1f2>
}
case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */
{
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
SYSCLK = PLL_VCO / PLLP */
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
8002954: 4b6f ldr r3, [pc, #444] ; (8002b14 <HAL_RCC_GetSysClockFreq+0x200>)
8002956: 685b ldr r3, [r3, #4]
8002958: f003 033f and.w r3, r3, #63 ; 0x3f
800295c: 647b str r3, [r7, #68] ; 0x44
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
800295e: 4b6d ldr r3, [pc, #436] ; (8002b14 <HAL_RCC_GetSysClockFreq+0x200>)
8002960: 685b ldr r3, [r3, #4]
8002962: f403 0380 and.w r3, r3, #4194304 ; 0x400000
8002966: 2b00 cmp r3, #0
8002968: d063 beq.n 8002a32 <HAL_RCC_GetSysClockFreq+0x11e>
{
/* HSE used as PLL clock source */
pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
800296a: 4b6a ldr r3, [pc, #424] ; (8002b14 <HAL_RCC_GetSysClockFreq+0x200>)
800296c: 685b ldr r3, [r3, #4]
800296e: 099b lsrs r3, r3, #6
8002970: 2200 movs r2, #0
8002972: 63bb str r3, [r7, #56] ; 0x38
8002974: 63fa str r2, [r7, #60] ; 0x3c
8002976: 6bbb ldr r3, [r7, #56] ; 0x38
8002978: f3c3 0308 ubfx r3, r3, #0, #9
800297c: 633b str r3, [r7, #48] ; 0x30
800297e: 2300 movs r3, #0
8002980: 637b str r3, [r7, #52] ; 0x34
8002982: e9d7 450c ldrd r4, r5, [r7, #48] ; 0x30
8002986: 4622 mov r2, r4
8002988: 462b mov r3, r5
800298a: f04f 0000 mov.w r0, #0
800298e: f04f 0100 mov.w r1, #0
8002992: 0159 lsls r1, r3, #5
8002994: ea41 61d2 orr.w r1, r1, r2, lsr #27
8002998: 0150 lsls r0, r2, #5
800299a: 4602 mov r2, r0
800299c: 460b mov r3, r1
800299e: 4621 mov r1, r4
80029a0: 1a51 subs r1, r2, r1
80029a2: 6139 str r1, [r7, #16]
80029a4: 4629 mov r1, r5
80029a6: eb63 0301 sbc.w r3, r3, r1
80029aa: 617b str r3, [r7, #20]
80029ac: f04f 0200 mov.w r2, #0
80029b0: f04f 0300 mov.w r3, #0
80029b4: e9d7 ab04 ldrd sl, fp, [r7, #16]
80029b8: 4659 mov r1, fp
80029ba: 018b lsls r3, r1, #6
80029bc: 4651 mov r1, sl
80029be: ea43 6391 orr.w r3, r3, r1, lsr #26
80029c2: 4651 mov r1, sl
80029c4: 018a lsls r2, r1, #6
80029c6: 4651 mov r1, sl
80029c8: ebb2 0801 subs.w r8, r2, r1
80029cc: 4659 mov r1, fp
80029ce: eb63 0901 sbc.w r9, r3, r1
80029d2: f04f 0200 mov.w r2, #0
80029d6: f04f 0300 mov.w r3, #0
80029da: ea4f 03c9 mov.w r3, r9, lsl #3
80029de: ea43 7358 orr.w r3, r3, r8, lsr #29
80029e2: ea4f 02c8 mov.w r2, r8, lsl #3
80029e6: 4690 mov r8, r2
80029e8: 4699 mov r9, r3
80029ea: 4623 mov r3, r4
80029ec: eb18 0303 adds.w r3, r8, r3
80029f0: 60bb str r3, [r7, #8]
80029f2: 462b mov r3, r5
80029f4: eb49 0303 adc.w r3, r9, r3
80029f8: 60fb str r3, [r7, #12]
80029fa: f04f 0200 mov.w r2, #0
80029fe: f04f 0300 mov.w r3, #0
8002a02: e9d7 4502 ldrd r4, r5, [r7, #8]
8002a06: 4629 mov r1, r5
8002a08: 024b lsls r3, r1, #9
8002a0a: 4621 mov r1, r4
8002a0c: ea43 53d1 orr.w r3, r3, r1, lsr #23
8002a10: 4621 mov r1, r4
8002a12: 024a lsls r2, r1, #9
8002a14: 4610 mov r0, r2
8002a16: 4619 mov r1, r3
8002a18: 6c7b ldr r3, [r7, #68] ; 0x44
8002a1a: 2200 movs r2, #0
8002a1c: 62bb str r3, [r7, #40] ; 0x28
8002a1e: 62fa str r2, [r7, #44] ; 0x2c
8002a20: e9d7 230a ldrd r2, r3, [r7, #40] ; 0x28
8002a24: f7fd fbea bl 80001fc <__aeabi_uldivmod>
8002a28: 4602 mov r2, r0
8002a2a: 460b mov r3, r1
8002a2c: 4613 mov r3, r2
8002a2e: 64fb str r3, [r7, #76] ; 0x4c
8002a30: e058 b.n 8002ae4 <HAL_RCC_GetSysClockFreq+0x1d0>
}
else
{
/* HSI used as PLL clock source */
pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
8002a32: 4b38 ldr r3, [pc, #224] ; (8002b14 <HAL_RCC_GetSysClockFreq+0x200>)
8002a34: 685b ldr r3, [r3, #4]
8002a36: 099b lsrs r3, r3, #6
8002a38: 2200 movs r2, #0
8002a3a: 4618 mov r0, r3
8002a3c: 4611 mov r1, r2
8002a3e: f3c0 0308 ubfx r3, r0, #0, #9
8002a42: 623b str r3, [r7, #32]
8002a44: 2300 movs r3, #0
8002a46: 627b str r3, [r7, #36] ; 0x24
8002a48: e9d7 8908 ldrd r8, r9, [r7, #32]
8002a4c: 4642 mov r2, r8
8002a4e: 464b mov r3, r9
8002a50: f04f 0000 mov.w r0, #0
8002a54: f04f 0100 mov.w r1, #0
8002a58: 0159 lsls r1, r3, #5
8002a5a: ea41 61d2 orr.w r1, r1, r2, lsr #27
8002a5e: 0150 lsls r0, r2, #5
8002a60: 4602 mov r2, r0
8002a62: 460b mov r3, r1
8002a64: 4641 mov r1, r8
8002a66: ebb2 0a01 subs.w sl, r2, r1
8002a6a: 4649 mov r1, r9
8002a6c: eb63 0b01 sbc.w fp, r3, r1
8002a70: f04f 0200 mov.w r2, #0
8002a74: f04f 0300 mov.w r3, #0
8002a78: ea4f 138b mov.w r3, fp, lsl #6
8002a7c: ea43 639a orr.w r3, r3, sl, lsr #26
8002a80: ea4f 128a mov.w r2, sl, lsl #6
8002a84: ebb2 040a subs.w r4, r2, sl
8002a88: eb63 050b sbc.w r5, r3, fp
8002a8c: f04f 0200 mov.w r2, #0
8002a90: f04f 0300 mov.w r3, #0
8002a94: 00eb lsls r3, r5, #3
8002a96: ea43 7354 orr.w r3, r3, r4, lsr #29
8002a9a: 00e2 lsls r2, r4, #3
8002a9c: 4614 mov r4, r2
8002a9e: 461d mov r5, r3
8002aa0: 4643 mov r3, r8
8002aa2: 18e3 adds r3, r4, r3
8002aa4: 603b str r3, [r7, #0]
8002aa6: 464b mov r3, r9
8002aa8: eb45 0303 adc.w r3, r5, r3
8002aac: 607b str r3, [r7, #4]
8002aae: f04f 0200 mov.w r2, #0
8002ab2: f04f 0300 mov.w r3, #0
8002ab6: e9d7 4500 ldrd r4, r5, [r7]
8002aba: 4629 mov r1, r5
8002abc: 028b lsls r3, r1, #10
8002abe: 4621 mov r1, r4
8002ac0: ea43 5391 orr.w r3, r3, r1, lsr #22
8002ac4: 4621 mov r1, r4
8002ac6: 028a lsls r2, r1, #10
8002ac8: 4610 mov r0, r2
8002aca: 4619 mov r1, r3
8002acc: 6c7b ldr r3, [r7, #68] ; 0x44
8002ace: 2200 movs r2, #0
8002ad0: 61bb str r3, [r7, #24]
8002ad2: 61fa str r2, [r7, #28]
8002ad4: e9d7 2306 ldrd r2, r3, [r7, #24]
8002ad8: f7fd fb90 bl 80001fc <__aeabi_uldivmod>
8002adc: 4602 mov r2, r0
8002ade: 460b mov r3, r1
8002ae0: 4613 mov r3, r2
8002ae2: 64fb str r3, [r7, #76] ; 0x4c
}
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) * 2U);
8002ae4: 4b0b ldr r3, [pc, #44] ; (8002b14 <HAL_RCC_GetSysClockFreq+0x200>)
8002ae6: 685b ldr r3, [r3, #4]
8002ae8: 0c1b lsrs r3, r3, #16
8002aea: f003 0303 and.w r3, r3, #3
8002aee: 3301 adds r3, #1
8002af0: 005b lsls r3, r3, #1
8002af2: 643b str r3, [r7, #64] ; 0x40
sysclockfreq = pllvco / pllp;
8002af4: 6cfa ldr r2, [r7, #76] ; 0x4c
8002af6: 6c3b ldr r3, [r7, #64] ; 0x40
8002af8: fbb2 f3f3 udiv r3, r2, r3
8002afc: 64bb str r3, [r7, #72] ; 0x48
break;
8002afe: e002 b.n 8002b06 <HAL_RCC_GetSysClockFreq+0x1f2>
}
default:
{
sysclockfreq = HSI_VALUE;
8002b00: 4b05 ldr r3, [pc, #20] ; (8002b18 <HAL_RCC_GetSysClockFreq+0x204>)
8002b02: 64bb str r3, [r7, #72] ; 0x48
break;
8002b04: bf00 nop
}
}
return sysclockfreq;
8002b06: 6cbb ldr r3, [r7, #72] ; 0x48
}
8002b08: 4618 mov r0, r3
8002b0a: 3750 adds r7, #80 ; 0x50
8002b0c: 46bd mov sp, r7
8002b0e: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
8002b12: bf00 nop
8002b14: 40023800 .word 0x40023800
8002b18: 00f42400 .word 0x00f42400
8002b1c: 007a1200 .word 0x007a1200
08002b20 <HAL_RCC_GetHCLKFreq>:
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* and updated within this function
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
8002b20: b480 push {r7}
8002b22: af00 add r7, sp, #0
return SystemCoreClock;
8002b24: 4b03 ldr r3, [pc, #12] ; (8002b34 <HAL_RCC_GetHCLKFreq+0x14>)
8002b26: 681b ldr r3, [r3, #0]
}
8002b28: 4618 mov r0, r3
8002b2a: 46bd mov sp, r7
8002b2c: f85d 7b04 ldr.w r7, [sp], #4
8002b30: 4770 bx lr
8002b32: bf00 nop
8002b34: 200006b8 .word 0x200006b8
08002b38 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
8002b38: b580 push {r7, lr}
8002b3a: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
8002b3c: f7ff fff0 bl 8002b20 <HAL_RCC_GetHCLKFreq>
8002b40: 4602 mov r2, r0
8002b42: 4b05 ldr r3, [pc, #20] ; (8002b58 <HAL_RCC_GetPCLK1Freq+0x20>)
8002b44: 689b ldr r3, [r3, #8]
8002b46: 0a9b lsrs r3, r3, #10
8002b48: f003 0307 and.w r3, r3, #7
8002b4c: 4903 ldr r1, [pc, #12] ; (8002b5c <HAL_RCC_GetPCLK1Freq+0x24>)
8002b4e: 5ccb ldrb r3, [r1, r3]
8002b50: fa22 f303 lsr.w r3, r2, r3
}
8002b54: 4618 mov r0, r3
8002b56: bd80 pop {r7, pc}
8002b58: 40023800 .word 0x40023800
8002b5c: 08003c78 .word 0x08003c78
08002b60 <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
8002b60: b580 push {r7, lr}
8002b62: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
8002b64: f7ff ffdc bl 8002b20 <HAL_RCC_GetHCLKFreq>
8002b68: 4602 mov r2, r0
8002b6a: 4b05 ldr r3, [pc, #20] ; (8002b80 <HAL_RCC_GetPCLK2Freq+0x20>)
8002b6c: 689b ldr r3, [r3, #8]
8002b6e: 0b5b lsrs r3, r3, #13
8002b70: f003 0307 and.w r3, r3, #7
8002b74: 4903 ldr r1, [pc, #12] ; (8002b84 <HAL_RCC_GetPCLK2Freq+0x24>)
8002b76: 5ccb ldrb r3, [r1, r3]
8002b78: fa22 f303 lsr.w r3, r2, r3
}
8002b7c: 4618 mov r0, r3
8002b7e: bd80 pop {r7, pc}
8002b80: 40023800 .word 0x40023800
8002b84: 08003c78 .word 0x08003c78
08002b88 <HAL_RNG_Init>:
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
{
8002b88: b580 push {r7, lr}
8002b8a: b082 sub sp, #8
8002b8c: af00 add r7, sp, #0
8002b8e: 6078 str r0, [r7, #4]
/* Check the RNG handle allocation */
if (hrng == NULL)
8002b90: 687b ldr r3, [r7, #4]
8002b92: 2b00 cmp r3, #0
8002b94: d101 bne.n 8002b9a <HAL_RNG_Init+0x12>
{
return HAL_ERROR;
8002b96: 2301 movs r3, #1
8002b98: e01c b.n 8002bd4 <HAL_RNG_Init+0x4c>
/* Init the low level hardware */
hrng->MspInitCallback(hrng);
}
#else
if (hrng->State == HAL_RNG_STATE_RESET)
8002b9a: 687b ldr r3, [r7, #4]
8002b9c: 795b ldrb r3, [r3, #5]
8002b9e: b2db uxtb r3, r3
8002ba0: 2b00 cmp r3, #0
8002ba2: d105 bne.n 8002bb0 <HAL_RNG_Init+0x28>
{
/* Allocate lock resource and initialize it */
hrng->Lock = HAL_UNLOCKED;
8002ba4: 687b ldr r3, [r7, #4]
8002ba6: 2200 movs r2, #0
8002ba8: 711a strb r2, [r3, #4]
/* Init the low level hardware */
HAL_RNG_MspInit(hrng);
8002baa: 6878 ldr r0, [r7, #4]
8002bac: f7fe fa38 bl 8001020 <HAL_RNG_MspInit>
}
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_BUSY;
8002bb0: 687b ldr r3, [r7, #4]
8002bb2: 2202 movs r2, #2
8002bb4: 715a strb r2, [r3, #5]
/* Enable the RNG Peripheral */
__HAL_RNG_ENABLE(hrng);
8002bb6: 687b ldr r3, [r7, #4]
8002bb8: 681b ldr r3, [r3, #0]
8002bba: 681a ldr r2, [r3, #0]
8002bbc: 687b ldr r3, [r7, #4]
8002bbe: 681b ldr r3, [r3, #0]
8002bc0: f042 0204 orr.w r2, r2, #4
8002bc4: 601a str r2, [r3, #0]
/* Initialize the RNG state */
hrng->State = HAL_RNG_STATE_READY;
8002bc6: 687b ldr r3, [r7, #4]
8002bc8: 2201 movs r2, #1
8002bca: 715a strb r2, [r3, #5]
/* Initialise the error code */
hrng->ErrorCode = HAL_RNG_ERROR_NONE;
8002bcc: 687b ldr r3, [r7, #4]
8002bce: 2200 movs r2, #0
8002bd0: 609a str r2, [r3, #8]
/* Return function status */
return HAL_OK;
8002bd2: 2300 movs r3, #0
}
8002bd4: 4618 mov r0, r3
8002bd6: 3708 adds r7, #8
8002bd8: 46bd mov sp, r7
8002bda: bd80 pop {r7, pc}
08002bdc <HAL_UART_Init>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
8002bdc: b580 push {r7, lr}
8002bde: b082 sub sp, #8
8002be0: af00 add r7, sp, #0
8002be2: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
8002be4: 687b ldr r3, [r7, #4]
8002be6: 2b00 cmp r3, #0
8002be8: d101 bne.n 8002bee <HAL_UART_Init+0x12>
{
return HAL_ERROR;
8002bea: 2301 movs r3, #1
8002bec: e042 b.n 8002c74 <HAL_UART_Init+0x98>
assert_param(IS_UART_INSTANCE(huart->Instance));
}
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
if (huart->gState == HAL_UART_STATE_RESET)
8002bee: 687b ldr r3, [r7, #4]
8002bf0: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
8002bf4: b2db uxtb r3, r3
8002bf6: 2b00 cmp r3, #0
8002bf8: d106 bne.n 8002c08 <HAL_UART_Init+0x2c>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
8002bfa: 687b ldr r3, [r7, #4]
8002bfc: 2200 movs r2, #0
8002bfe: f883 2040 strb.w r2, [r3, #64] ; 0x40
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
8002c02: 6878 ldr r0, [r7, #4]
8002c04: f7fe fa2e bl 8001064 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
8002c08: 687b ldr r3, [r7, #4]
8002c0a: 2224 movs r2, #36 ; 0x24
8002c0c: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Disable the peripheral */
__HAL_UART_DISABLE(huart);
8002c10: 687b ldr r3, [r7, #4]
8002c12: 681b ldr r3, [r3, #0]
8002c14: 68da ldr r2, [r3, #12]
8002c16: 687b ldr r3, [r7, #4]
8002c18: 681b ldr r3, [r3, #0]
8002c1a: f422 5200 bic.w r2, r2, #8192 ; 0x2000
8002c1e: 60da str r2, [r3, #12]
/* Set the UART Communication parameters */
UART_SetConfig(huart);
8002c20: 6878 ldr r0, [r7, #4]
8002c22: f000 fa09 bl 8003038 <UART_SetConfig>
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
8002c26: 687b ldr r3, [r7, #4]
8002c28: 681b ldr r3, [r3, #0]
8002c2a: 691a ldr r2, [r3, #16]
8002c2c: 687b ldr r3, [r7, #4]
8002c2e: 681b ldr r3, [r3, #0]
8002c30: f422 4290 bic.w r2, r2, #18432 ; 0x4800
8002c34: 611a str r2, [r3, #16]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
8002c36: 687b ldr r3, [r7, #4]
8002c38: 681b ldr r3, [r3, #0]
8002c3a: 695a ldr r2, [r3, #20]
8002c3c: 687b ldr r3, [r7, #4]
8002c3e: 681b ldr r3, [r3, #0]
8002c40: f022 022a bic.w r2, r2, #42 ; 0x2a
8002c44: 615a str r2, [r3, #20]
/* Enable the peripheral */
__HAL_UART_ENABLE(huart);
8002c46: 687b ldr r3, [r7, #4]
8002c48: 681b ldr r3, [r3, #0]
8002c4a: 68da ldr r2, [r3, #12]
8002c4c: 687b ldr r3, [r7, #4]
8002c4e: 681b ldr r3, [r3, #0]
8002c50: f442 5200 orr.w r2, r2, #8192 ; 0x2000
8002c54: 60da str r2, [r3, #12]
/* Initialize the UART state */
huart->ErrorCode = HAL_UART_ERROR_NONE;
8002c56: 687b ldr r3, [r7, #4]
8002c58: 2200 movs r2, #0
8002c5a: 645a str r2, [r3, #68] ; 0x44
huart->gState = HAL_UART_STATE_READY;
8002c5c: 687b ldr r3, [r7, #4]
8002c5e: 2220 movs r2, #32
8002c60: f883 2041 strb.w r2, [r3, #65] ; 0x41
huart->RxState = HAL_UART_STATE_READY;
8002c64: 687b ldr r3, [r7, #4]
8002c66: 2220 movs r2, #32
8002c68: f883 2042 strb.w r2, [r3, #66] ; 0x42
huart->RxEventType = HAL_UART_RXEVENT_TC;
8002c6c: 687b ldr r3, [r7, #4]
8002c6e: 2200 movs r2, #0
8002c70: 635a str r2, [r3, #52] ; 0x34
return HAL_OK;
8002c72: 2300 movs r3, #0
}
8002c74: 4618 mov r0, r3
8002c76: 3708 adds r7, #8
8002c78: 46bd mov sp, r7
8002c7a: bd80 pop {r7, pc}
08002c7c <HAL_UART_Transmit>:
* @param Size Amount of data elements (u8 or u16) to be sent
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
8002c7c: b580 push {r7, lr}
8002c7e: b08a sub sp, #40 ; 0x28
8002c80: af02 add r7, sp, #8
8002c82: 60f8 str r0, [r7, #12]
8002c84: 60b9 str r1, [r7, #8]
8002c86: 603b str r3, [r7, #0]
8002c88: 4613 mov r3, r2
8002c8a: 80fb strh r3, [r7, #6]
const uint8_t *pdata8bits;
const uint16_t *pdata16bits;
uint32_t tickstart = 0U;
8002c8c: 2300 movs r3, #0
8002c8e: 617b str r3, [r7, #20]
/* Check that a Tx process is not already ongoing */
if (huart->gState == HAL_UART_STATE_READY)
8002c90: 68fb ldr r3, [r7, #12]
8002c92: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
8002c96: b2db uxtb r3, r3
8002c98: 2b20 cmp r3, #32
8002c9a: d175 bne.n 8002d88 <HAL_UART_Transmit+0x10c>
{
if ((pData == NULL) || (Size == 0U))
8002c9c: 68bb ldr r3, [r7, #8]
8002c9e: 2b00 cmp r3, #0
8002ca0: d002 beq.n 8002ca8 <HAL_UART_Transmit+0x2c>
8002ca2: 88fb ldrh r3, [r7, #6]
8002ca4: 2b00 cmp r3, #0
8002ca6: d101 bne.n 8002cac <HAL_UART_Transmit+0x30>
{
return HAL_ERROR;
8002ca8: 2301 movs r3, #1
8002caa: e06e b.n 8002d8a <HAL_UART_Transmit+0x10e>
}
huart->ErrorCode = HAL_UART_ERROR_NONE;
8002cac: 68fb ldr r3, [r7, #12]
8002cae: 2200 movs r2, #0
8002cb0: 645a str r2, [r3, #68] ; 0x44
huart->gState = HAL_UART_STATE_BUSY_TX;
8002cb2: 68fb ldr r3, [r7, #12]
8002cb4: 2221 movs r2, #33 ; 0x21
8002cb6: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
8002cba: f7fe fb79 bl 80013b0 <HAL_GetTick>
8002cbe: 6178 str r0, [r7, #20]
huart->TxXferSize = Size;
8002cc0: 68fb ldr r3, [r7, #12]
8002cc2: 88fa ldrh r2, [r7, #6]
8002cc4: 849a strh r2, [r3, #36] ; 0x24
huart->TxXferCount = Size;
8002cc6: 68fb ldr r3, [r7, #12]
8002cc8: 88fa ldrh r2, [r7, #6]
8002cca: 84da strh r2, [r3, #38] ; 0x26
/* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
8002ccc: 68fb ldr r3, [r7, #12]
8002cce: 689b ldr r3, [r3, #8]
8002cd0: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
8002cd4: d108 bne.n 8002ce8 <HAL_UART_Transmit+0x6c>
8002cd6: 68fb ldr r3, [r7, #12]
8002cd8: 691b ldr r3, [r3, #16]
8002cda: 2b00 cmp r3, #0
8002cdc: d104 bne.n 8002ce8 <HAL_UART_Transmit+0x6c>
{
pdata8bits = NULL;
8002cde: 2300 movs r3, #0
8002ce0: 61fb str r3, [r7, #28]
pdata16bits = (const uint16_t *) pData;
8002ce2: 68bb ldr r3, [r7, #8]
8002ce4: 61bb str r3, [r7, #24]
8002ce6: e003 b.n 8002cf0 <HAL_UART_Transmit+0x74>
}
else
{
pdata8bits = pData;
8002ce8: 68bb ldr r3, [r7, #8]
8002cea: 61fb str r3, [r7, #28]
pdata16bits = NULL;
8002cec: 2300 movs r3, #0
8002cee: 61bb str r3, [r7, #24]
}
while (huart->TxXferCount > 0U)
8002cf0: e02e b.n 8002d50 <HAL_UART_Transmit+0xd4>
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
8002cf2: 683b ldr r3, [r7, #0]
8002cf4: 9300 str r3, [sp, #0]
8002cf6: 697b ldr r3, [r7, #20]
8002cf8: 2200 movs r2, #0
8002cfa: 2180 movs r1, #128 ; 0x80
8002cfc: 68f8 ldr r0, [r7, #12]
8002cfe: f000 f8df bl 8002ec0 <UART_WaitOnFlagUntilTimeout>
8002d02: 4603 mov r3, r0
8002d04: 2b00 cmp r3, #0
8002d06: d005 beq.n 8002d14 <HAL_UART_Transmit+0x98>
{
huart->gState = HAL_UART_STATE_READY;
8002d08: 68fb ldr r3, [r7, #12]
8002d0a: 2220 movs r2, #32
8002d0c: f883 2041 strb.w r2, [r3, #65] ; 0x41
return HAL_TIMEOUT;
8002d10: 2303 movs r3, #3
8002d12: e03a b.n 8002d8a <HAL_UART_Transmit+0x10e>
}
if (pdata8bits == NULL)
8002d14: 69fb ldr r3, [r7, #28]
8002d16: 2b00 cmp r3, #0
8002d18: d10b bne.n 8002d32 <HAL_UART_Transmit+0xb6>
{
huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU);
8002d1a: 69bb ldr r3, [r7, #24]
8002d1c: 881b ldrh r3, [r3, #0]
8002d1e: 461a mov r2, r3
8002d20: 68fb ldr r3, [r7, #12]
8002d22: 681b ldr r3, [r3, #0]
8002d24: f3c2 0208 ubfx r2, r2, #0, #9
8002d28: 605a str r2, [r3, #4]
pdata16bits++;
8002d2a: 69bb ldr r3, [r7, #24]
8002d2c: 3302 adds r3, #2
8002d2e: 61bb str r3, [r7, #24]
8002d30: e007 b.n 8002d42 <HAL_UART_Transmit+0xc6>
}
else
{
huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU);
8002d32: 69fb ldr r3, [r7, #28]
8002d34: 781a ldrb r2, [r3, #0]
8002d36: 68fb ldr r3, [r7, #12]
8002d38: 681b ldr r3, [r3, #0]
8002d3a: 605a str r2, [r3, #4]
pdata8bits++;
8002d3c: 69fb ldr r3, [r7, #28]
8002d3e: 3301 adds r3, #1
8002d40: 61fb str r3, [r7, #28]
}
huart->TxXferCount--;
8002d42: 68fb ldr r3, [r7, #12]
8002d44: 8cdb ldrh r3, [r3, #38] ; 0x26
8002d46: b29b uxth r3, r3
8002d48: 3b01 subs r3, #1
8002d4a: b29a uxth r2, r3
8002d4c: 68fb ldr r3, [r7, #12]
8002d4e: 84da strh r2, [r3, #38] ; 0x26
while (huart->TxXferCount > 0U)
8002d50: 68fb ldr r3, [r7, #12]
8002d52: 8cdb ldrh r3, [r3, #38] ; 0x26
8002d54: b29b uxth r3, r3
8002d56: 2b00 cmp r3, #0
8002d58: d1cb bne.n 8002cf2 <HAL_UART_Transmit+0x76>
}
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
8002d5a: 683b ldr r3, [r7, #0]
8002d5c: 9300 str r3, [sp, #0]
8002d5e: 697b ldr r3, [r7, #20]
8002d60: 2200 movs r2, #0
8002d62: 2140 movs r1, #64 ; 0x40
8002d64: 68f8 ldr r0, [r7, #12]
8002d66: f000 f8ab bl 8002ec0 <UART_WaitOnFlagUntilTimeout>
8002d6a: 4603 mov r3, r0
8002d6c: 2b00 cmp r3, #0
8002d6e: d005 beq.n 8002d7c <HAL_UART_Transmit+0x100>
{
huart->gState = HAL_UART_STATE_READY;
8002d70: 68fb ldr r3, [r7, #12]
8002d72: 2220 movs r2, #32
8002d74: f883 2041 strb.w r2, [r3, #65] ; 0x41
return HAL_TIMEOUT;
8002d78: 2303 movs r3, #3
8002d7a: e006 b.n 8002d8a <HAL_UART_Transmit+0x10e>
}
/* At end of Tx process, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
8002d7c: 68fb ldr r3, [r7, #12]
8002d7e: 2220 movs r2, #32
8002d80: f883 2041 strb.w r2, [r3, #65] ; 0x41
return HAL_OK;
8002d84: 2300 movs r3, #0
8002d86: e000 b.n 8002d8a <HAL_UART_Transmit+0x10e>
}
else
{
return HAL_BUSY;
8002d88: 2302 movs r3, #2
}
}
8002d8a: 4618 mov r0, r3
8002d8c: 3720 adds r7, #32
8002d8e: 46bd mov sp, r7
8002d90: bd80 pop {r7, pc}
08002d92 <HAL_UART_Receive>:
* @param Size Amount of data elements (u8 or u16) to be received.
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
8002d92: b580 push {r7, lr}
8002d94: b08a sub sp, #40 ; 0x28
8002d96: af02 add r7, sp, #8
8002d98: 60f8 str r0, [r7, #12]
8002d9a: 60b9 str r1, [r7, #8]
8002d9c: 603b str r3, [r7, #0]
8002d9e: 4613 mov r3, r2
8002da0: 80fb strh r3, [r7, #6]
uint8_t *pdata8bits;
uint16_t *pdata16bits;
uint32_t tickstart = 0U;
8002da2: 2300 movs r3, #0
8002da4: 617b str r3, [r7, #20]
/* Check that a Rx process is not already ongoing */
if (huart->RxState == HAL_UART_STATE_READY)
8002da6: 68fb ldr r3, [r7, #12]
8002da8: f893 3042 ldrb.w r3, [r3, #66] ; 0x42
8002dac: b2db uxtb r3, r3
8002dae: 2b20 cmp r3, #32
8002db0: f040 8081 bne.w 8002eb6 <HAL_UART_Receive+0x124>
{
if ((pData == NULL) || (Size == 0U))
8002db4: 68bb ldr r3, [r7, #8]
8002db6: 2b00 cmp r3, #0
8002db8: d002 beq.n 8002dc0 <HAL_UART_Receive+0x2e>
8002dba: 88fb ldrh r3, [r7, #6]
8002dbc: 2b00 cmp r3, #0
8002dbe: d101 bne.n 8002dc4 <HAL_UART_Receive+0x32>
{
return HAL_ERROR;
8002dc0: 2301 movs r3, #1
8002dc2: e079 b.n 8002eb8 <HAL_UART_Receive+0x126>
}
huart->ErrorCode = HAL_UART_ERROR_NONE;
8002dc4: 68fb ldr r3, [r7, #12]
8002dc6: 2200 movs r2, #0
8002dc8: 645a str r2, [r3, #68] ; 0x44
huart->RxState = HAL_UART_STATE_BUSY_RX;
8002dca: 68fb ldr r3, [r7, #12]
8002dcc: 2222 movs r2, #34 ; 0x22
8002dce: f883 2042 strb.w r2, [r3, #66] ; 0x42
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8002dd2: 68fb ldr r3, [r7, #12]
8002dd4: 2200 movs r2, #0
8002dd6: 631a str r2, [r3, #48] ; 0x30
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
8002dd8: f7fe faea bl 80013b0 <HAL_GetTick>
8002ddc: 6178 str r0, [r7, #20]
huart->RxXferSize = Size;
8002dde: 68fb ldr r3, [r7, #12]
8002de0: 88fa ldrh r2, [r7, #6]
8002de2: 859a strh r2, [r3, #44] ; 0x2c
huart->RxXferCount = Size;
8002de4: 68fb ldr r3, [r7, #12]
8002de6: 88fa ldrh r2, [r7, #6]
8002de8: 85da strh r2, [r3, #46] ; 0x2e
/* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
8002dea: 68fb ldr r3, [r7, #12]
8002dec: 689b ldr r3, [r3, #8]
8002dee: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
8002df2: d108 bne.n 8002e06 <HAL_UART_Receive+0x74>
8002df4: 68fb ldr r3, [r7, #12]
8002df6: 691b ldr r3, [r3, #16]
8002df8: 2b00 cmp r3, #0
8002dfa: d104 bne.n 8002e06 <HAL_UART_Receive+0x74>
{
pdata8bits = NULL;
8002dfc: 2300 movs r3, #0
8002dfe: 61fb str r3, [r7, #28]
pdata16bits = (uint16_t *) pData;
8002e00: 68bb ldr r3, [r7, #8]
8002e02: 61bb str r3, [r7, #24]
8002e04: e003 b.n 8002e0e <HAL_UART_Receive+0x7c>
}
else
{
pdata8bits = pData;
8002e06: 68bb ldr r3, [r7, #8]
8002e08: 61fb str r3, [r7, #28]
pdata16bits = NULL;
8002e0a: 2300 movs r3, #0
8002e0c: 61bb str r3, [r7, #24]
}
/* Check the remain data to be received */
while (huart->RxXferCount > 0U)
8002e0e: e047 b.n 8002ea0 <HAL_UART_Receive+0x10e>
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
8002e10: 683b ldr r3, [r7, #0]
8002e12: 9300 str r3, [sp, #0]
8002e14: 697b ldr r3, [r7, #20]
8002e16: 2200 movs r2, #0
8002e18: 2120 movs r1, #32
8002e1a: 68f8 ldr r0, [r7, #12]
8002e1c: f000 f850 bl 8002ec0 <UART_WaitOnFlagUntilTimeout>
8002e20: 4603 mov r3, r0
8002e22: 2b00 cmp r3, #0
8002e24: d005 beq.n 8002e32 <HAL_UART_Receive+0xa0>
{
huart->RxState = HAL_UART_STATE_READY;
8002e26: 68fb ldr r3, [r7, #12]
8002e28: 2220 movs r2, #32
8002e2a: f883 2042 strb.w r2, [r3, #66] ; 0x42
return HAL_TIMEOUT;
8002e2e: 2303 movs r3, #3
8002e30: e042 b.n 8002eb8 <HAL_UART_Receive+0x126>
}
if (pdata8bits == NULL)
8002e32: 69fb ldr r3, [r7, #28]
8002e34: 2b00 cmp r3, #0
8002e36: d10c bne.n 8002e52 <HAL_UART_Receive+0xc0>
{
*pdata16bits = (uint16_t)(huart->Instance->DR & 0x01FF);
8002e38: 68fb ldr r3, [r7, #12]
8002e3a: 681b ldr r3, [r3, #0]
8002e3c: 685b ldr r3, [r3, #4]
8002e3e: b29b uxth r3, r3
8002e40: f3c3 0308 ubfx r3, r3, #0, #9
8002e44: b29a uxth r2, r3
8002e46: 69bb ldr r3, [r7, #24]
8002e48: 801a strh r2, [r3, #0]
pdata16bits++;
8002e4a: 69bb ldr r3, [r7, #24]
8002e4c: 3302 adds r3, #2
8002e4e: 61bb str r3, [r7, #24]
8002e50: e01f b.n 8002e92 <HAL_UART_Receive+0x100>
}
else
{
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE)))
8002e52: 68fb ldr r3, [r7, #12]
8002e54: 689b ldr r3, [r3, #8]
8002e56: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
8002e5a: d007 beq.n 8002e6c <HAL_UART_Receive+0xda>
8002e5c: 68fb ldr r3, [r7, #12]
8002e5e: 689b ldr r3, [r3, #8]
8002e60: 2b00 cmp r3, #0
8002e62: d10a bne.n 8002e7a <HAL_UART_Receive+0xe8>
8002e64: 68fb ldr r3, [r7, #12]
8002e66: 691b ldr r3, [r3, #16]
8002e68: 2b00 cmp r3, #0
8002e6a: d106 bne.n 8002e7a <HAL_UART_Receive+0xe8>
{
*pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
8002e6c: 68fb ldr r3, [r7, #12]
8002e6e: 681b ldr r3, [r3, #0]
8002e70: 685b ldr r3, [r3, #4]
8002e72: b2da uxtb r2, r3
8002e74: 69fb ldr r3, [r7, #28]
8002e76: 701a strb r2, [r3, #0]
8002e78: e008 b.n 8002e8c <HAL_UART_Receive+0xfa>
}
else
{
*pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
8002e7a: 68fb ldr r3, [r7, #12]
8002e7c: 681b ldr r3, [r3, #0]
8002e7e: 685b ldr r3, [r3, #4]
8002e80: b2db uxtb r3, r3
8002e82: f003 037f and.w r3, r3, #127 ; 0x7f
8002e86: b2da uxtb r2, r3
8002e88: 69fb ldr r3, [r7, #28]
8002e8a: 701a strb r2, [r3, #0]
}
pdata8bits++;
8002e8c: 69fb ldr r3, [r7, #28]
8002e8e: 3301 adds r3, #1
8002e90: 61fb str r3, [r7, #28]
}
huart->RxXferCount--;
8002e92: 68fb ldr r3, [r7, #12]
8002e94: 8ddb ldrh r3, [r3, #46] ; 0x2e
8002e96: b29b uxth r3, r3
8002e98: 3b01 subs r3, #1
8002e9a: b29a uxth r2, r3
8002e9c: 68fb ldr r3, [r7, #12]
8002e9e: 85da strh r2, [r3, #46] ; 0x2e
while (huart->RxXferCount > 0U)
8002ea0: 68fb ldr r3, [r7, #12]
8002ea2: 8ddb ldrh r3, [r3, #46] ; 0x2e
8002ea4: b29b uxth r3, r3
8002ea6: 2b00 cmp r3, #0
8002ea8: d1b2 bne.n 8002e10 <HAL_UART_Receive+0x7e>
}
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8002eaa: 68fb ldr r3, [r7, #12]
8002eac: 2220 movs r2, #32
8002eae: f883 2042 strb.w r2, [r3, #66] ; 0x42
return HAL_OK;
8002eb2: 2300 movs r3, #0
8002eb4: e000 b.n 8002eb8 <HAL_UART_Receive+0x126>
}
else
{
return HAL_BUSY;
8002eb6: 2302 movs r3, #2
}
}
8002eb8: 4618 mov r0, r3
8002eba: 3720 adds r7, #32
8002ebc: 46bd mov sp, r7
8002ebe: bd80 pop {r7, pc}
08002ec0 <UART_WaitOnFlagUntilTimeout>:
* @param Timeout Timeout duration
* @retval HAL status
*/
static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
8002ec0: b580 push {r7, lr}
8002ec2: b086 sub sp, #24
8002ec4: af00 add r7, sp, #0
8002ec6: 60f8 str r0, [r7, #12]
8002ec8: 60b9 str r1, [r7, #8]
8002eca: 603b str r3, [r7, #0]
8002ecc: 4613 mov r3, r2
8002ece: 71fb strb r3, [r7, #7]
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
8002ed0: e03b b.n 8002f4a <UART_WaitOnFlagUntilTimeout+0x8a>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8002ed2: 6a3b ldr r3, [r7, #32]
8002ed4: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
8002ed8: d037 beq.n 8002f4a <UART_WaitOnFlagUntilTimeout+0x8a>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8002eda: f7fe fa69 bl 80013b0 <HAL_GetTick>
8002ede: 4602 mov r2, r0
8002ee0: 683b ldr r3, [r7, #0]
8002ee2: 1ad3 subs r3, r2, r3
8002ee4: 6a3a ldr r2, [r7, #32]
8002ee6: 429a cmp r2, r3
8002ee8: d302 bcc.n 8002ef0 <UART_WaitOnFlagUntilTimeout+0x30>
8002eea: 6a3b ldr r3, [r7, #32]
8002eec: 2b00 cmp r3, #0
8002eee: d101 bne.n 8002ef4 <UART_WaitOnFlagUntilTimeout+0x34>
{
return HAL_TIMEOUT;
8002ef0: 2303 movs r3, #3
8002ef2: e03a b.n 8002f6a <UART_WaitOnFlagUntilTimeout+0xaa>
}
if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
8002ef4: 68fb ldr r3, [r7, #12]
8002ef6: 681b ldr r3, [r3, #0]
8002ef8: 68db ldr r3, [r3, #12]
8002efa: f003 0304 and.w r3, r3, #4
8002efe: 2b00 cmp r3, #0
8002f00: d023 beq.n 8002f4a <UART_WaitOnFlagUntilTimeout+0x8a>
8002f02: 68bb ldr r3, [r7, #8]
8002f04: 2b80 cmp r3, #128 ; 0x80
8002f06: d020 beq.n 8002f4a <UART_WaitOnFlagUntilTimeout+0x8a>
8002f08: 68bb ldr r3, [r7, #8]
8002f0a: 2b40 cmp r3, #64 ; 0x40
8002f0c: d01d beq.n 8002f4a <UART_WaitOnFlagUntilTimeout+0x8a>
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
8002f0e: 68fb ldr r3, [r7, #12]
8002f10: 681b ldr r3, [r3, #0]
8002f12: 681b ldr r3, [r3, #0]
8002f14: f003 0308 and.w r3, r3, #8
8002f18: 2b08 cmp r3, #8
8002f1a: d116 bne.n 8002f4a <UART_WaitOnFlagUntilTimeout+0x8a>
{
/* Clear Overrun Error flag*/
__HAL_UART_CLEAR_OREFLAG(huart);
8002f1c: 2300 movs r3, #0
8002f1e: 617b str r3, [r7, #20]
8002f20: 68fb ldr r3, [r7, #12]
8002f22: 681b ldr r3, [r3, #0]
8002f24: 681b ldr r3, [r3, #0]
8002f26: 617b str r3, [r7, #20]
8002f28: 68fb ldr r3, [r7, #12]
8002f2a: 681b ldr r3, [r3, #0]
8002f2c: 685b ldr r3, [r3, #4]
8002f2e: 617b str r3, [r7, #20]
8002f30: 697b ldr r3, [r7, #20]
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts if ongoing */
UART_EndRxTransfer(huart);
8002f32: 68f8 ldr r0, [r7, #12]
8002f34: f000 f81d bl 8002f72 <UART_EndRxTransfer>
huart->ErrorCode = HAL_UART_ERROR_ORE;
8002f38: 68fb ldr r3, [r7, #12]
8002f3a: 2208 movs r2, #8
8002f3c: 645a str r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(huart);
8002f3e: 68fb ldr r3, [r7, #12]
8002f40: 2200 movs r2, #0
8002f42: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_ERROR;
8002f46: 2301 movs r3, #1
8002f48: e00f b.n 8002f6a <UART_WaitOnFlagUntilTimeout+0xaa>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
8002f4a: 68fb ldr r3, [r7, #12]
8002f4c: 681b ldr r3, [r3, #0]
8002f4e: 681a ldr r2, [r3, #0]
8002f50: 68bb ldr r3, [r7, #8]
8002f52: 4013 ands r3, r2
8002f54: 68ba ldr r2, [r7, #8]
8002f56: 429a cmp r2, r3
8002f58: bf0c ite eq
8002f5a: 2301 moveq r3, #1
8002f5c: 2300 movne r3, #0
8002f5e: b2db uxtb r3, r3
8002f60: 461a mov r2, r3
8002f62: 79fb ldrb r3, [r7, #7]
8002f64: 429a cmp r2, r3
8002f66: d0b4 beq.n 8002ed2 <UART_WaitOnFlagUntilTimeout+0x12>
}
}
}
}
return HAL_OK;
8002f68: 2300 movs r3, #0
}
8002f6a: 4618 mov r0, r3
8002f6c: 3718 adds r7, #24
8002f6e: 46bd mov sp, r7
8002f70: bd80 pop {r7, pc}
08002f72 <UART_EndRxTransfer>:
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
* @param huart UART handle.
* @retval None
*/
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
8002f72: b480 push {r7}
8002f74: b095 sub sp, #84 ; 0x54
8002f76: af00 add r7, sp, #0
8002f78: 6078 str r0, [r7, #4]
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
8002f7a: 687b ldr r3, [r7, #4]
8002f7c: 681b ldr r3, [r3, #0]
8002f7e: 330c adds r3, #12
8002f80: 637b str r3, [r7, #52] ; 0x34
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8002f82: 6b7b ldr r3, [r7, #52] ; 0x34
8002f84: e853 3f00 ldrex r3, [r3]
8002f88: 633b str r3, [r7, #48] ; 0x30
return(result);
8002f8a: 6b3b ldr r3, [r7, #48] ; 0x30
8002f8c: f423 7390 bic.w r3, r3, #288 ; 0x120
8002f90: 64fb str r3, [r7, #76] ; 0x4c
8002f92: 687b ldr r3, [r7, #4]
8002f94: 681b ldr r3, [r3, #0]
8002f96: 330c adds r3, #12
8002f98: 6cfa ldr r2, [r7, #76] ; 0x4c
8002f9a: 643a str r2, [r7, #64] ; 0x40
8002f9c: 63fb str r3, [r7, #60] ; 0x3c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8002f9e: 6bf9 ldr r1, [r7, #60] ; 0x3c
8002fa0: 6c3a ldr r2, [r7, #64] ; 0x40
8002fa2: e841 2300 strex r3, r2, [r1]
8002fa6: 63bb str r3, [r7, #56] ; 0x38
return(result);
8002fa8: 6bbb ldr r3, [r7, #56] ; 0x38
8002faa: 2b00 cmp r3, #0
8002fac: d1e5 bne.n 8002f7a <UART_EndRxTransfer+0x8>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8002fae: 687b ldr r3, [r7, #4]
8002fb0: 681b ldr r3, [r3, #0]
8002fb2: 3314 adds r3, #20
8002fb4: 623b str r3, [r7, #32]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8002fb6: 6a3b ldr r3, [r7, #32]
8002fb8: e853 3f00 ldrex r3, [r3]
8002fbc: 61fb str r3, [r7, #28]
return(result);
8002fbe: 69fb ldr r3, [r7, #28]
8002fc0: f023 0301 bic.w r3, r3, #1
8002fc4: 64bb str r3, [r7, #72] ; 0x48
8002fc6: 687b ldr r3, [r7, #4]
8002fc8: 681b ldr r3, [r3, #0]
8002fca: 3314 adds r3, #20
8002fcc: 6cba ldr r2, [r7, #72] ; 0x48
8002fce: 62fa str r2, [r7, #44] ; 0x2c
8002fd0: 62bb str r3, [r7, #40] ; 0x28
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8002fd2: 6ab9 ldr r1, [r7, #40] ; 0x28
8002fd4: 6afa ldr r2, [r7, #44] ; 0x2c
8002fd6: e841 2300 strex r3, r2, [r1]
8002fda: 627b str r3, [r7, #36] ; 0x24
return(result);
8002fdc: 6a7b ldr r3, [r7, #36] ; 0x24
8002fde: 2b00 cmp r3, #0
8002fe0: d1e5 bne.n 8002fae <UART_EndRxTransfer+0x3c>
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8002fe2: 687b ldr r3, [r7, #4]
8002fe4: 6b1b ldr r3, [r3, #48] ; 0x30
8002fe6: 2b01 cmp r3, #1
8002fe8: d119 bne.n 800301e <UART_EndRxTransfer+0xac>
{
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8002fea: 687b ldr r3, [r7, #4]
8002fec: 681b ldr r3, [r3, #0]
8002fee: 330c adds r3, #12
8002ff0: 60fb str r3, [r7, #12]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8002ff2: 68fb ldr r3, [r7, #12]
8002ff4: e853 3f00 ldrex r3, [r3]
8002ff8: 60bb str r3, [r7, #8]
return(result);
8002ffa: 68bb ldr r3, [r7, #8]
8002ffc: f023 0310 bic.w r3, r3, #16
8003000: 647b str r3, [r7, #68] ; 0x44
8003002: 687b ldr r3, [r7, #4]
8003004: 681b ldr r3, [r3, #0]
8003006: 330c adds r3, #12
8003008: 6c7a ldr r2, [r7, #68] ; 0x44
800300a: 61ba str r2, [r7, #24]
800300c: 617b str r3, [r7, #20]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800300e: 6979 ldr r1, [r7, #20]
8003010: 69ba ldr r2, [r7, #24]
8003012: e841 2300 strex r3, r2, [r1]
8003016: 613b str r3, [r7, #16]
return(result);
8003018: 693b ldr r3, [r7, #16]
800301a: 2b00 cmp r3, #0
800301c: d1e5 bne.n 8002fea <UART_EndRxTransfer+0x78>
}
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
800301e: 687b ldr r3, [r7, #4]
8003020: 2220 movs r2, #32
8003022: f883 2042 strb.w r2, [r3, #66] ; 0x42
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8003026: 687b ldr r3, [r7, #4]
8003028: 2200 movs r2, #0
800302a: 631a str r2, [r3, #48] ; 0x30
}
800302c: bf00 nop
800302e: 3754 adds r7, #84 ; 0x54
8003030: 46bd mov sp, r7
8003032: f85d 7b04 ldr.w r7, [sp], #4
8003036: 4770 bx lr
08003038 <UART_SetConfig>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
static void UART_SetConfig(UART_HandleTypeDef *huart)
{
8003038: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
800303c: b0c0 sub sp, #256 ; 0x100
800303e: af00 add r7, sp, #0
8003040: f8c7 00f4 str.w r0, [r7, #244] ; 0xf4
assert_param(IS_UART_MODE(huart->Init.Mode));
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits
according to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
8003044: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8003048: 681b ldr r3, [r3, #0]
800304a: 691b ldr r3, [r3, #16]
800304c: f423 5040 bic.w r0, r3, #12288 ; 0x3000
8003050: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8003054: 68d9 ldr r1, [r3, #12]
8003056: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
800305a: 681a ldr r2, [r3, #0]
800305c: ea40 0301 orr.w r3, r0, r1
8003060: 6113 str r3, [r2, #16]
Set the M bits according to huart->Init.WordLength value
Set PCE and PS bits according to huart->Init.Parity value
Set TE and RE bits according to huart->Init.Mode value
Set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
8003062: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8003066: 689a ldr r2, [r3, #8]
8003068: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
800306c: 691b ldr r3, [r3, #16]
800306e: 431a orrs r2, r3
8003070: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8003074: 695b ldr r3, [r3, #20]
8003076: 431a orrs r2, r3
8003078: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
800307c: 69db ldr r3, [r3, #28]
800307e: 4313 orrs r3, r2
8003080: f8c7 30f8 str.w r3, [r7, #248] ; 0xf8
MODIFY_REG(huart->Instance->CR1,
8003084: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8003088: 681b ldr r3, [r3, #0]
800308a: 68db ldr r3, [r3, #12]
800308c: f423 4116 bic.w r1, r3, #38400 ; 0x9600
8003090: f021 010c bic.w r1, r1, #12
8003094: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8003098: 681a ldr r2, [r3, #0]
800309a: f8d7 30f8 ldr.w r3, [r7, #248] ; 0xf8
800309e: 430b orrs r3, r1
80030a0: 60d3 str r3, [r2, #12]
(uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
tmpreg);
/*-------------------------- USART CR3 Configuration -----------------------*/
/* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
80030a2: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
80030a6: 681b ldr r3, [r3, #0]
80030a8: 695b ldr r3, [r3, #20]
80030aa: f423 7040 bic.w r0, r3, #768 ; 0x300
80030ae: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
80030b2: 6999 ldr r1, [r3, #24]
80030b4: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
80030b8: 681a ldr r2, [r3, #0]
80030ba: ea40 0301 orr.w r3, r0, r1
80030be: 6153 str r3, [r2, #20]
if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10))
{
pclk = HAL_RCC_GetPCLK2Freq();
}
#elif defined(USART6)
if ((huart->Instance == USART1) || (huart->Instance == USART6))
80030c0: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
80030c4: 681a ldr r2, [r3, #0]
80030c6: 4b8f ldr r3, [pc, #572] ; (8003304 <UART_SetConfig+0x2cc>)
80030c8: 429a cmp r2, r3
80030ca: d005 beq.n 80030d8 <UART_SetConfig+0xa0>
80030cc: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
80030d0: 681a ldr r2, [r3, #0]
80030d2: 4b8d ldr r3, [pc, #564] ; (8003308 <UART_SetConfig+0x2d0>)
80030d4: 429a cmp r2, r3
80030d6: d104 bne.n 80030e2 <UART_SetConfig+0xaa>
{
pclk = HAL_RCC_GetPCLK2Freq();
80030d8: f7ff fd42 bl 8002b60 <HAL_RCC_GetPCLK2Freq>
80030dc: f8c7 00fc str.w r0, [r7, #252] ; 0xfc
80030e0: e003 b.n 80030ea <UART_SetConfig+0xb2>
pclk = HAL_RCC_GetPCLK2Freq();
}
#endif /* USART6 */
else
{
pclk = HAL_RCC_GetPCLK1Freq();
80030e2: f7ff fd29 bl 8002b38 <HAL_RCC_GetPCLK1Freq>
80030e6: f8c7 00fc str.w r0, [r7, #252] ; 0xfc
}
/*-------------------------- USART BRR Configuration ---------------------*/
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
80030ea: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
80030ee: 69db ldr r3, [r3, #28]
80030f0: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
80030f4: f040 810c bne.w 8003310 <UART_SetConfig+0x2d8>
{
huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
80030f8: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc
80030fc: 2200 movs r2, #0
80030fe: f8c7 30e8 str.w r3, [r7, #232] ; 0xe8
8003102: f8c7 20ec str.w r2, [r7, #236] ; 0xec
8003106: e9d7 453a ldrd r4, r5, [r7, #232] ; 0xe8
800310a: 4622 mov r2, r4
800310c: 462b mov r3, r5
800310e: 1891 adds r1, r2, r2
8003110: 65b9 str r1, [r7, #88] ; 0x58
8003112: 415b adcs r3, r3
8003114: 65fb str r3, [r7, #92] ; 0x5c
8003116: e9d7 2316 ldrd r2, r3, [r7, #88] ; 0x58
800311a: 4621 mov r1, r4
800311c: eb12 0801 adds.w r8, r2, r1
8003120: 4629 mov r1, r5
8003122: eb43 0901 adc.w r9, r3, r1
8003126: f04f 0200 mov.w r2, #0
800312a: f04f 0300 mov.w r3, #0
800312e: ea4f 03c9 mov.w r3, r9, lsl #3
8003132: ea43 7358 orr.w r3, r3, r8, lsr #29
8003136: ea4f 02c8 mov.w r2, r8, lsl #3
800313a: 4690 mov r8, r2
800313c: 4699 mov r9, r3
800313e: 4623 mov r3, r4
8003140: eb18 0303 adds.w r3, r8, r3
8003144: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0
8003148: 462b mov r3, r5
800314a: eb49 0303 adc.w r3, r9, r3
800314e: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4
8003152: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8003156: 685b ldr r3, [r3, #4]
8003158: 2200 movs r2, #0
800315a: f8c7 30d8 str.w r3, [r7, #216] ; 0xd8
800315e: f8c7 20dc str.w r2, [r7, #220] ; 0xdc
8003162: e9d7 1236 ldrd r1, r2, [r7, #216] ; 0xd8
8003166: 460b mov r3, r1
8003168: 18db adds r3, r3, r3
800316a: 653b str r3, [r7, #80] ; 0x50
800316c: 4613 mov r3, r2
800316e: eb42 0303 adc.w r3, r2, r3
8003172: 657b str r3, [r7, #84] ; 0x54
8003174: e9d7 2314 ldrd r2, r3, [r7, #80] ; 0x50
8003178: e9d7 0138 ldrd r0, r1, [r7, #224] ; 0xe0
800317c: f7fd f83e bl 80001fc <__aeabi_uldivmod>
8003180: 4602 mov r2, r0
8003182: 460b mov r3, r1
8003184: 4b61 ldr r3, [pc, #388] ; (800330c <UART_SetConfig+0x2d4>)
8003186: fba3 2302 umull r2, r3, r3, r2
800318a: 095b lsrs r3, r3, #5
800318c: 011c lsls r4, r3, #4
800318e: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc
8003192: 2200 movs r2, #0
8003194: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0
8003198: f8c7 20d4 str.w r2, [r7, #212] ; 0xd4
800319c: e9d7 8934 ldrd r8, r9, [r7, #208] ; 0xd0
80031a0: 4642 mov r2, r8
80031a2: 464b mov r3, r9
80031a4: 1891 adds r1, r2, r2
80031a6: 64b9 str r1, [r7, #72] ; 0x48
80031a8: 415b adcs r3, r3
80031aa: 64fb str r3, [r7, #76] ; 0x4c
80031ac: e9d7 2312 ldrd r2, r3, [r7, #72] ; 0x48
80031b0: 4641 mov r1, r8
80031b2: eb12 0a01 adds.w sl, r2, r1
80031b6: 4649 mov r1, r9
80031b8: eb43 0b01 adc.w fp, r3, r1
80031bc: f04f 0200 mov.w r2, #0
80031c0: f04f 0300 mov.w r3, #0
80031c4: ea4f 03cb mov.w r3, fp, lsl #3
80031c8: ea43 735a orr.w r3, r3, sl, lsr #29
80031cc: ea4f 02ca mov.w r2, sl, lsl #3
80031d0: 4692 mov sl, r2
80031d2: 469b mov fp, r3
80031d4: 4643 mov r3, r8
80031d6: eb1a 0303 adds.w r3, sl, r3
80031da: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8
80031de: 464b mov r3, r9
80031e0: eb4b 0303 adc.w r3, fp, r3
80031e4: f8c7 30cc str.w r3, [r7, #204] ; 0xcc
80031e8: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
80031ec: 685b ldr r3, [r3, #4]
80031ee: 2200 movs r2, #0
80031f0: f8c7 30c0 str.w r3, [r7, #192] ; 0xc0
80031f4: f8c7 20c4 str.w r2, [r7, #196] ; 0xc4
80031f8: e9d7 1230 ldrd r1, r2, [r7, #192] ; 0xc0
80031fc: 460b mov r3, r1
80031fe: 18db adds r3, r3, r3
8003200: 643b str r3, [r7, #64] ; 0x40
8003202: 4613 mov r3, r2
8003204: eb42 0303 adc.w r3, r2, r3
8003208: 647b str r3, [r7, #68] ; 0x44
800320a: e9d7 2310 ldrd r2, r3, [r7, #64] ; 0x40
800320e: e9d7 0132 ldrd r0, r1, [r7, #200] ; 0xc8
8003212: f7fc fff3 bl 80001fc <__aeabi_uldivmod>
8003216: 4602 mov r2, r0
8003218: 460b mov r3, r1
800321a: 4611 mov r1, r2
800321c: 4b3b ldr r3, [pc, #236] ; (800330c <UART_SetConfig+0x2d4>)
800321e: fba3 2301 umull r2, r3, r3, r1
8003222: 095b lsrs r3, r3, #5
8003224: 2264 movs r2, #100 ; 0x64
8003226: fb02 f303 mul.w r3, r2, r3
800322a: 1acb subs r3, r1, r3
800322c: 00db lsls r3, r3, #3
800322e: f103 0232 add.w r2, r3, #50 ; 0x32
8003232: 4b36 ldr r3, [pc, #216] ; (800330c <UART_SetConfig+0x2d4>)
8003234: fba3 2302 umull r2, r3, r3, r2
8003238: 095b lsrs r3, r3, #5
800323a: 005b lsls r3, r3, #1
800323c: f403 73f8 and.w r3, r3, #496 ; 0x1f0
8003240: 441c add r4, r3
8003242: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc
8003246: 2200 movs r2, #0
8003248: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8
800324c: f8c7 20bc str.w r2, [r7, #188] ; 0xbc
8003250: e9d7 892e ldrd r8, r9, [r7, #184] ; 0xb8
8003254: 4642 mov r2, r8
8003256: 464b mov r3, r9
8003258: 1891 adds r1, r2, r2
800325a: 63b9 str r1, [r7, #56] ; 0x38
800325c: 415b adcs r3, r3
800325e: 63fb str r3, [r7, #60] ; 0x3c
8003260: e9d7 230e ldrd r2, r3, [r7, #56] ; 0x38
8003264: 4641 mov r1, r8
8003266: 1851 adds r1, r2, r1
8003268: 6339 str r1, [r7, #48] ; 0x30
800326a: 4649 mov r1, r9
800326c: 414b adcs r3, r1
800326e: 637b str r3, [r7, #52] ; 0x34
8003270: f04f 0200 mov.w r2, #0
8003274: f04f 0300 mov.w r3, #0
8003278: e9d7 ab0c ldrd sl, fp, [r7, #48] ; 0x30
800327c: 4659 mov r1, fp
800327e: 00cb lsls r3, r1, #3
8003280: 4651 mov r1, sl
8003282: ea43 7351 orr.w r3, r3, r1, lsr #29
8003286: 4651 mov r1, sl
8003288: 00ca lsls r2, r1, #3
800328a: 4610 mov r0, r2
800328c: 4619 mov r1, r3
800328e: 4603 mov r3, r0
8003290: 4642 mov r2, r8
8003292: 189b adds r3, r3, r2
8003294: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0
8003298: 464b mov r3, r9
800329a: 460a mov r2, r1
800329c: eb42 0303 adc.w r3, r2, r3
80032a0: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4
80032a4: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
80032a8: 685b ldr r3, [r3, #4]
80032aa: 2200 movs r2, #0
80032ac: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8
80032b0: f8c7 20ac str.w r2, [r7, #172] ; 0xac
80032b4: e9d7 122a ldrd r1, r2, [r7, #168] ; 0xa8
80032b8: 460b mov r3, r1
80032ba: 18db adds r3, r3, r3
80032bc: 62bb str r3, [r7, #40] ; 0x28
80032be: 4613 mov r3, r2
80032c0: eb42 0303 adc.w r3, r2, r3
80032c4: 62fb str r3, [r7, #44] ; 0x2c
80032c6: e9d7 230a ldrd r2, r3, [r7, #40] ; 0x28
80032ca: e9d7 012c ldrd r0, r1, [r7, #176] ; 0xb0
80032ce: f7fc ff95 bl 80001fc <__aeabi_uldivmod>
80032d2: 4602 mov r2, r0
80032d4: 460b mov r3, r1
80032d6: 4b0d ldr r3, [pc, #52] ; (800330c <UART_SetConfig+0x2d4>)
80032d8: fba3 1302 umull r1, r3, r3, r2
80032dc: 095b lsrs r3, r3, #5
80032de: 2164 movs r1, #100 ; 0x64
80032e0: fb01 f303 mul.w r3, r1, r3
80032e4: 1ad3 subs r3, r2, r3
80032e6: 00db lsls r3, r3, #3
80032e8: 3332 adds r3, #50 ; 0x32
80032ea: 4a08 ldr r2, [pc, #32] ; (800330c <UART_SetConfig+0x2d4>)
80032ec: fba2 2303 umull r2, r3, r2, r3
80032f0: 095b lsrs r3, r3, #5
80032f2: f003 0207 and.w r2, r3, #7
80032f6: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
80032fa: 681b ldr r3, [r3, #0]
80032fc: 4422 add r2, r4
80032fe: 609a str r2, [r3, #8]
}
else
{
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
}
}
8003300: e106 b.n 8003510 <UART_SetConfig+0x4d8>
8003302: bf00 nop
8003304: 40011000 .word 0x40011000
8003308: 40011400 .word 0x40011400
800330c: 51eb851f .word 0x51eb851f
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
8003310: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc
8003314: 2200 movs r2, #0
8003316: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0
800331a: f8c7 20a4 str.w r2, [r7, #164] ; 0xa4
800331e: e9d7 8928 ldrd r8, r9, [r7, #160] ; 0xa0
8003322: 4642 mov r2, r8
8003324: 464b mov r3, r9
8003326: 1891 adds r1, r2, r2
8003328: 6239 str r1, [r7, #32]
800332a: 415b adcs r3, r3
800332c: 627b str r3, [r7, #36] ; 0x24
800332e: e9d7 2308 ldrd r2, r3, [r7, #32]
8003332: 4641 mov r1, r8
8003334: 1854 adds r4, r2, r1
8003336: 4649 mov r1, r9
8003338: eb43 0501 adc.w r5, r3, r1
800333c: f04f 0200 mov.w r2, #0
8003340: f04f 0300 mov.w r3, #0
8003344: 00eb lsls r3, r5, #3
8003346: ea43 7354 orr.w r3, r3, r4, lsr #29
800334a: 00e2 lsls r2, r4, #3
800334c: 4614 mov r4, r2
800334e: 461d mov r5, r3
8003350: 4643 mov r3, r8
8003352: 18e3 adds r3, r4, r3
8003354: f8c7 3098 str.w r3, [r7, #152] ; 0x98
8003358: 464b mov r3, r9
800335a: eb45 0303 adc.w r3, r5, r3
800335e: f8c7 309c str.w r3, [r7, #156] ; 0x9c
8003362: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8003366: 685b ldr r3, [r3, #4]
8003368: 2200 movs r2, #0
800336a: f8c7 3090 str.w r3, [r7, #144] ; 0x90
800336e: f8c7 2094 str.w r2, [r7, #148] ; 0x94
8003372: f04f 0200 mov.w r2, #0
8003376: f04f 0300 mov.w r3, #0
800337a: e9d7 4524 ldrd r4, r5, [r7, #144] ; 0x90
800337e: 4629 mov r1, r5
8003380: 008b lsls r3, r1, #2
8003382: 4621 mov r1, r4
8003384: ea43 7391 orr.w r3, r3, r1, lsr #30
8003388: 4621 mov r1, r4
800338a: 008a lsls r2, r1, #2
800338c: e9d7 0126 ldrd r0, r1, [r7, #152] ; 0x98
8003390: f7fc ff34 bl 80001fc <__aeabi_uldivmod>
8003394: 4602 mov r2, r0
8003396: 460b mov r3, r1
8003398: 4b60 ldr r3, [pc, #384] ; (800351c <UART_SetConfig+0x4e4>)
800339a: fba3 2302 umull r2, r3, r3, r2
800339e: 095b lsrs r3, r3, #5
80033a0: 011c lsls r4, r3, #4
80033a2: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc
80033a6: 2200 movs r2, #0
80033a8: f8c7 3088 str.w r3, [r7, #136] ; 0x88
80033ac: f8c7 208c str.w r2, [r7, #140] ; 0x8c
80033b0: e9d7 8922 ldrd r8, r9, [r7, #136] ; 0x88
80033b4: 4642 mov r2, r8
80033b6: 464b mov r3, r9
80033b8: 1891 adds r1, r2, r2
80033ba: 61b9 str r1, [r7, #24]
80033bc: 415b adcs r3, r3
80033be: 61fb str r3, [r7, #28]
80033c0: e9d7 2306 ldrd r2, r3, [r7, #24]
80033c4: 4641 mov r1, r8
80033c6: 1851 adds r1, r2, r1
80033c8: 6139 str r1, [r7, #16]
80033ca: 4649 mov r1, r9
80033cc: 414b adcs r3, r1
80033ce: 617b str r3, [r7, #20]
80033d0: f04f 0200 mov.w r2, #0
80033d4: f04f 0300 mov.w r3, #0
80033d8: e9d7 ab04 ldrd sl, fp, [r7, #16]
80033dc: 4659 mov r1, fp
80033de: 00cb lsls r3, r1, #3
80033e0: 4651 mov r1, sl
80033e2: ea43 7351 orr.w r3, r3, r1, lsr #29
80033e6: 4651 mov r1, sl
80033e8: 00ca lsls r2, r1, #3
80033ea: 4610 mov r0, r2
80033ec: 4619 mov r1, r3
80033ee: 4603 mov r3, r0
80033f0: 4642 mov r2, r8
80033f2: 189b adds r3, r3, r2
80033f4: f8c7 3080 str.w r3, [r7, #128] ; 0x80
80033f8: 464b mov r3, r9
80033fa: 460a mov r2, r1
80033fc: eb42 0303 adc.w r3, r2, r3
8003400: f8c7 3084 str.w r3, [r7, #132] ; 0x84
8003404: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8003408: 685b ldr r3, [r3, #4]
800340a: 2200 movs r2, #0
800340c: 67bb str r3, [r7, #120] ; 0x78
800340e: 67fa str r2, [r7, #124] ; 0x7c
8003410: f04f 0200 mov.w r2, #0
8003414: f04f 0300 mov.w r3, #0
8003418: e9d7 891e ldrd r8, r9, [r7, #120] ; 0x78
800341c: 4649 mov r1, r9
800341e: 008b lsls r3, r1, #2
8003420: 4641 mov r1, r8
8003422: ea43 7391 orr.w r3, r3, r1, lsr #30
8003426: 4641 mov r1, r8
8003428: 008a lsls r2, r1, #2
800342a: e9d7 0120 ldrd r0, r1, [r7, #128] ; 0x80
800342e: f7fc fee5 bl 80001fc <__aeabi_uldivmod>
8003432: 4602 mov r2, r0
8003434: 460b mov r3, r1
8003436: 4611 mov r1, r2
8003438: 4b38 ldr r3, [pc, #224] ; (800351c <UART_SetConfig+0x4e4>)
800343a: fba3 2301 umull r2, r3, r3, r1
800343e: 095b lsrs r3, r3, #5
8003440: 2264 movs r2, #100 ; 0x64
8003442: fb02 f303 mul.w r3, r2, r3
8003446: 1acb subs r3, r1, r3
8003448: 011b lsls r3, r3, #4
800344a: 3332 adds r3, #50 ; 0x32
800344c: 4a33 ldr r2, [pc, #204] ; (800351c <UART_SetConfig+0x4e4>)
800344e: fba2 2303 umull r2, r3, r2, r3
8003452: 095b lsrs r3, r3, #5
8003454: f003 03f0 and.w r3, r3, #240 ; 0xf0
8003458: 441c add r4, r3
800345a: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc
800345e: 2200 movs r2, #0
8003460: 673b str r3, [r7, #112] ; 0x70
8003462: 677a str r2, [r7, #116] ; 0x74
8003464: e9d7 891c ldrd r8, r9, [r7, #112] ; 0x70
8003468: 4642 mov r2, r8
800346a: 464b mov r3, r9
800346c: 1891 adds r1, r2, r2
800346e: 60b9 str r1, [r7, #8]
8003470: 415b adcs r3, r3
8003472: 60fb str r3, [r7, #12]
8003474: e9d7 2302 ldrd r2, r3, [r7, #8]
8003478: 4641 mov r1, r8
800347a: 1851 adds r1, r2, r1
800347c: 6039 str r1, [r7, #0]
800347e: 4649 mov r1, r9
8003480: 414b adcs r3, r1
8003482: 607b str r3, [r7, #4]
8003484: f04f 0200 mov.w r2, #0
8003488: f04f 0300 mov.w r3, #0
800348c: e9d7 ab00 ldrd sl, fp, [r7]
8003490: 4659 mov r1, fp
8003492: 00cb lsls r3, r1, #3
8003494: 4651 mov r1, sl
8003496: ea43 7351 orr.w r3, r3, r1, lsr #29
800349a: 4651 mov r1, sl
800349c: 00ca lsls r2, r1, #3
800349e: 4610 mov r0, r2
80034a0: 4619 mov r1, r3
80034a2: 4603 mov r3, r0
80034a4: 4642 mov r2, r8
80034a6: 189b adds r3, r3, r2
80034a8: 66bb str r3, [r7, #104] ; 0x68
80034aa: 464b mov r3, r9
80034ac: 460a mov r2, r1
80034ae: eb42 0303 adc.w r3, r2, r3
80034b2: 66fb str r3, [r7, #108] ; 0x6c
80034b4: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
80034b8: 685b ldr r3, [r3, #4]
80034ba: 2200 movs r2, #0
80034bc: 663b str r3, [r7, #96] ; 0x60
80034be: 667a str r2, [r7, #100] ; 0x64
80034c0: f04f 0200 mov.w r2, #0
80034c4: f04f 0300 mov.w r3, #0
80034c8: e9d7 8918 ldrd r8, r9, [r7, #96] ; 0x60
80034cc: 4649 mov r1, r9
80034ce: 008b lsls r3, r1, #2
80034d0: 4641 mov r1, r8
80034d2: ea43 7391 orr.w r3, r3, r1, lsr #30
80034d6: 4641 mov r1, r8
80034d8: 008a lsls r2, r1, #2
80034da: e9d7 011a ldrd r0, r1, [r7, #104] ; 0x68
80034de: f7fc fe8d bl 80001fc <__aeabi_uldivmod>
80034e2: 4602 mov r2, r0
80034e4: 460b mov r3, r1
80034e6: 4b0d ldr r3, [pc, #52] ; (800351c <UART_SetConfig+0x4e4>)
80034e8: fba3 1302 umull r1, r3, r3, r2
80034ec: 095b lsrs r3, r3, #5
80034ee: 2164 movs r1, #100 ; 0x64
80034f0: fb01 f303 mul.w r3, r1, r3
80034f4: 1ad3 subs r3, r2, r3
80034f6: 011b lsls r3, r3, #4
80034f8: 3332 adds r3, #50 ; 0x32
80034fa: 4a08 ldr r2, [pc, #32] ; (800351c <UART_SetConfig+0x4e4>)
80034fc: fba2 2303 umull r2, r3, r2, r3
8003500: 095b lsrs r3, r3, #5
8003502: f003 020f and.w r2, r3, #15
8003506: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
800350a: 681b ldr r3, [r3, #0]
800350c: 4422 add r2, r4
800350e: 609a str r2, [r3, #8]
}
8003510: bf00 nop
8003512: f507 7780 add.w r7, r7, #256 ; 0x100
8003516: 46bd mov sp, r7
8003518: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
800351c: 51eb851f .word 0x51eb851f
08003520 <USB_CoreInit>:
* @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
{
8003520: b084 sub sp, #16
8003522: b580 push {r7, lr}
8003524: b084 sub sp, #16
8003526: af00 add r7, sp, #0
8003528: 6078 str r0, [r7, #4]
800352a: f107 001c add.w r0, r7, #28
800352e: e880 000e stmia.w r0, {r1, r2, r3}
HAL_StatusTypeDef ret;
if (cfg.phy_itface == USB_OTG_ULPI_PHY)
8003532: f897 3021 ldrb.w r3, [r7, #33] ; 0x21
8003536: 2b01 cmp r3, #1
8003538: d123 bne.n 8003582 <USB_CoreInit+0x62>
{
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
800353a: 687b ldr r3, [r7, #4]
800353c: 6b9b ldr r3, [r3, #56] ; 0x38
800353e: f423 3280 bic.w r2, r3, #65536 ; 0x10000
8003542: 687b ldr r3, [r7, #4]
8003544: 639a str r2, [r3, #56] ; 0x38
/* Init The ULPI Interface */
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
8003546: 687b ldr r3, [r7, #4]
8003548: 68db ldr r3, [r3, #12]
800354a: f423 0384 bic.w r3, r3, #4325376 ; 0x420000
800354e: f023 0340 bic.w r3, r3, #64 ; 0x40
8003552: 687a ldr r2, [r7, #4]
8003554: 60d3 str r3, [r2, #12]
/* Select vbus source */
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
8003556: 687b ldr r3, [r7, #4]
8003558: 68db ldr r3, [r3, #12]
800355a: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
800355e: 687b ldr r3, [r7, #4]
8003560: 60da str r2, [r3, #12]
if (cfg.use_external_vbus == 1U)
8003562: f897 3028 ldrb.w r3, [r7, #40] ; 0x28
8003566: 2b01 cmp r3, #1
8003568: d105 bne.n 8003576 <USB_CoreInit+0x56>
{
USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;
800356a: 687b ldr r3, [r7, #4]
800356c: 68db ldr r3, [r3, #12]
800356e: f443 1280 orr.w r2, r3, #1048576 ; 0x100000
8003572: 687b ldr r3, [r7, #4]
8003574: 60da str r2, [r3, #12]
}
/* Reset after a PHY select */
ret = USB_CoreReset(USBx);
8003576: 6878 ldr r0, [r7, #4]
8003578: f000 faa0 bl 8003abc <USB_CoreReset>
800357c: 4603 mov r3, r0
800357e: 73fb strb r3, [r7, #15]
8003580: e01b b.n 80035ba <USB_CoreInit+0x9a>
}
else /* FS interface (embedded Phy) */
{
/* Select FS Embedded PHY */
USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
8003582: 687b ldr r3, [r7, #4]
8003584: 68db ldr r3, [r3, #12]
8003586: f043 0240 orr.w r2, r3, #64 ; 0x40
800358a: 687b ldr r3, [r7, #4]
800358c: 60da str r2, [r3, #12]
/* Reset after a PHY select */
ret = USB_CoreReset(USBx);
800358e: 6878 ldr r0, [r7, #4]
8003590: f000 fa94 bl 8003abc <USB_CoreReset>
8003594: 4603 mov r3, r0
8003596: 73fb strb r3, [r7, #15]
if (cfg.battery_charging_enable == 0U)
8003598: f897 3025 ldrb.w r3, [r7, #37] ; 0x25
800359c: 2b00 cmp r3, #0
800359e: d106 bne.n 80035ae <USB_CoreInit+0x8e>
{
/* Activate the USB Transceiver */
USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
80035a0: 687b ldr r3, [r7, #4]
80035a2: 6b9b ldr r3, [r3, #56] ; 0x38
80035a4: f443 3280 orr.w r2, r3, #65536 ; 0x10000
80035a8: 687b ldr r3, [r7, #4]
80035aa: 639a str r2, [r3, #56] ; 0x38
80035ac: e005 b.n 80035ba <USB_CoreInit+0x9a>
}
else
{
/* Deactivate the USB Transceiver */
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
80035ae: 687b ldr r3, [r7, #4]
80035b0: 6b9b ldr r3, [r3, #56] ; 0x38
80035b2: f423 3280 bic.w r2, r3, #65536 ; 0x10000
80035b6: 687b ldr r3, [r7, #4]
80035b8: 639a str r2, [r3, #56] ; 0x38
}
}
if (cfg.dma_enable == 1U)
80035ba: 7fbb ldrb r3, [r7, #30]
80035bc: 2b01 cmp r3, #1
80035be: d10b bne.n 80035d8 <USB_CoreInit+0xb8>
{
USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2;
80035c0: 687b ldr r3, [r7, #4]
80035c2: 689b ldr r3, [r3, #8]
80035c4: f043 0206 orr.w r2, r3, #6
80035c8: 687b ldr r3, [r7, #4]
80035ca: 609a str r2, [r3, #8]
USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
80035cc: 687b ldr r3, [r7, #4]
80035ce: 689b ldr r3, [r3, #8]
80035d0: f043 0220 orr.w r2, r3, #32
80035d4: 687b ldr r3, [r7, #4]
80035d6: 609a str r2, [r3, #8]
}
return ret;
80035d8: 7bfb ldrb r3, [r7, #15]
}
80035da: 4618 mov r0, r3
80035dc: 3710 adds r7, #16
80035de: 46bd mov sp, r7
80035e0: e8bd 4080 ldmia.w sp!, {r7, lr}
80035e4: b004 add sp, #16
80035e6: 4770 bx lr
080035e8 <USB_DisableGlobalInt>:
* Disable the controller's Global Int in the AHB Config reg
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
{
80035e8: b480 push {r7}
80035ea: b083 sub sp, #12
80035ec: af00 add r7, sp, #0
80035ee: 6078 str r0, [r7, #4]
USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
80035f0: 687b ldr r3, [r7, #4]
80035f2: 689b ldr r3, [r3, #8]
80035f4: f023 0201 bic.w r2, r3, #1
80035f8: 687b ldr r3, [r7, #4]
80035fa: 609a str r2, [r3, #8]
return HAL_OK;
80035fc: 2300 movs r3, #0
}
80035fe: 4618 mov r0, r3
8003600: 370c adds r7, #12
8003602: 46bd mov sp, r7
8003604: f85d 7b04 ldr.w r7, [sp], #4
8003608: 4770 bx lr
0800360a <USB_SetCurrentMode>:
* @arg USB_DEVICE_MODE Peripheral mode
* @arg USB_HOST_MODE Host mode
* @retval HAL status
*/
HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode)
{
800360a: b580 push {r7, lr}
800360c: b084 sub sp, #16
800360e: af00 add r7, sp, #0
8003610: 6078 str r0, [r7, #4]
8003612: 460b mov r3, r1
8003614: 70fb strb r3, [r7, #3]
uint32_t ms = 0U;
8003616: 2300 movs r3, #0
8003618: 60fb str r3, [r7, #12]
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
800361a: 687b ldr r3, [r7, #4]
800361c: 68db ldr r3, [r3, #12]
800361e: f023 42c0 bic.w r2, r3, #1610612736 ; 0x60000000
8003622: 687b ldr r3, [r7, #4]
8003624: 60da str r2, [r3, #12]
if (mode == USB_HOST_MODE)
8003626: 78fb ldrb r3, [r7, #3]
8003628: 2b01 cmp r3, #1
800362a: d115 bne.n 8003658 <USB_SetCurrentMode+0x4e>
{
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
800362c: 687b ldr r3, [r7, #4]
800362e: 68db ldr r3, [r3, #12]
8003630: f043 5200 orr.w r2, r3, #536870912 ; 0x20000000
8003634: 687b ldr r3, [r7, #4]
8003636: 60da str r2, [r3, #12]
do
{
HAL_Delay(10U);
8003638: 200a movs r0, #10
800363a: f7fd fec5 bl 80013c8 <HAL_Delay>
ms += 10U;
800363e: 68fb ldr r3, [r7, #12]
8003640: 330a adds r3, #10
8003642: 60fb str r3, [r7, #12]
} while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
8003644: 6878 ldr r0, [r7, #4]
8003646: f000 fa2b bl 8003aa0 <USB_GetMode>
800364a: 4603 mov r3, r0
800364c: 2b01 cmp r3, #1
800364e: d01e beq.n 800368e <USB_SetCurrentMode+0x84>
8003650: 68fb ldr r3, [r7, #12]
8003652: 2bc7 cmp r3, #199 ; 0xc7
8003654: d9f0 bls.n 8003638 <USB_SetCurrentMode+0x2e>
8003656: e01a b.n 800368e <USB_SetCurrentMode+0x84>
}
else if (mode == USB_DEVICE_MODE)
8003658: 78fb ldrb r3, [r7, #3]
800365a: 2b00 cmp r3, #0
800365c: d115 bne.n 800368a <USB_SetCurrentMode+0x80>
{
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
800365e: 687b ldr r3, [r7, #4]
8003660: 68db ldr r3, [r3, #12]
8003662: f043 4280 orr.w r2, r3, #1073741824 ; 0x40000000
8003666: 687b ldr r3, [r7, #4]
8003668: 60da str r2, [r3, #12]
do
{
HAL_Delay(10U);
800366a: 200a movs r0, #10
800366c: f7fd feac bl 80013c8 <HAL_Delay>
ms += 10U;
8003670: 68fb ldr r3, [r7, #12]
8003672: 330a adds r3, #10
8003674: 60fb str r3, [r7, #12]
} while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
8003676: 6878 ldr r0, [r7, #4]
8003678: f000 fa12 bl 8003aa0 <USB_GetMode>
800367c: 4603 mov r3, r0
800367e: 2b00 cmp r3, #0
8003680: d005 beq.n 800368e <USB_SetCurrentMode+0x84>
8003682: 68fb ldr r3, [r7, #12]
8003684: 2bc7 cmp r3, #199 ; 0xc7
8003686: d9f0 bls.n 800366a <USB_SetCurrentMode+0x60>
8003688: e001 b.n 800368e <USB_SetCurrentMode+0x84>
}
else
{
return HAL_ERROR;
800368a: 2301 movs r3, #1
800368c: e005 b.n 800369a <USB_SetCurrentMode+0x90>
}
if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS)
800368e: 68fb ldr r3, [r7, #12]
8003690: 2bc8 cmp r3, #200 ; 0xc8
8003692: d101 bne.n 8003698 <USB_SetCurrentMode+0x8e>
{
return HAL_ERROR;
8003694: 2301 movs r3, #1
8003696: e000 b.n 800369a <USB_SetCurrentMode+0x90>
}
return HAL_OK;
8003698: 2300 movs r3, #0
}
800369a: 4618 mov r0, r3
800369c: 3710 adds r7, #16
800369e: 46bd mov sp, r7
80036a0: bd80 pop {r7, pc}
...
080036a4 <USB_DevInit>:
* @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
{
80036a4: b084 sub sp, #16
80036a6: b580 push {r7, lr}
80036a8: b086 sub sp, #24
80036aa: af00 add r7, sp, #0
80036ac: 6078 str r0, [r7, #4]
80036ae: f107 0024 add.w r0, r7, #36 ; 0x24
80036b2: e880 000e stmia.w r0, {r1, r2, r3}
HAL_StatusTypeDef ret = HAL_OK;
80036b6: 2300 movs r3, #0
80036b8: 75fb strb r3, [r7, #23]
uint32_t USBx_BASE = (uint32_t)USBx;
80036ba: 687b ldr r3, [r7, #4]
80036bc: 60fb str r3, [r7, #12]
uint32_t i;
for (i = 0U; i < 15U; i++)
80036be: 2300 movs r3, #0
80036c0: 613b str r3, [r7, #16]
80036c2: e009 b.n 80036d8 <USB_DevInit+0x34>
{
USBx->DIEPTXF[i] = 0U;
80036c4: 687a ldr r2, [r7, #4]
80036c6: 693b ldr r3, [r7, #16]
80036c8: 3340 adds r3, #64 ; 0x40
80036ca: 009b lsls r3, r3, #2
80036cc: 4413 add r3, r2
80036ce: 2200 movs r2, #0
80036d0: 605a str r2, [r3, #4]
for (i = 0U; i < 15U; i++)
80036d2: 693b ldr r3, [r7, #16]
80036d4: 3301 adds r3, #1
80036d6: 613b str r3, [r7, #16]
80036d8: 693b ldr r3, [r7, #16]
80036da: 2b0e cmp r3, #14
80036dc: d9f2 bls.n 80036c4 <USB_DevInit+0x20>
/* Enable HW VBUS sensing */
USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
}
#else
/* VBUS Sensing setup */
if (cfg.vbus_sensing_enable == 0U)
80036de: f897 302e ldrb.w r3, [r7, #46] ; 0x2e
80036e2: 2b00 cmp r3, #0
80036e4: d11c bne.n 8003720 <USB_DevInit+0x7c>
{
/*
* Disable HW VBUS sensing. VBUS is internally considered to be always
* at VBUS-Valid level (5V).
*/
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
80036e6: 68fb ldr r3, [r7, #12]
80036e8: f503 6300 add.w r3, r3, #2048 ; 0x800
80036ec: 685b ldr r3, [r3, #4]
80036ee: 68fa ldr r2, [r7, #12]
80036f0: f502 6200 add.w r2, r2, #2048 ; 0x800
80036f4: f043 0302 orr.w r3, r3, #2
80036f8: 6053 str r3, [r2, #4]
USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
80036fa: 687b ldr r3, [r7, #4]
80036fc: 6b9b ldr r3, [r3, #56] ; 0x38
80036fe: f443 1200 orr.w r2, r3, #2097152 ; 0x200000
8003702: 687b ldr r3, [r7, #4]
8003704: 639a str r2, [r3, #56] ; 0x38
USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
8003706: 687b ldr r3, [r7, #4]
8003708: 6b9b ldr r3, [r3, #56] ; 0x38
800370a: f423 2200 bic.w r2, r3, #524288 ; 0x80000
800370e: 687b ldr r3, [r7, #4]
8003710: 639a str r2, [r3, #56] ; 0x38
USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;
8003712: 687b ldr r3, [r7, #4]
8003714: 6b9b ldr r3, [r3, #56] ; 0x38
8003716: f423 2280 bic.w r2, r3, #262144 ; 0x40000
800371a: 687b ldr r3, [r7, #4]
800371c: 639a str r2, [r3, #56] ; 0x38
800371e: e00b b.n 8003738 <USB_DevInit+0x94>
}
else
{
/* Enable HW VBUS sensing */
USBx->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
8003720: 687b ldr r3, [r7, #4]
8003722: 6b9b ldr r3, [r3, #56] ; 0x38
8003724: f423 1200 bic.w r2, r3, #2097152 ; 0x200000
8003728: 687b ldr r3, [r7, #4]
800372a: 639a str r2, [r3, #56] ; 0x38
USBx->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
800372c: 687b ldr r3, [r7, #4]
800372e: 6b9b ldr r3, [r3, #56] ; 0x38
8003730: f443 2200 orr.w r2, r3, #524288 ; 0x80000
8003734: 687b ldr r3, [r7, #4]
8003736: 639a str r2, [r3, #56] ; 0x38
#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||
defined(STM32F423xx) */
/* Restart the Phy Clock */
USBx_PCGCCTL = 0U;
8003738: 68fb ldr r3, [r7, #12]
800373a: f503 6360 add.w r3, r3, #3584 ; 0xe00
800373e: 461a mov r2, r3
8003740: 2300 movs r3, #0
8003742: 6013 str r3, [r2, #0]
if (cfg.phy_itface == USB_OTG_ULPI_PHY)
8003744: f897 3029 ldrb.w r3, [r7, #41] ; 0x29
8003748: 2b01 cmp r3, #1
800374a: d10d bne.n 8003768 <USB_DevInit+0xc4>
{
if (cfg.speed == USBD_HS_SPEED)
800374c: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8003750: 2b00 cmp r3, #0
8003752: d104 bne.n 800375e <USB_DevInit+0xba>
{
/* Set Core speed to High speed mode */
(void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH);
8003754: 2100 movs r1, #0
8003756: 6878 ldr r0, [r7, #4]
8003758: f000 f968 bl 8003a2c <USB_SetDevSpeed>
800375c: e008 b.n 8003770 <USB_DevInit+0xcc>
}
else
{
/* Set Core speed to Full speed mode */
(void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL);
800375e: 2101 movs r1, #1
8003760: 6878 ldr r0, [r7, #4]
8003762: f000 f963 bl 8003a2c <USB_SetDevSpeed>
8003766: e003 b.n 8003770 <USB_DevInit+0xcc>
}
}
else
{
/* Set Core speed to Full speed mode */
(void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL);
8003768: 2103 movs r1, #3
800376a: 6878 ldr r0, [r7, #4]
800376c: f000 f95e bl 8003a2c <USB_SetDevSpeed>
}
/* Flush the FIFOs */
if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
8003770: 2110 movs r1, #16
8003772: 6878 ldr r0, [r7, #4]
8003774: f000 f8fa bl 800396c <USB_FlushTxFifo>
8003778: 4603 mov r3, r0
800377a: 2b00 cmp r3, #0
800377c: d001 beq.n 8003782 <USB_DevInit+0xde>
{
ret = HAL_ERROR;
800377e: 2301 movs r3, #1
8003780: 75fb strb r3, [r7, #23]
}
if (USB_FlushRxFifo(USBx) != HAL_OK)
8003782: 6878 ldr r0, [r7, #4]
8003784: f000 f924 bl 80039d0 <USB_FlushRxFifo>
8003788: 4603 mov r3, r0
800378a: 2b00 cmp r3, #0
800378c: d001 beq.n 8003792 <USB_DevInit+0xee>
{
ret = HAL_ERROR;
800378e: 2301 movs r3, #1
8003790: 75fb strb r3, [r7, #23]
}
/* Clear all pending Device Interrupts */
USBx_DEVICE->DIEPMSK = 0U;
8003792: 68fb ldr r3, [r7, #12]
8003794: f503 6300 add.w r3, r3, #2048 ; 0x800
8003798: 461a mov r2, r3
800379a: 2300 movs r3, #0
800379c: 6113 str r3, [r2, #16]
USBx_DEVICE->DOEPMSK = 0U;
800379e: 68fb ldr r3, [r7, #12]
80037a0: f503 6300 add.w r3, r3, #2048 ; 0x800
80037a4: 461a mov r2, r3
80037a6: 2300 movs r3, #0
80037a8: 6153 str r3, [r2, #20]
USBx_DEVICE->DAINTMSK = 0U;
80037aa: 68fb ldr r3, [r7, #12]
80037ac: f503 6300 add.w r3, r3, #2048 ; 0x800
80037b0: 461a mov r2, r3
80037b2: 2300 movs r3, #0
80037b4: 61d3 str r3, [r2, #28]
for (i = 0U; i < cfg.dev_endpoints; i++)
80037b6: 2300 movs r3, #0
80037b8: 613b str r3, [r7, #16]
80037ba: e043 b.n 8003844 <USB_DevInit+0x1a0>
{
if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
80037bc: 693b ldr r3, [r7, #16]
80037be: 015a lsls r2, r3, #5
80037c0: 68fb ldr r3, [r7, #12]
80037c2: 4413 add r3, r2
80037c4: f503 6310 add.w r3, r3, #2304 ; 0x900
80037c8: 681b ldr r3, [r3, #0]
80037ca: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000
80037ce: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000
80037d2: d118 bne.n 8003806 <USB_DevInit+0x162>
{
if (i == 0U)
80037d4: 693b ldr r3, [r7, #16]
80037d6: 2b00 cmp r3, #0
80037d8: d10a bne.n 80037f0 <USB_DevInit+0x14c>
{
USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;
80037da: 693b ldr r3, [r7, #16]
80037dc: 015a lsls r2, r3, #5
80037de: 68fb ldr r3, [r7, #12]
80037e0: 4413 add r3, r2
80037e2: f503 6310 add.w r3, r3, #2304 ; 0x900
80037e6: 461a mov r2, r3
80037e8: f04f 6300 mov.w r3, #134217728 ; 0x8000000
80037ec: 6013 str r3, [r2, #0]
80037ee: e013 b.n 8003818 <USB_DevInit+0x174>
}
else
{
USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK;
80037f0: 693b ldr r3, [r7, #16]
80037f2: 015a lsls r2, r3, #5
80037f4: 68fb ldr r3, [r7, #12]
80037f6: 4413 add r3, r2
80037f8: f503 6310 add.w r3, r3, #2304 ; 0x900
80037fc: 461a mov r2, r3
80037fe: f04f 4390 mov.w r3, #1207959552 ; 0x48000000
8003802: 6013 str r3, [r2, #0]
8003804: e008 b.n 8003818 <USB_DevInit+0x174>
}
}
else
{
USBx_INEP(i)->DIEPCTL = 0U;
8003806: 693b ldr r3, [r7, #16]
8003808: 015a lsls r2, r3, #5
800380a: 68fb ldr r3, [r7, #12]
800380c: 4413 add r3, r2
800380e: f503 6310 add.w r3, r3, #2304 ; 0x900
8003812: 461a mov r2, r3
8003814: 2300 movs r3, #0
8003816: 6013 str r3, [r2, #0]
}
USBx_INEP(i)->DIEPTSIZ = 0U;
8003818: 693b ldr r3, [r7, #16]
800381a: 015a lsls r2, r3, #5
800381c: 68fb ldr r3, [r7, #12]
800381e: 4413 add r3, r2
8003820: f503 6310 add.w r3, r3, #2304 ; 0x900
8003824: 461a mov r2, r3
8003826: 2300 movs r3, #0
8003828: 6113 str r3, [r2, #16]
USBx_INEP(i)->DIEPINT = 0xFB7FU;
800382a: 693b ldr r3, [r7, #16]
800382c: 015a lsls r2, r3, #5
800382e: 68fb ldr r3, [r7, #12]
8003830: 4413 add r3, r2
8003832: f503 6310 add.w r3, r3, #2304 ; 0x900
8003836: 461a mov r2, r3
8003838: f64f 337f movw r3, #64383 ; 0xfb7f
800383c: 6093 str r3, [r2, #8]
for (i = 0U; i < cfg.dev_endpoints; i++)
800383e: 693b ldr r3, [r7, #16]
8003840: 3301 adds r3, #1
8003842: 613b str r3, [r7, #16]
8003844: f897 3024 ldrb.w r3, [r7, #36] ; 0x24
8003848: 461a mov r2, r3
800384a: 693b ldr r3, [r7, #16]
800384c: 4293 cmp r3, r2
800384e: d3b5 bcc.n 80037bc <USB_DevInit+0x118>
}
for (i = 0U; i < cfg.dev_endpoints; i++)
8003850: 2300 movs r3, #0
8003852: 613b str r3, [r7, #16]
8003854: e043 b.n 80038de <USB_DevInit+0x23a>
{
if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
8003856: 693b ldr r3, [r7, #16]
8003858: 015a lsls r2, r3, #5
800385a: 68fb ldr r3, [r7, #12]
800385c: 4413 add r3, r2
800385e: f503 6330 add.w r3, r3, #2816 ; 0xb00
8003862: 681b ldr r3, [r3, #0]
8003864: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000
8003868: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000
800386c: d118 bne.n 80038a0 <USB_DevInit+0x1fc>
{
if (i == 0U)
800386e: 693b ldr r3, [r7, #16]
8003870: 2b00 cmp r3, #0
8003872: d10a bne.n 800388a <USB_DevInit+0x1e6>
{
USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;
8003874: 693b ldr r3, [r7, #16]
8003876: 015a lsls r2, r3, #5
8003878: 68fb ldr r3, [r7, #12]
800387a: 4413 add r3, r2
800387c: f503 6330 add.w r3, r3, #2816 ; 0xb00
8003880: 461a mov r2, r3
8003882: f04f 6300 mov.w r3, #134217728 ; 0x8000000
8003886: 6013 str r3, [r2, #0]
8003888: e013 b.n 80038b2 <USB_DevInit+0x20e>
}
else
{
USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK;
800388a: 693b ldr r3, [r7, #16]
800388c: 015a lsls r2, r3, #5
800388e: 68fb ldr r3, [r7, #12]
8003890: 4413 add r3, r2
8003892: f503 6330 add.w r3, r3, #2816 ; 0xb00
8003896: 461a mov r2, r3
8003898: f04f 4390 mov.w r3, #1207959552 ; 0x48000000
800389c: 6013 str r3, [r2, #0]
800389e: e008 b.n 80038b2 <USB_DevInit+0x20e>
}
}
else
{
USBx_OUTEP(i)->DOEPCTL = 0U;
80038a0: 693b ldr r3, [r7, #16]
80038a2: 015a lsls r2, r3, #5
80038a4: 68fb ldr r3, [r7, #12]
80038a6: 4413 add r3, r2
80038a8: f503 6330 add.w r3, r3, #2816 ; 0xb00
80038ac: 461a mov r2, r3
80038ae: 2300 movs r3, #0
80038b0: 6013 str r3, [r2, #0]
}
USBx_OUTEP(i)->DOEPTSIZ = 0U;
80038b2: 693b ldr r3, [r7, #16]
80038b4: 015a lsls r2, r3, #5
80038b6: 68fb ldr r3, [r7, #12]
80038b8: 4413 add r3, r2
80038ba: f503 6330 add.w r3, r3, #2816 ; 0xb00
80038be: 461a mov r2, r3
80038c0: 2300 movs r3, #0
80038c2: 6113 str r3, [r2, #16]
USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
80038c4: 693b ldr r3, [r7, #16]
80038c6: 015a lsls r2, r3, #5
80038c8: 68fb ldr r3, [r7, #12]
80038ca: 4413 add r3, r2
80038cc: f503 6330 add.w r3, r3, #2816 ; 0xb00
80038d0: 461a mov r2, r3
80038d2: f64f 337f movw r3, #64383 ; 0xfb7f
80038d6: 6093 str r3, [r2, #8]
for (i = 0U; i < cfg.dev_endpoints; i++)
80038d8: 693b ldr r3, [r7, #16]
80038da: 3301 adds r3, #1
80038dc: 613b str r3, [r7, #16]
80038de: f897 3024 ldrb.w r3, [r7, #36] ; 0x24
80038e2: 461a mov r2, r3
80038e4: 693b ldr r3, [r7, #16]
80038e6: 4293 cmp r3, r2
80038e8: d3b5 bcc.n 8003856 <USB_DevInit+0x1b2>
}
USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
80038ea: 68fb ldr r3, [r7, #12]
80038ec: f503 6300 add.w r3, r3, #2048 ; 0x800
80038f0: 691b ldr r3, [r3, #16]
80038f2: 68fa ldr r2, [r7, #12]
80038f4: f502 6200 add.w r2, r2, #2048 ; 0x800
80038f8: f423 7380 bic.w r3, r3, #256 ; 0x100
80038fc: 6113 str r3, [r2, #16]
/* Disable all interrupts. */
USBx->GINTMSK = 0U;
80038fe: 687b ldr r3, [r7, #4]
8003900: 2200 movs r2, #0
8003902: 619a str r2, [r3, #24]
/* Clear any pending interrupts */
USBx->GINTSTS = 0xBFFFFFFFU;
8003904: 687b ldr r3, [r7, #4]
8003906: f06f 4280 mvn.w r2, #1073741824 ; 0x40000000
800390a: 615a str r2, [r3, #20]
/* Enable the common interrupts */
if (cfg.dma_enable == 0U)
800390c: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
8003910: 2b00 cmp r3, #0
8003912: d105 bne.n 8003920 <USB_DevInit+0x27c>
{
USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
8003914: 687b ldr r3, [r7, #4]
8003916: 699b ldr r3, [r3, #24]
8003918: f043 0210 orr.w r2, r3, #16
800391c: 687b ldr r3, [r7, #4]
800391e: 619a str r2, [r3, #24]
}
/* Enable interrupts matching to the Device mode ONLY */
USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |
8003920: 687b ldr r3, [r7, #4]
8003922: 699a ldr r2, [r3, #24]
8003924: 4b10 ldr r3, [pc, #64] ; (8003968 <USB_DevInit+0x2c4>)
8003926: 4313 orrs r3, r2
8003928: 687a ldr r2, [r7, #4]
800392a: 6193 str r3, [r2, #24]
USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |
USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM |
USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM;
if (cfg.Sof_enable != 0U)
800392c: f897 302a ldrb.w r3, [r7, #42] ; 0x2a
8003930: 2b00 cmp r3, #0
8003932: d005 beq.n 8003940 <USB_DevInit+0x29c>
{
USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
8003934: 687b ldr r3, [r7, #4]
8003936: 699b ldr r3, [r3, #24]
8003938: f043 0208 orr.w r2, r3, #8
800393c: 687b ldr r3, [r7, #4]
800393e: 619a str r2, [r3, #24]
}
if (cfg.vbus_sensing_enable == 1U)
8003940: f897 302e ldrb.w r3, [r7, #46] ; 0x2e
8003944: 2b01 cmp r3, #1
8003946: d107 bne.n 8003958 <USB_DevInit+0x2b4>
{
USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);
8003948: 687b ldr r3, [r7, #4]
800394a: 699b ldr r3, [r3, #24]
800394c: f043 4380 orr.w r3, r3, #1073741824 ; 0x40000000
8003950: f043 0304 orr.w r3, r3, #4
8003954: 687a ldr r2, [r7, #4]
8003956: 6193 str r3, [r2, #24]
}
return ret;
8003958: 7dfb ldrb r3, [r7, #23]
}
800395a: 4618 mov r0, r3
800395c: 3718 adds r7, #24
800395e: 46bd mov sp, r7
8003960: e8bd 4080 ldmia.w sp!, {r7, lr}
8003964: b004 add sp, #16
8003966: 4770 bx lr
8003968: 803c3800 .word 0x803c3800
0800396c <USB_FlushTxFifo>:
* This parameter can be a value from 1 to 15
15 means Flush all Tx FIFOs
* @retval HAL status
*/
HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
{
800396c: b480 push {r7}
800396e: b085 sub sp, #20
8003970: af00 add r7, sp, #0
8003972: 6078 str r0, [r7, #4]
8003974: 6039 str r1, [r7, #0]
__IO uint32_t count = 0U;
8003976: 2300 movs r3, #0
8003978: 60fb str r3, [r7, #12]
/* Wait for AHB master IDLE state. */
do
{
count++;
800397a: 68fb ldr r3, [r7, #12]
800397c: 3301 adds r3, #1
800397e: 60fb str r3, [r7, #12]
if (count > HAL_USB_TIMEOUT)
8003980: 68fb ldr r3, [r7, #12]
8003982: f1b3 6f70 cmp.w r3, #251658240 ; 0xf000000
8003986: d901 bls.n 800398c <USB_FlushTxFifo+0x20>
{
return HAL_TIMEOUT;
8003988: 2303 movs r3, #3
800398a: e01b b.n 80039c4 <USB_FlushTxFifo+0x58>
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
800398c: 687b ldr r3, [r7, #4]
800398e: 691b ldr r3, [r3, #16]
8003990: 2b00 cmp r3, #0
8003992: daf2 bge.n 800397a <USB_FlushTxFifo+0xe>
/* Flush TX Fifo */
count = 0U;
8003994: 2300 movs r3, #0
8003996: 60fb str r3, [r7, #12]
USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));
8003998: 683b ldr r3, [r7, #0]
800399a: 019b lsls r3, r3, #6
800399c: f043 0220 orr.w r2, r3, #32
80039a0: 687b ldr r3, [r7, #4]
80039a2: 611a str r2, [r3, #16]
do
{
count++;
80039a4: 68fb ldr r3, [r7, #12]
80039a6: 3301 adds r3, #1
80039a8: 60fb str r3, [r7, #12]
if (count > HAL_USB_TIMEOUT)
80039aa: 68fb ldr r3, [r7, #12]
80039ac: f1b3 6f70 cmp.w r3, #251658240 ; 0xf000000
80039b0: d901 bls.n 80039b6 <USB_FlushTxFifo+0x4a>
{
return HAL_TIMEOUT;
80039b2: 2303 movs r3, #3
80039b4: e006 b.n 80039c4 <USB_FlushTxFifo+0x58>
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
80039b6: 687b ldr r3, [r7, #4]
80039b8: 691b ldr r3, [r3, #16]
80039ba: f003 0320 and.w r3, r3, #32
80039be: 2b20 cmp r3, #32
80039c0: d0f0 beq.n 80039a4 <USB_FlushTxFifo+0x38>
return HAL_OK;
80039c2: 2300 movs r3, #0
}
80039c4: 4618 mov r0, r3
80039c6: 3714 adds r7, #20
80039c8: 46bd mov sp, r7
80039ca: f85d 7b04 ldr.w r7, [sp], #4
80039ce: 4770 bx lr
080039d0 <USB_FlushRxFifo>:
* @brief USB_FlushRxFifo Flush Rx FIFO
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
{
80039d0: b480 push {r7}
80039d2: b085 sub sp, #20
80039d4: af00 add r7, sp, #0
80039d6: 6078 str r0, [r7, #4]
__IO uint32_t count = 0U;
80039d8: 2300 movs r3, #0
80039da: 60fb str r3, [r7, #12]
/* Wait for AHB master IDLE state. */
do
{
count++;
80039dc: 68fb ldr r3, [r7, #12]
80039de: 3301 adds r3, #1
80039e0: 60fb str r3, [r7, #12]
if (count > HAL_USB_TIMEOUT)
80039e2: 68fb ldr r3, [r7, #12]
80039e4: f1b3 6f70 cmp.w r3, #251658240 ; 0xf000000
80039e8: d901 bls.n 80039ee <USB_FlushRxFifo+0x1e>
{
return HAL_TIMEOUT;
80039ea: 2303 movs r3, #3
80039ec: e018 b.n 8003a20 <USB_FlushRxFifo+0x50>
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
80039ee: 687b ldr r3, [r7, #4]
80039f0: 691b ldr r3, [r3, #16]
80039f2: 2b00 cmp r3, #0
80039f4: daf2 bge.n 80039dc <USB_FlushRxFifo+0xc>
/* Flush RX Fifo */
count = 0U;
80039f6: 2300 movs r3, #0
80039f8: 60fb str r3, [r7, #12]
USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
80039fa: 687b ldr r3, [r7, #4]
80039fc: 2210 movs r2, #16
80039fe: 611a str r2, [r3, #16]
do
{
count++;
8003a00: 68fb ldr r3, [r7, #12]
8003a02: 3301 adds r3, #1
8003a04: 60fb str r3, [r7, #12]
if (count > HAL_USB_TIMEOUT)
8003a06: 68fb ldr r3, [r7, #12]
8003a08: f1b3 6f70 cmp.w r3, #251658240 ; 0xf000000
8003a0c: d901 bls.n 8003a12 <USB_FlushRxFifo+0x42>
{
return HAL_TIMEOUT;
8003a0e: 2303 movs r3, #3
8003a10: e006 b.n 8003a20 <USB_FlushRxFifo+0x50>
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
8003a12: 687b ldr r3, [r7, #4]
8003a14: 691b ldr r3, [r3, #16]
8003a16: f003 0310 and.w r3, r3, #16
8003a1a: 2b10 cmp r3, #16
8003a1c: d0f0 beq.n 8003a00 <USB_FlushRxFifo+0x30>
return HAL_OK;
8003a1e: 2300 movs r3, #0
}
8003a20: 4618 mov r0, r3
8003a22: 3714 adds r7, #20
8003a24: 46bd mov sp, r7
8003a26: f85d 7b04 ldr.w r7, [sp], #4
8003a2a: 4770 bx lr
08003a2c <USB_SetDevSpeed>:
* @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode
* @arg USB_OTG_SPEED_FULL: Full speed mode
* @retval Hal status
*/
HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
{
8003a2c: b480 push {r7}
8003a2e: b085 sub sp, #20
8003a30: af00 add r7, sp, #0
8003a32: 6078 str r0, [r7, #4]
8003a34: 460b mov r3, r1
8003a36: 70fb strb r3, [r7, #3]
uint32_t USBx_BASE = (uint32_t)USBx;
8003a38: 687b ldr r3, [r7, #4]
8003a3a: 60fb str r3, [r7, #12]
USBx_DEVICE->DCFG |= speed;
8003a3c: 68fb ldr r3, [r7, #12]
8003a3e: f503 6300 add.w r3, r3, #2048 ; 0x800
8003a42: 681a ldr r2, [r3, #0]
8003a44: 78fb ldrb r3, [r7, #3]
8003a46: 68f9 ldr r1, [r7, #12]
8003a48: f501 6100 add.w r1, r1, #2048 ; 0x800
8003a4c: 4313 orrs r3, r2
8003a4e: 600b str r3, [r1, #0]
return HAL_OK;
8003a50: 2300 movs r3, #0
}
8003a52: 4618 mov r0, r3
8003a54: 3714 adds r7, #20
8003a56: 46bd mov sp, r7
8003a58: f85d 7b04 ldr.w r7, [sp], #4
8003a5c: 4770 bx lr
08003a5e <USB_DevDisconnect>:
* @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx)
{
8003a5e: b480 push {r7}
8003a60: b085 sub sp, #20
8003a62: af00 add r7, sp, #0
8003a64: 6078 str r0, [r7, #4]
uint32_t USBx_BASE = (uint32_t)USBx;
8003a66: 687b ldr r3, [r7, #4]
8003a68: 60fb str r3, [r7, #12]
/* In case phy is stopped, ensure to ungate and restore the phy CLK */
USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);
8003a6a: 68fb ldr r3, [r7, #12]
8003a6c: f503 6360 add.w r3, r3, #3584 ; 0xe00
8003a70: 681b ldr r3, [r3, #0]
8003a72: 68fa ldr r2, [r7, #12]
8003a74: f502 6260 add.w r2, r2, #3584 ; 0xe00
8003a78: f023 0303 bic.w r3, r3, #3
8003a7c: 6013 str r3, [r2, #0]
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
8003a7e: 68fb ldr r3, [r7, #12]
8003a80: f503 6300 add.w r3, r3, #2048 ; 0x800
8003a84: 685b ldr r3, [r3, #4]
8003a86: 68fa ldr r2, [r7, #12]
8003a88: f502 6200 add.w r2, r2, #2048 ; 0x800
8003a8c: f043 0302 orr.w r3, r3, #2
8003a90: 6053 str r3, [r2, #4]
return HAL_OK;
8003a92: 2300 movs r3, #0
}
8003a94: 4618 mov r0, r3
8003a96: 3714 adds r7, #20
8003a98: 46bd mov sp, r7
8003a9a: f85d 7b04 ldr.w r7, [sp], #4
8003a9e: 4770 bx lr
08003aa0 <USB_GetMode>:
* This parameter can be one of these values:
* 1 : Host
* 0 : Device
*/
uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx)
{
8003aa0: b480 push {r7}
8003aa2: b083 sub sp, #12
8003aa4: af00 add r7, sp, #0
8003aa6: 6078 str r0, [r7, #4]
return ((USBx->GINTSTS) & 0x1U);
8003aa8: 687b ldr r3, [r7, #4]
8003aaa: 695b ldr r3, [r3, #20]
8003aac: f003 0301 and.w r3, r3, #1
}
8003ab0: 4618 mov r0, r3
8003ab2: 370c adds r7, #12
8003ab4: 46bd mov sp, r7
8003ab6: f85d 7b04 ldr.w r7, [sp], #4
8003aba: 4770 bx lr
08003abc <USB_CoreReset>:
* @brief Reset the USB Core (needed after USB clock settings change)
* @param USBx Selected device
* @retval HAL status
*/
static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
{
8003abc: b480 push {r7}
8003abe: b085 sub sp, #20
8003ac0: af00 add r7, sp, #0
8003ac2: 6078 str r0, [r7, #4]
__IO uint32_t count = 0U;
8003ac4: 2300 movs r3, #0
8003ac6: 60fb str r3, [r7, #12]
/* Wait for AHB master IDLE state. */
do
{
count++;
8003ac8: 68fb ldr r3, [r7, #12]
8003aca: 3301 adds r3, #1
8003acc: 60fb str r3, [r7, #12]
if (count > HAL_USB_TIMEOUT)
8003ace: 68fb ldr r3, [r7, #12]
8003ad0: f1b3 6f70 cmp.w r3, #251658240 ; 0xf000000
8003ad4: d901 bls.n 8003ada <USB_CoreReset+0x1e>
{
return HAL_TIMEOUT;
8003ad6: 2303 movs r3, #3
8003ad8: e022 b.n 8003b20 <USB_CoreReset+0x64>
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
8003ada: 687b ldr r3, [r7, #4]
8003adc: 691b ldr r3, [r3, #16]
8003ade: 2b00 cmp r3, #0
8003ae0: daf2 bge.n 8003ac8 <USB_CoreReset+0xc>
count = 10U;
8003ae2: 230a movs r3, #10
8003ae4: 60fb str r3, [r7, #12]
/* few cycles before setting core reset */
while (count > 0U)
8003ae6: e002 b.n 8003aee <USB_CoreReset+0x32>
{
count--;
8003ae8: 68fb ldr r3, [r7, #12]
8003aea: 3b01 subs r3, #1
8003aec: 60fb str r3, [r7, #12]
while (count > 0U)
8003aee: 68fb ldr r3, [r7, #12]
8003af0: 2b00 cmp r3, #0
8003af2: d1f9 bne.n 8003ae8 <USB_CoreReset+0x2c>
}
/* Core Soft Reset */
USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
8003af4: 687b ldr r3, [r7, #4]
8003af6: 691b ldr r3, [r3, #16]
8003af8: f043 0201 orr.w r2, r3, #1
8003afc: 687b ldr r3, [r7, #4]
8003afe: 611a str r2, [r3, #16]
do
{
count++;
8003b00: 68fb ldr r3, [r7, #12]
8003b02: 3301 adds r3, #1
8003b04: 60fb str r3, [r7, #12]
if (count > HAL_USB_TIMEOUT)
8003b06: 68fb ldr r3, [r7, #12]
8003b08: f1b3 6f70 cmp.w r3, #251658240 ; 0xf000000
8003b0c: d901 bls.n 8003b12 <USB_CoreReset+0x56>
{
return HAL_TIMEOUT;
8003b0e: 2303 movs r3, #3
8003b10: e006 b.n 8003b20 <USB_CoreReset+0x64>
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
8003b12: 687b ldr r3, [r7, #4]
8003b14: 691b ldr r3, [r3, #16]
8003b16: f003 0301 and.w r3, r3, #1
8003b1a: 2b01 cmp r3, #1
8003b1c: d0f0 beq.n 8003b00 <USB_CoreReset+0x44>
return HAL_OK;
8003b1e: 2300 movs r3, #0
}
8003b20: 4618 mov r0, r3
8003b22: 3714 adds r7, #20
8003b24: 46bd mov sp, r7
8003b26: f85d 7b04 ldr.w r7, [sp], #4
8003b2a: 4770 bx lr
08003b2c <memset>:
8003b2c: 4402 add r2, r0
8003b2e: 4603 mov r3, r0
8003b30: 4293 cmp r3, r2
8003b32: d100 bne.n 8003b36 <memset+0xa>
8003b34: 4770 bx lr
8003b36: f803 1b01 strb.w r1, [r3], #1
8003b3a: e7f9 b.n 8003b30 <memset+0x4>
08003b3c <__libc_init_array>:
8003b3c: b570 push {r4, r5, r6, lr}
8003b3e: 4d0d ldr r5, [pc, #52] ; (8003b74 <__libc_init_array+0x38>)
8003b40: 4c0d ldr r4, [pc, #52] ; (8003b78 <__libc_init_array+0x3c>)
8003b42: 1b64 subs r4, r4, r5
8003b44: 10a4 asrs r4, r4, #2
8003b46: 2600 movs r6, #0
8003b48: 42a6 cmp r6, r4
8003b4a: d109 bne.n 8003b60 <__libc_init_array+0x24>
8003b4c: 4d0b ldr r5, [pc, #44] ; (8003b7c <__libc_init_array+0x40>)
8003b4e: 4c0c ldr r4, [pc, #48] ; (8003b80 <__libc_init_array+0x44>)
8003b50: f000 f87e bl 8003c50 <_init>
8003b54: 1b64 subs r4, r4, r5
8003b56: 10a4 asrs r4, r4, #2
8003b58: 2600 movs r6, #0
8003b5a: 42a6 cmp r6, r4
8003b5c: d105 bne.n 8003b6a <__libc_init_array+0x2e>
8003b5e: bd70 pop {r4, r5, r6, pc}
8003b60: f855 3b04 ldr.w r3, [r5], #4
8003b64: 4798 blx r3
8003b66: 3601 adds r6, #1
8003b68: e7ee b.n 8003b48 <__libc_init_array+0xc>
8003b6a: f855 3b04 ldr.w r3, [r5], #4
8003b6e: 4798 blx r3
8003b70: 3601 adds r6, #1
8003b72: e7f2 b.n 8003b5a <__libc_init_array+0x1e>
8003b74: 08003c88 .word 0x08003c88
8003b78: 08003c88 .word 0x08003c88
8003b7c: 08003c88 .word 0x08003c88
8003b80: 08003c90 .word 0x08003c90
08003b84 <__retarget_lock_acquire_recursive>:
8003b84: 4770 bx lr
08003b86 <__retarget_lock_release_recursive>:
8003b86: 4770 bx lr
08003b88 <register_fini>:
8003b88: 4b02 ldr r3, [pc, #8] ; (8003b94 <register_fini+0xc>)
8003b8a: b113 cbz r3, 8003b92 <register_fini+0xa>
8003b8c: 4802 ldr r0, [pc, #8] ; (8003b98 <register_fini+0x10>)
8003b8e: f000 b805 b.w 8003b9c <atexit>
8003b92: 4770 bx lr
8003b94: 00000000 .word 0x00000000
8003b98: 08003ba9 .word 0x08003ba9
08003b9c <atexit>:
8003b9c: 2300 movs r3, #0
8003b9e: 4601 mov r1, r0
8003ba0: 461a mov r2, r3
8003ba2: 4618 mov r0, r3
8003ba4: f000 b814 b.w 8003bd0 <__register_exitproc>
08003ba8 <__libc_fini_array>:
8003ba8: b538 push {r3, r4, r5, lr}
8003baa: 4d07 ldr r5, [pc, #28] ; (8003bc8 <__libc_fini_array+0x20>)
8003bac: 4c07 ldr r4, [pc, #28] ; (8003bcc <__libc_fini_array+0x24>)
8003bae: 1b64 subs r4, r4, r5
8003bb0: 10a4 asrs r4, r4, #2
8003bb2: b91c cbnz r4, 8003bbc <__libc_fini_array+0x14>
8003bb4: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
8003bb8: f000 b850 b.w 8003c5c <_fini>
8003bbc: 3c01 subs r4, #1
8003bbe: f855 3024 ldr.w r3, [r5, r4, lsl #2]
8003bc2: 4798 blx r3
8003bc4: e7f5 b.n 8003bb2 <__libc_fini_array+0xa>
8003bc6: bf00 nop
8003bc8: 08003c90 .word 0x08003c90
8003bcc: 08003c94 .word 0x08003c94
08003bd0 <__register_exitproc>:
8003bd0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
8003bd4: f8df a074 ldr.w sl, [pc, #116] ; 8003c4c <__register_exitproc+0x7c>
8003bd8: 4606 mov r6, r0
8003bda: f8da 0000 ldr.w r0, [sl]
8003bde: 4698 mov r8, r3
8003be0: 460f mov r7, r1
8003be2: 4691 mov r9, r2
8003be4: f7ff ffce bl 8003b84 <__retarget_lock_acquire_recursive>
8003be8: 4b16 ldr r3, [pc, #88] ; (8003c44 <__register_exitproc+0x74>)
8003bea: 681c ldr r4, [r3, #0]
8003bec: b90c cbnz r4, 8003bf2 <__register_exitproc+0x22>
8003bee: 4c16 ldr r4, [pc, #88] ; (8003c48 <__register_exitproc+0x78>)
8003bf0: 601c str r4, [r3, #0]
8003bf2: 6865 ldr r5, [r4, #4]
8003bf4: f8da 0000 ldr.w r0, [sl]
8003bf8: 2d1f cmp r5, #31
8003bfa: dd05 ble.n 8003c08 <__register_exitproc+0x38>
8003bfc: f7ff ffc3 bl 8003b86 <__retarget_lock_release_recursive>
8003c00: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
8003c04: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8003c08: b19e cbz r6, 8003c32 <__register_exitproc+0x62>
8003c0a: eb04 0185 add.w r1, r4, r5, lsl #2
8003c0e: 2201 movs r2, #1
8003c10: f8c1 9088 str.w r9, [r1, #136] ; 0x88
8003c14: f8d4 3188 ldr.w r3, [r4, #392] ; 0x188
8003c18: 40aa lsls r2, r5
8003c1a: 4313 orrs r3, r2
8003c1c: f8c4 3188 str.w r3, [r4, #392] ; 0x188
8003c20: 2e02 cmp r6, #2
8003c22: f8c1 8108 str.w r8, [r1, #264] ; 0x108
8003c26: bf02 ittt eq
8003c28: f8d4 318c ldreq.w r3, [r4, #396] ; 0x18c
8003c2c: 4313 orreq r3, r2
8003c2e: f8c4 318c streq.w r3, [r4, #396] ; 0x18c
8003c32: 1c6b adds r3, r5, #1
8003c34: 3502 adds r5, #2
8003c36: 6063 str r3, [r4, #4]
8003c38: f844 7025 str.w r7, [r4, r5, lsl #2]
8003c3c: f7ff ffa3 bl 8003b86 <__retarget_lock_release_recursive>
8003c40: 2000 movs r0, #0
8003c42: e7df b.n 8003c04 <__register_exitproc+0x34>
8003c44: 200010a8 .word 0x200010a8
8003c48: 200010ac .word 0x200010ac
8003c4c: 200006c4 .word 0x200006c4
08003c50 <_init>:
8003c50: b5f8 push {r3, r4, r5, r6, r7, lr}
8003c52: bf00 nop
8003c54: bcf8 pop {r3, r4, r5, r6, r7}
8003c56: bc08 pop {r3}
8003c58: 469e mov lr, r3
8003c5a: 4770 bx lr
08003c5c <_fini>:
8003c5c: b5f8 push {r3, r4, r5, r6, r7, lr}
8003c5e: bf00 nop
8003c60: bcf8 pop {r3, r4, r5, r6, r7}
8003c62: bc08 pop {r3}
8003c64: 469e mov lr, r3
8003c66: 4770 bx lr
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