: /** * @brief The application entry point. * @retval int */ int main(void) { 800096c: b5b0 push {r4, r5, r7, lr} 800096e: b092 sub sp, #72 ; 0x48 8000970: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8000972: f000 fc77 bl 8001264 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8000976: f000 f85d bl 8000a34 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 800097a: f000 f97f bl 8000c7c MX_ETH_Init(); 800097e: f000 f8c3 bl 8000b08 MX_USART3_UART_Init(); 8000982: f000 f923 bl 8000bcc MX_USB_OTG_FS_PCD_Init(); 8000986: f000 f94b bl 8000c20 MX_RNG_Init(); 800098a: f000 f90b bl 8000ba4 /* USER CODE BEGIN 2 */ init_entropy(); 800098e: f7ff fdb3 bl 80004f8 while (1) { /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ HAL_StatusTypeDef status = HAL_UART_Receive(&huart3, &buf_recv, 1, 100); 8000992: f107 011b add.w r1, r7, #27 8000996: 2364 movs r3, #100 ; 0x64 8000998: 2201 movs r2, #1 800099a: 4824 ldr r0, [pc, #144] ; (8000a2c ) 800099c: f002 fa77 bl 8002e8e 80009a0: 4603 mov r3, r0 80009a2: f887 3047 strb.w r3, [r7, #71] ; 0x47 if (status == HAL_OK){ 80009a6: f897 3047 ldrb.w r3, [r7, #71] ; 0x47 80009aa: 2b00 cmp r3, #0 80009ac: d1f1 bne.n 8000992 if (buf_recv == 1){ 80009ae: 7efb ldrb r3, [r7, #27] 80009b0: 2b01 cmp r3, #1 80009b2: d1ee bne.n 8000992 struct prng s_prng = {0}; 80009b4: 463b mov r3, r7 80009b6: 2200 movs r2, #0 80009b8: 601a str r2, [r3, #0] 80009ba: 605a str r2, [r3, #4] 80009bc: 609a str r2, [r3, #8] 80009be: 60da str r2, [r3, #12] 80009c0: 611a str r2, [r3, #16] 80009c2: 615a str r2, [r3, #20] memset(buffer, 0, sizeof(struct prng)); 80009c4: f107 031c add.w r3, r7, #28 80009c8: 2218 movs r2, #24 80009ca: 2100 movs r1, #0 80009cc: 4618 mov r0, r3 80009ce: f003 fd2d bl 800442c HAL_GPIO_WritePin(GPIOB, GPIO_PIN_0, GPIO_PIN_SET); 80009d2: 2201 movs r2, #1 80009d4: 2101 movs r1, #1 80009d6: 4816 ldr r0, [pc, #88] ; (8000a30 ) 80009d8: f001 fb7a bl 80020d0 unsigned long long random = bbs(&s_prng.p, &s_prng.q, &s_prng.seed); 80009dc: 463b mov r3, r7 80009de: f103 0208 add.w r2, r3, #8 80009e2: 463b mov r3, r7 80009e4: 1d19 adds r1, r3, #4 80009e6: 463b mov r3, r7 80009e8: 4618 mov r0, r3 80009ea: f7ff fe97 bl 800071c 80009ee: e9c7 010e strd r0, r1, [r7, #56] ; 0x38 s_prng.output = random; 80009f2: e9d7 230e ldrd r2, r3, [r7, #56] ; 0x38 80009f6: e9c7 2304 strd r2, r3, [r7, #16] memcpy(buffer, &s_prng, sizeof(struct prng)); 80009fa: f107 041c add.w r4, r7, #28 80009fe: 463d mov r5, r7 8000a00: cd0f ldmia r5!, {r0, r1, r2, r3} 8000a02: c40f stmia r4!, {r0, r1, r2, r3} 8000a04: e895 0003 ldmia.w r5, {r0, r1} 8000a08: e884 0003 stmia.w r4, {r0, r1} HAL_StatusTypeDef s = HAL_UART_Transmit(&huart3, buffer, sizeof(struct prng), 0xF); 8000a0c: f107 011c add.w r1, r7, #28 8000a10: 230f movs r3, #15 8000a12: 2218 movs r2, #24 8000a14: 4805 ldr r0, [pc, #20] ; (8000a2c ) 8000a16: f002 f9af bl 8002d78 8000a1a: 4603 mov r3, r0 8000a1c: f887 3037 strb.w r3, [r7, #55] ; 0x37 // We have finished, we disable the pin HAL_GPIO_WritePin(GPIOB, GPIO_PIN_0, GPIO_PIN_RESET); 8000a20: 2200 movs r2, #0 8000a22: 2101 movs r1, #1 8000a24: 4802 ldr r0, [pc, #8] ; (8000a30 ) 8000a26: f001 fb53 bl 80020d0 { 8000a2a: e7b2 b.n 8000992 8000a2c: 20000b24 .word 0x20000b24 8000a30: 40020400 .word 0x40020400 08000a34 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8000a34: b580 push {r7, lr} 8000a36: b094 sub sp, #80 ; 0x50 8000a38: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8000a3a: f107 0320 add.w r3, r7, #32 8000a3e: 2230 movs r2, #48 ; 0x30 8000a40: 2100 movs r1, #0 8000a42: 4618 mov r0, r3 8000a44: f003 fcf2 bl 800442c RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000a48: f107 030c add.w r3, r7, #12 8000a4c: 2200 movs r2, #0 8000a4e: 601a str r2, [r3, #0] 8000a50: 605a str r2, [r3, #4] 8000a52: 609a str r2, [r3, #8] 8000a54: 60da str r2, [r3, #12] 8000a56: 611a str r2, [r3, #16] /** Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); 8000a58: 2300 movs r3, #0 8000a5a: 60bb str r3, [r7, #8] 8000a5c: 4b28 ldr r3, [pc, #160] ; (8000b00 ) 8000a5e: 6c1b ldr r3, [r3, #64] ; 0x40 8000a60: 4a27 ldr r2, [pc, #156] ; (8000b00 ) 8000a62: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8000a66: 6413 str r3, [r2, #64] ; 0x40 8000a68: 4b25 ldr r3, [pc, #148] ; (8000b00 ) 8000a6a: 6c1b ldr r3, [r3, #64] ; 0x40 8000a6c: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8000a70: 60bb str r3, [r7, #8] 8000a72: 68bb ldr r3, [r7, #8] __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 8000a74: 2300 movs r3, #0 8000a76: 607b str r3, [r7, #4] 8000a78: 4b22 ldr r3, [pc, #136] ; (8000b04 ) 8000a7a: 681b ldr r3, [r3, #0] 8000a7c: 4a21 ldr r2, [pc, #132] ; (8000b04 ) 8000a7e: f443 4340 orr.w r3, r3, #49152 ; 0xc000 8000a82: 6013 str r3, [r2, #0] 8000a84: 4b1f ldr r3, [pc, #124] ; (8000b04 ) 8000a86: 681b ldr r3, [r3, #0] 8000a88: f403 4340 and.w r3, r3, #49152 ; 0xc000 8000a8c: 607b str r3, [r7, #4] 8000a8e: 687b ldr r3, [r7, #4] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 8000a90: 2301 movs r3, #1 8000a92: 623b str r3, [r7, #32] RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; 8000a94: f44f 23a0 mov.w r3, #327680 ; 0x50000 8000a98: 627b str r3, [r7, #36] ; 0x24 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8000a9a: 2302 movs r3, #2 8000a9c: 63bb str r3, [r7, #56] ; 0x38 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 8000a9e: f44f 0380 mov.w r3, #4194304 ; 0x400000 8000aa2: 63fb str r3, [r7, #60] ; 0x3c RCC_OscInitStruct.PLL.PLLM = 4; 8000aa4: 2304 movs r3, #4 8000aa6: 643b str r3, [r7, #64] ; 0x40 RCC_OscInitStruct.PLL.PLLN = 168; 8000aa8: 23a8 movs r3, #168 ; 0xa8 8000aaa: 647b str r3, [r7, #68] ; 0x44 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 8000aac: 2302 movs r3, #2 8000aae: 64bb str r3, [r7, #72] ; 0x48 RCC_OscInitStruct.PLL.PLLQ = 7; 8000ab0: 2307 movs r3, #7 8000ab2: 64fb str r3, [r7, #76] ; 0x4c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8000ab4: f107 0320 add.w r3, r7, #32 8000ab8: 4618 mov r0, r3 8000aba: f001 fc4b bl 8002354 8000abe: 4603 mov r3, r0 8000ac0: 2b00 cmp r3, #0 8000ac2: d001 beq.n 8000ac8 { Error_Handler(); 8000ac4: f000 f99e bl 8000e04 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8000ac8: 230f movs r3, #15 8000aca: 60fb str r3, [r7, #12] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 8000acc: 2302 movs r3, #2 8000ace: 613b str r3, [r7, #16] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 8000ad0: 2300 movs r3, #0 8000ad2: 617b str r3, [r7, #20] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; 8000ad4: f44f 53a0 mov.w r3, #5120 ; 0x1400 8000ad8: 61bb str r3, [r7, #24] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; 8000ada: f44f 5380 mov.w r3, #4096 ; 0x1000 8000ade: 61fb str r3, [r7, #28] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) 8000ae0: f107 030c add.w r3, r7, #12 8000ae4: 2105 movs r1, #5 8000ae6: 4618 mov r0, r3 8000ae8: f001 feac bl 8002844 8000aec: 4603 mov r3, r0 8000aee: 2b00 cmp r3, #0 8000af0: d001 beq.n 8000af6 { Error_Handler(); 8000af2: f000 f987 bl 8000e04 } } 8000af6: bf00 nop 8000af8: 3750 adds r7, #80 ; 0x50 8000afa: 46bd mov sp, r7 8000afc: bd80 pop {r7, pc} 8000afe: bf00 nop 8000b00: 40023800 .word 0x40023800 8000b04: 40007000 .word 0x40007000 08000b08 : * @brief ETH Initialization Function * @param None * @retval None */ static void MX_ETH_Init(void) { 8000b08: b580 push {r7, lr} 8000b0a: af00 add r7, sp, #0 static uint8_t MACAddr[6]; /* USER CODE BEGIN ETH_Init 1 */ /* USER CODE END ETH_Init 1 */ heth.Instance = ETH; 8000b0c: 4b1f ldr r3, [pc, #124] ; (8000b8c ) 8000b0e: 4a20 ldr r2, [pc, #128] ; (8000b90 ) 8000b10: 601a str r2, [r3, #0] MACAddr[0] = 0x00; 8000b12: 4b20 ldr r3, [pc, #128] ; (8000b94 ) 8000b14: 2200 movs r2, #0 8000b16: 701a strb r2, [r3, #0] MACAddr[1] = 0x80; 8000b18: 4b1e ldr r3, [pc, #120] ; (8000b94 ) 8000b1a: 2280 movs r2, #128 ; 0x80 8000b1c: 705a strb r2, [r3, #1] MACAddr[2] = 0xE1; 8000b1e: 4b1d ldr r3, [pc, #116] ; (8000b94 ) 8000b20: 22e1 movs r2, #225 ; 0xe1 8000b22: 709a strb r2, [r3, #2] MACAddr[3] = 0x00; 8000b24: 4b1b ldr r3, [pc, #108] ; (8000b94 ) 8000b26: 2200 movs r2, #0 8000b28: 70da strb r2, [r3, #3] MACAddr[4] = 0x00; 8000b2a: 4b1a ldr r3, [pc, #104] ; (8000b94 ) 8000b2c: 2200 movs r2, #0 8000b2e: 711a strb r2, [r3, #4] MACAddr[5] = 0x00; 8000b30: 4b18 ldr r3, [pc, #96] ; (8000b94 ) 8000b32: 2200 movs r2, #0 8000b34: 715a strb r2, [r3, #5] heth.Init.MACAddr = &MACAddr[0]; 8000b36: 4b15 ldr r3, [pc, #84] ; (8000b8c ) 8000b38: 4a16 ldr r2, [pc, #88] ; (8000b94 ) 8000b3a: 605a str r2, [r3, #4] heth.Init.MediaInterface = HAL_ETH_RMII_MODE; 8000b3c: 4b13 ldr r3, [pc, #76] ; (8000b8c ) 8000b3e: f44f 0200 mov.w r2, #8388608 ; 0x800000 8000b42: 609a str r2, [r3, #8] heth.Init.TxDesc = DMATxDscrTab; 8000b44: 4b11 ldr r3, [pc, #68] ; (8000b8c ) 8000b46: 4a14 ldr r2, [pc, #80] ; (8000b98 ) 8000b48: 60da str r2, [r3, #12] heth.Init.RxDesc = DMARxDscrTab; 8000b4a: 4b10 ldr r3, [pc, #64] ; (8000b8c ) 8000b4c: 4a13 ldr r2, [pc, #76] ; (8000b9c ) 8000b4e: 611a str r2, [r3, #16] heth.Init.RxBuffLen = 1524; 8000b50: 4b0e ldr r3, [pc, #56] ; (8000b8c ) 8000b52: f240 52f4 movw r2, #1524 ; 0x5f4 8000b56: 615a str r2, [r3, #20] /* USER CODE BEGIN MACADDRESS */ /* USER CODE END MACADDRESS */ if (HAL_ETH_Init(&heth) != HAL_OK) 8000b58: 480c ldr r0, [pc, #48] ; (8000b8c ) 8000b5a: f000 fdbd bl 80016d8 8000b5e: 4603 mov r3, r0 8000b60: 2b00 cmp r3, #0 8000b62: d001 beq.n 8000b68 { Error_Handler(); 8000b64: f000 f94e bl 8000e04 } memset(&TxConfig, 0 , sizeof(ETH_TxPacketConfig)); 8000b68: 2238 movs r2, #56 ; 0x38 8000b6a: 2100 movs r1, #0 8000b6c: 480c ldr r0, [pc, #48] ; (8000ba0 ) 8000b6e: f003 fc5d bl 800442c TxConfig.Attributes = ETH_TX_PACKETS_FEATURES_CSUM | ETH_TX_PACKETS_FEATURES_CRCPAD; 8000b72: 4b0b ldr r3, [pc, #44] ; (8000ba0 ) 8000b74: 2221 movs r2, #33 ; 0x21 8000b76: 601a str r2, [r3, #0] TxConfig.ChecksumCtrl = ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC; 8000b78: 4b09 ldr r3, [pc, #36] ; (8000ba0 ) 8000b7a: f44f 0240 mov.w r2, #12582912 ; 0xc00000 8000b7e: 615a str r2, [r3, #20] TxConfig.CRCPadCtrl = ETH_CRC_PAD_INSERT; 8000b80: 4b07 ldr r3, [pc, #28] ; (8000ba0 ) 8000b82: 2200 movs r2, #0 8000b84: 611a str r2, [r3, #16] /* USER CODE BEGIN ETH_Init 2 */ /* USER CODE END ETH_Init 2 */ } 8000b86: bf00 nop 8000b88: bd80 pop {r7, pc} 8000b8a: bf00 nop 8000b8c: 20000a64 .word 0x20000a64 8000b90: 40028000 .word 0x40028000 8000b94: 20001050 .word 0x20001050 8000b98: 200009c4 .word 0x200009c4 8000b9c: 20000924 .word 0x20000924 8000ba0: 200008ec .word 0x200008ec 08000ba4 : * @brief RNG Initialization Function * @param None * @retval None */ static void MX_RNG_Init(void) { 8000ba4: b580 push {r7, lr} 8000ba6: af00 add r7, sp, #0 /* USER CODE END RNG_Init 0 */ /* USER CODE BEGIN RNG_Init 1 */ /* USER CODE END RNG_Init 1 */ hrng.Instance = RNG; 8000ba8: 4b06 ldr r3, [pc, #24] ; (8000bc4 ) 8000baa: 4a07 ldr r2, [pc, #28] ; (8000bc8 ) 8000bac: 601a str r2, [r3, #0] if (HAL_RNG_Init(&hrng) != HAL_OK) 8000bae: 4805 ldr r0, [pc, #20] ; (8000bc4 ) 8000bb0: f002 f868 bl 8002c84 8000bb4: 4603 mov r3, r0 8000bb6: 2b00 cmp r3, #0 8000bb8: d001 beq.n 8000bbe { Error_Handler(); 8000bba: f000 f923 bl 8000e04 } /* USER CODE BEGIN RNG_Init 2 */ /* USER CODE END RNG_Init 2 */ } 8000bbe: bf00 nop 8000bc0: bd80 pop {r7, pc} 8000bc2: bf00 nop 8000bc4: 20000b14 .word 0x20000b14 8000bc8: 50060800 .word 0x50060800 08000bcc : * @brief USART3 Initialization Function * @param None * @retval None */ static void MX_USART3_UART_Init(void) { 8000bcc: b580 push {r7, lr} 8000bce: af00 add r7, sp, #0 /* USER CODE END USART3_Init 0 */ /* USER CODE BEGIN USART3_Init 1 */ /* USER CODE END USART3_Init 1 */ huart3.Instance = USART3; 8000bd0: 4b11 ldr r3, [pc, #68] ; (8000c18 ) 8000bd2: 4a12 ldr r2, [pc, #72] ; (8000c1c ) 8000bd4: 601a str r2, [r3, #0] huart3.Init.BaudRate = 115200; 8000bd6: 4b10 ldr r3, [pc, #64] ; (8000c18 ) 8000bd8: f44f 32e1 mov.w r2, #115200 ; 0x1c200 8000bdc: 605a str r2, [r3, #4] huart3.Init.WordLength = UART_WORDLENGTH_8B; 8000bde: 4b0e ldr r3, [pc, #56] ; (8000c18 ) 8000be0: 2200 movs r2, #0 8000be2: 609a str r2, [r3, #8] huart3.Init.StopBits = UART_STOPBITS_1; 8000be4: 4b0c ldr r3, [pc, #48] ; (8000c18 ) 8000be6: 2200 movs r2, #0 8000be8: 60da str r2, [r3, #12] huart3.Init.Parity = UART_PARITY_NONE; 8000bea: 4b0b ldr r3, [pc, #44] ; (8000c18 ) 8000bec: 2200 movs r2, #0 8000bee: 611a str r2, [r3, #16] huart3.Init.Mode = UART_MODE_TX_RX; 8000bf0: 4b09 ldr r3, [pc, #36] ; (8000c18 ) 8000bf2: 220c movs r2, #12 8000bf4: 615a str r2, [r3, #20] huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8000bf6: 4b08 ldr r3, [pc, #32] ; (8000c18 ) 8000bf8: 2200 movs r2, #0 8000bfa: 619a str r2, [r3, #24] huart3.Init.OverSampling = UART_OVERSAMPLING_16; 8000bfc: 4b06 ldr r3, [pc, #24] ; (8000c18 ) 8000bfe: 2200 movs r2, #0 8000c00: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart3) != HAL_OK) 8000c02: 4805 ldr r0, [pc, #20] ; (8000c18 ) 8000c04: f002 f868 bl 8002cd8 8000c08: 4603 mov r3, r0 8000c0a: 2b00 cmp r3, #0 8000c0c: d001 beq.n 8000c12 { Error_Handler(); 8000c0e: f000 f8f9 bl 8000e04 } /* USER CODE BEGIN USART3_Init 2 */ /* USER CODE END USART3_Init 2 */ } 8000c12: bf00 nop 8000c14: bd80 pop {r7, pc} 8000c16: bf00 nop 8000c18: 20000b24 .word 0x20000b24 8000c1c: 40004800 .word 0x40004800 08000c20 : * @brief USB_OTG_FS Initialization Function * @param None * @retval None */ static void MX_USB_OTG_FS_PCD_Init(void) { 8000c20: b580 push {r7, lr} 8000c22: af00 add r7, sp, #0 /* USER CODE END USB_OTG_FS_Init 0 */ /* USER CODE BEGIN USB_OTG_FS_Init 1 */ /* USER CODE END USB_OTG_FS_Init 1 */ hpcd_USB_OTG_FS.Instance = USB_OTG_FS; 8000c24: 4b14 ldr r3, [pc, #80] ; (8000c78 ) 8000c26: f04f 42a0 mov.w r2, #1342177280 ; 0x50000000 8000c2a: 601a str r2, [r3, #0] hpcd_USB_OTG_FS.Init.dev_endpoints = 4; 8000c2c: 4b12 ldr r3, [pc, #72] ; (8000c78 ) 8000c2e: 2204 movs r2, #4 8000c30: 711a strb r2, [r3, #4] hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL; 8000c32: 4b11 ldr r3, [pc, #68] ; (8000c78 ) 8000c34: 2202 movs r2, #2 8000c36: 71da strb r2, [r3, #7] hpcd_USB_OTG_FS.Init.dma_enable = DISABLE; 8000c38: 4b0f ldr r3, [pc, #60] ; (8000c78 ) 8000c3a: 2200 movs r2, #0 8000c3c: 719a strb r2, [r3, #6] hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED; 8000c3e: 4b0e ldr r3, [pc, #56] ; (8000c78 ) 8000c40: 2202 movs r2, #2 8000c42: 725a strb r2, [r3, #9] hpcd_USB_OTG_FS.Init.Sof_enable = ENABLE; 8000c44: 4b0c ldr r3, [pc, #48] ; (8000c78 ) 8000c46: 2201 movs r2, #1 8000c48: 729a strb r2, [r3, #10] hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE; 8000c4a: 4b0b ldr r3, [pc, #44] ; (8000c78 ) 8000c4c: 2200 movs r2, #0 8000c4e: 72da strb r2, [r3, #11] hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE; 8000c50: 4b09 ldr r3, [pc, #36] ; (8000c78 ) 8000c52: 2200 movs r2, #0 8000c54: 731a strb r2, [r3, #12] hpcd_USB_OTG_FS.Init.vbus_sensing_enable = ENABLE; 8000c56: 4b08 ldr r3, [pc, #32] ; (8000c78 ) 8000c58: 2201 movs r2, #1 8000c5a: 739a strb r2, [r3, #14] hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE; 8000c5c: 4b06 ldr r3, [pc, #24] ; (8000c78 ) 8000c5e: 2200 movs r2, #0 8000c60: 73da strb r2, [r3, #15] if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK) 8000c62: 4805 ldr r0, [pc, #20] ; (8000c78 ) 8000c64: f001 fa67 bl 8002136 8000c68: 4603 mov r3, r0 8000c6a: 2b00 cmp r3, #0 8000c6c: d001 beq.n 8000c72 { Error_Handler(); 8000c6e: f000 f8c9 bl 8000e04 } /* USER CODE BEGIN USB_OTG_FS_Init 2 */ /* USER CODE END USB_OTG_FS_Init 2 */ } 8000c72: bf00 nop 8000c74: bd80 pop {r7, pc} 8000c76: bf00 nop 8000c78: 20000b6c .word 0x20000b6c 08000c7c : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 8000c7c: b580 push {r7, lr} 8000c7e: b08c sub sp, #48 ; 0x30 8000c80: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000c82: f107 031c add.w r3, r7, #28 8000c86: 2200 movs r2, #0 8000c88: 601a str r2, [r3, #0] 8000c8a: 605a str r2, [r3, #4] 8000c8c: 609a str r2, [r3, #8] 8000c8e: 60da str r2, [r3, #12] 8000c90: 611a str r2, [r3, #16] /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); 8000c92: 2300 movs r3, #0 8000c94: 61bb str r3, [r7, #24] 8000c96: 4b4c ldr r3, [pc, #304] ; (8000dc8 ) 8000c98: 6b1b ldr r3, [r3, #48] ; 0x30 8000c9a: 4a4b ldr r2, [pc, #300] ; (8000dc8 ) 8000c9c: f043 0304 orr.w r3, r3, #4 8000ca0: 6313 str r3, [r2, #48] ; 0x30 8000ca2: 4b49 ldr r3, [pc, #292] ; (8000dc8 ) 8000ca4: 6b1b ldr r3, [r3, #48] ; 0x30 8000ca6: f003 0304 and.w r3, r3, #4 8000caa: 61bb str r3, [r7, #24] 8000cac: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOH_CLK_ENABLE(); 8000cae: 2300 movs r3, #0 8000cb0: 617b str r3, [r7, #20] 8000cb2: 4b45 ldr r3, [pc, #276] ; (8000dc8 ) 8000cb4: 6b1b ldr r3, [r3, #48] ; 0x30 8000cb6: 4a44 ldr r2, [pc, #272] ; (8000dc8 ) 8000cb8: f043 0380 orr.w r3, r3, #128 ; 0x80 8000cbc: 6313 str r3, [r2, #48] ; 0x30 8000cbe: 4b42 ldr r3, [pc, #264] ; (8000dc8 ) 8000cc0: 6b1b ldr r3, [r3, #48] ; 0x30 8000cc2: f003 0380 and.w r3, r3, #128 ; 0x80 8000cc6: 617b str r3, [r7, #20] 8000cc8: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 8000cca: 2300 movs r3, #0 8000ccc: 613b str r3, [r7, #16] 8000cce: 4b3e ldr r3, [pc, #248] ; (8000dc8 ) 8000cd0: 6b1b ldr r3, [r3, #48] ; 0x30 8000cd2: 4a3d ldr r2, [pc, #244] ; (8000dc8 ) 8000cd4: f043 0301 orr.w r3, r3, #1 8000cd8: 6313 str r3, [r2, #48] ; 0x30 8000cda: 4b3b ldr r3, [pc, #236] ; (8000dc8 ) 8000cdc: 6b1b ldr r3, [r3, #48] ; 0x30 8000cde: f003 0301 and.w r3, r3, #1 8000ce2: 613b str r3, [r7, #16] 8000ce4: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 8000ce6: 2300 movs r3, #0 8000ce8: 60fb str r3, [r7, #12] 8000cea: 4b37 ldr r3, [pc, #220] ; (8000dc8 ) 8000cec: 6b1b ldr r3, [r3, #48] ; 0x30 8000cee: 4a36 ldr r2, [pc, #216] ; (8000dc8 ) 8000cf0: f043 0302 orr.w r3, r3, #2 8000cf4: 6313 str r3, [r2, #48] ; 0x30 8000cf6: 4b34 ldr r3, [pc, #208] ; (8000dc8 ) 8000cf8: 6b1b ldr r3, [r3, #48] ; 0x30 8000cfa: f003 0302 and.w r3, r3, #2 8000cfe: 60fb str r3, [r7, #12] 8000d00: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOD_CLK_ENABLE(); 8000d02: 2300 movs r3, #0 8000d04: 60bb str r3, [r7, #8] 8000d06: 4b30 ldr r3, [pc, #192] ; (8000dc8 ) 8000d08: 6b1b ldr r3, [r3, #48] ; 0x30 8000d0a: 4a2f ldr r2, [pc, #188] ; (8000dc8 ) 8000d0c: f043 0308 orr.w r3, r3, #8 8000d10: 6313 str r3, [r2, #48] ; 0x30 8000d12: 4b2d ldr r3, [pc, #180] ; (8000dc8 ) 8000d14: 6b1b ldr r3, [r3, #48] ; 0x30 8000d16: f003 0308 and.w r3, r3, #8 8000d1a: 60bb str r3, [r7, #8] 8000d1c: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOG_CLK_ENABLE(); 8000d1e: 2300 movs r3, #0 8000d20: 607b str r3, [r7, #4] 8000d22: 4b29 ldr r3, [pc, #164] ; (8000dc8 ) 8000d24: 6b1b ldr r3, [r3, #48] ; 0x30 8000d26: 4a28 ldr r2, [pc, #160] ; (8000dc8 ) 8000d28: f043 0340 orr.w r3, r3, #64 ; 0x40 8000d2c: 6313 str r3, [r2, #48] ; 0x30 8000d2e: 4b26 ldr r3, [pc, #152] ; (8000dc8 ) 8000d30: 6b1b ldr r3, [r3, #48] ; 0x30 8000d32: f003 0340 and.w r3, r3, #64 ; 0x40 8000d36: 607b str r3, [r7, #4] 8000d38: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, LD1_Pin|LD3_Pin|LD2_Pin, GPIO_PIN_RESET); 8000d3a: 2200 movs r2, #0 8000d3c: f244 0181 movw r1, #16513 ; 0x4081 8000d40: 4822 ldr r0, [pc, #136] ; (8000dcc ) 8000d42: f001 f9c5 bl 80020d0 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(USB_PowerSwitchOn_GPIO_Port, USB_PowerSwitchOn_Pin, GPIO_PIN_RESET); 8000d46: 2200 movs r2, #0 8000d48: 2140 movs r1, #64 ; 0x40 8000d4a: 4821 ldr r0, [pc, #132] ; (8000dd0 ) 8000d4c: f001 f9c0 bl 80020d0 /*Configure GPIO pin : USER_Btn_Pin */ GPIO_InitStruct.Pin = USER_Btn_Pin; 8000d50: f44f 5300 mov.w r3, #8192 ; 0x2000 8000d54: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; 8000d56: f44f 1388 mov.w r3, #1114112 ; 0x110000 8000d5a: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000d5c: 2300 movs r3, #0 8000d5e: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(USER_Btn_GPIO_Port, &GPIO_InitStruct); 8000d60: f107 031c add.w r3, r7, #28 8000d64: 4619 mov r1, r3 8000d66: 481b ldr r0, [pc, #108] ; (8000dd4 ) 8000d68: f001 f806 bl 8001d78 /*Configure GPIO pins : LD1_Pin LD3_Pin LD2_Pin */ GPIO_InitStruct.Pin = LD1_Pin|LD3_Pin|LD2_Pin; 8000d6c: f244 0381 movw r3, #16513 ; 0x4081 8000d70: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000d72: 2301 movs r3, #1 8000d74: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000d76: 2300 movs r3, #0 8000d78: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000d7a: 2300 movs r3, #0 8000d7c: 62bb str r3, [r7, #40] ; 0x28 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8000d7e: f107 031c add.w r3, r7, #28 8000d82: 4619 mov r1, r3 8000d84: 4811 ldr r0, [pc, #68] ; (8000dcc ) 8000d86: f000 fff7 bl 8001d78 /*Configure GPIO pin : USB_PowerSwitchOn_Pin */ GPIO_InitStruct.Pin = USB_PowerSwitchOn_Pin; 8000d8a: 2340 movs r3, #64 ; 0x40 8000d8c: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000d8e: 2301 movs r3, #1 8000d90: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000d92: 2300 movs r3, #0 8000d94: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000d96: 2300 movs r3, #0 8000d98: 62bb str r3, [r7, #40] ; 0x28 HAL_GPIO_Init(USB_PowerSwitchOn_GPIO_Port, &GPIO_InitStruct); 8000d9a: f107 031c add.w r3, r7, #28 8000d9e: 4619 mov r1, r3 8000da0: 480b ldr r0, [pc, #44] ; (8000dd0 ) 8000da2: f000 ffe9 bl 8001d78 /*Configure GPIO pin : USB_OverCurrent_Pin */ GPIO_InitStruct.Pin = USB_OverCurrent_Pin; 8000da6: 2380 movs r3, #128 ; 0x80 8000da8: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8000daa: 2300 movs r3, #0 8000dac: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000dae: 2300 movs r3, #0 8000db0: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(USB_OverCurrent_GPIO_Port, &GPIO_InitStruct); 8000db2: f107 031c add.w r3, r7, #28 8000db6: 4619 mov r1, r3 8000db8: 4805 ldr r0, [pc, #20] ; (8000dd0 ) 8000dba: f000 ffdd bl 8001d78 /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } 8000dbe: bf00 nop 8000dc0: 3730 adds r7, #48 ; 0x30 8000dc2: 46bd mov sp, r7 8000dc4: bd80 pop {r7, pc} 8000dc6: bf00 nop 8000dc8: 40023800 .word 0x40023800 8000dcc: 40020400 .word 0x40020400 8000dd0: 40021800 .word 0x40021800 8000dd4: 40020800 .word 0x40020800 08000dd8 : /* USER CODE BEGIN 4 */ void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { 8000dd8: b580 push {r7, lr} 8000dda: b082 sub sp, #8 8000ddc: af00 add r7, sp, #0 8000dde: 6078 str r0, [r7, #4] if (huart->Instance == USART3) 8000de0: 687b ldr r3, [r7, #4] 8000de2: 681b ldr r3, [r3, #0] 8000de4: 4a05 ldr r2, [pc, #20] ; (8000dfc ) 8000de6: 4293 cmp r3, r2 8000de8: d104 bne.n 8000df4 HAL_GPIO_WritePin(GPIOB, GPIO_PIN_0, GPIO_PIN_RESET); 8000dea: 2200 movs r2, #0 8000dec: 2101 movs r1, #1 8000dee: 4804 ldr r0, [pc, #16] ; (8000e00 ) 8000df0: f001 f96e bl 80020d0 } 8000df4: bf00 nop 8000df6: 3708 adds r7, #8 8000df8: 46bd mov sp, r7 8000dfa: bd80 pop {r7, pc} 8000dfc: 40004800 .word 0x40004800 8000e00: 40020400 .word 0x40020400 08000e04 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8000e04: b480 push {r7} 8000e06: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting special-purpose register PRIMASK. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8000e08: b672 cpsid i } 8000e0a: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8000e0c: e7fe b.n 8000e0c ... 08000e10 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8000e10: b480 push {r7} 8000e12: b083 sub sp, #12 8000e14: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8000e16: 2300 movs r3, #0 8000e18: 607b str r3, [r7, #4] 8000e1a: 4b10 ldr r3, [pc, #64] ; (8000e5c ) 8000e1c: 6c5b ldr r3, [r3, #68] ; 0x44 8000e1e: 4a0f ldr r2, [pc, #60] ; (8000e5c ) 8000e20: f443 4380 orr.w r3, r3, #16384 ; 0x4000 8000e24: 6453 str r3, [r2, #68] ; 0x44 8000e26: 4b0d ldr r3, [pc, #52] ; (8000e5c ) 8000e28: 6c5b ldr r3, [r3, #68] ; 0x44 8000e2a: f403 4380 and.w r3, r3, #16384 ; 0x4000 8000e2e: 607b str r3, [r7, #4] 8000e30: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 8000e32: 2300 movs r3, #0 8000e34: 603b str r3, [r7, #0] 8000e36: 4b09 ldr r3, [pc, #36] ; (8000e5c ) 8000e38: 6c1b ldr r3, [r3, #64] ; 0x40 8000e3a: 4a08 ldr r2, [pc, #32] ; (8000e5c ) 8000e3c: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8000e40: 6413 str r3, [r2, #64] ; 0x40 8000e42: 4b06 ldr r3, [pc, #24] ; (8000e5c ) 8000e44: 6c1b ldr r3, [r3, #64] ; 0x40 8000e46: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8000e4a: 603b str r3, [r7, #0] 8000e4c: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8000e4e: bf00 nop 8000e50: 370c adds r7, #12 8000e52: 46bd mov sp, r7 8000e54: f85d 7b04 ldr.w r7, [sp], #4 8000e58: 4770 bx lr 8000e5a: bf00 nop 8000e5c: 40023800 .word 0x40023800 08000e60 : * This function configures the hardware resources used in this example * @param heth: ETH handle pointer * @retval None */ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) { 8000e60: b580 push {r7, lr} 8000e62: b08e sub sp, #56 ; 0x38 8000e64: af00 add r7, sp, #0 8000e66: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000e68: f107 0324 add.w r3, r7, #36 ; 0x24 8000e6c: 2200 movs r2, #0 8000e6e: 601a str r2, [r3, #0] 8000e70: 605a str r2, [r3, #4] 8000e72: 609a str r2, [r3, #8] 8000e74: 60da str r2, [r3, #12] 8000e76: 611a str r2, [r3, #16] if(heth->Instance==ETH) 8000e78: 687b ldr r3, [r7, #4] 8000e7a: 681b ldr r3, [r3, #0] 8000e7c: 4a55 ldr r2, [pc, #340] ; (8000fd4 ) 8000e7e: 4293 cmp r3, r2 8000e80: f040 80a4 bne.w 8000fcc { /* USER CODE BEGIN ETH_MspInit 0 */ /* USER CODE END ETH_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ETH_CLK_ENABLE(); 8000e84: 2300 movs r3, #0 8000e86: 623b str r3, [r7, #32] 8000e88: 4b53 ldr r3, [pc, #332] ; (8000fd8 ) 8000e8a: 6b1b ldr r3, [r3, #48] ; 0x30 8000e8c: 4a52 ldr r2, [pc, #328] ; (8000fd8 ) 8000e8e: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000 8000e92: 6313 str r3, [r2, #48] ; 0x30 8000e94: 4b50 ldr r3, [pc, #320] ; (8000fd8 ) 8000e96: 6b1b ldr r3, [r3, #48] ; 0x30 8000e98: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8000e9c: 623b str r3, [r7, #32] 8000e9e: 6a3b ldr r3, [r7, #32] 8000ea0: 2300 movs r3, #0 8000ea2: 61fb str r3, [r7, #28] 8000ea4: 4b4c ldr r3, [pc, #304] ; (8000fd8 ) 8000ea6: 6b1b ldr r3, [r3, #48] ; 0x30 8000ea8: 4a4b ldr r2, [pc, #300] ; (8000fd8 ) 8000eaa: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 8000eae: 6313 str r3, [r2, #48] ; 0x30 8000eb0: 4b49 ldr r3, [pc, #292] ; (8000fd8 ) 8000eb2: 6b1b ldr r3, [r3, #48] ; 0x30 8000eb4: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 8000eb8: 61fb str r3, [r7, #28] 8000eba: 69fb ldr r3, [r7, #28] 8000ebc: 2300 movs r3, #0 8000ebe: 61bb str r3, [r7, #24] 8000ec0: 4b45 ldr r3, [pc, #276] ; (8000fd8 ) 8000ec2: 6b1b ldr r3, [r3, #48] ; 0x30 8000ec4: 4a44 ldr r2, [pc, #272] ; (8000fd8 ) 8000ec6: f043 6300 orr.w r3, r3, #134217728 ; 0x8000000 8000eca: 6313 str r3, [r2, #48] ; 0x30 8000ecc: 4b42 ldr r3, [pc, #264] ; (8000fd8 ) 8000ece: 6b1b ldr r3, [r3, #48] ; 0x30 8000ed0: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 8000ed4: 61bb str r3, [r7, #24] 8000ed6: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOC_CLK_ENABLE(); 8000ed8: 2300 movs r3, #0 8000eda: 617b str r3, [r7, #20] 8000edc: 4b3e ldr r3, [pc, #248] ; (8000fd8 ) 8000ede: 6b1b ldr r3, [r3, #48] ; 0x30 8000ee0: 4a3d ldr r2, [pc, #244] ; (8000fd8 ) 8000ee2: f043 0304 orr.w r3, r3, #4 8000ee6: 6313 str r3, [r2, #48] ; 0x30 8000ee8: 4b3b ldr r3, [pc, #236] ; (8000fd8 ) 8000eea: 6b1b ldr r3, [r3, #48] ; 0x30 8000eec: f003 0304 and.w r3, r3, #4 8000ef0: 617b str r3, [r7, #20] 8000ef2: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 8000ef4: 2300 movs r3, #0 8000ef6: 613b str r3, [r7, #16] 8000ef8: 4b37 ldr r3, [pc, #220] ; (8000fd8 ) 8000efa: 6b1b ldr r3, [r3, #48] ; 0x30 8000efc: 4a36 ldr r2, [pc, #216] ; (8000fd8 ) 8000efe: f043 0301 orr.w r3, r3, #1 8000f02: 6313 str r3, [r2, #48] ; 0x30 8000f04: 4b34 ldr r3, [pc, #208] ; (8000fd8 ) 8000f06: 6b1b ldr r3, [r3, #48] ; 0x30 8000f08: f003 0301 and.w r3, r3, #1 8000f0c: 613b str r3, [r7, #16] 8000f0e: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 8000f10: 2300 movs r3, #0 8000f12: 60fb str r3, [r7, #12] 8000f14: 4b30 ldr r3, [pc, #192] ; (8000fd8 ) 8000f16: 6b1b ldr r3, [r3, #48] ; 0x30 8000f18: 4a2f ldr r2, [pc, #188] ; (8000fd8 ) 8000f1a: f043 0302 orr.w r3, r3, #2 8000f1e: 6313 str r3, [r2, #48] ; 0x30 8000f20: 4b2d ldr r3, [pc, #180] ; (8000fd8 ) 8000f22: 6b1b ldr r3, [r3, #48] ; 0x30 8000f24: f003 0302 and.w r3, r3, #2 8000f28: 60fb str r3, [r7, #12] 8000f2a: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOG_CLK_ENABLE(); 8000f2c: 2300 movs r3, #0 8000f2e: 60bb str r3, [r7, #8] 8000f30: 4b29 ldr r3, [pc, #164] ; (8000fd8 ) 8000f32: 6b1b ldr r3, [r3, #48] ; 0x30 8000f34: 4a28 ldr r2, [pc, #160] ; (8000fd8 ) 8000f36: f043 0340 orr.w r3, r3, #64 ; 0x40 8000f3a: 6313 str r3, [r2, #48] ; 0x30 8000f3c: 4b26 ldr r3, [pc, #152] ; (8000fd8 ) 8000f3e: 6b1b ldr r3, [r3, #48] ; 0x30 8000f40: f003 0340 and.w r3, r3, #64 ; 0x40 8000f44: 60bb str r3, [r7, #8] 8000f46: 68bb ldr r3, [r7, #8] PC5 ------> ETH_RXD1 PB13 ------> ETH_TXD1 PG11 ------> ETH_TX_EN PG13 ------> ETH_TXD0 */ GPIO_InitStruct.Pin = RMII_MDC_Pin|RMII_RXD0_Pin|RMII_RXD1_Pin; 8000f48: 2332 movs r3, #50 ; 0x32 8000f4a: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000f4c: 2302 movs r3, #2 8000f4e: 62bb str r3, [r7, #40] ; 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000f50: 2300 movs r3, #0 8000f52: 62fb str r3, [r7, #44] ; 0x2c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8000f54: 2303 movs r3, #3 8000f56: 633b str r3, [r7, #48] ; 0x30 GPIO_InitStruct.Alternate = GPIO_AF11_ETH; 8000f58: 230b movs r3, #11 8000f5a: 637b str r3, [r7, #52] ; 0x34 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8000f5c: f107 0324 add.w r3, r7, #36 ; 0x24 8000f60: 4619 mov r1, r3 8000f62: 481e ldr r0, [pc, #120] ; (8000fdc ) 8000f64: f000 ff08 bl 8001d78 GPIO_InitStruct.Pin = RMII_REF_CLK_Pin|RMII_MDIO_Pin|RMII_CRS_DV_Pin; 8000f68: 2386 movs r3, #134 ; 0x86 8000f6a: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000f6c: 2302 movs r3, #2 8000f6e: 62bb str r3, [r7, #40] ; 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000f70: 2300 movs r3, #0 8000f72: 62fb str r3, [r7, #44] ; 0x2c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8000f74: 2303 movs r3, #3 8000f76: 633b str r3, [r7, #48] ; 0x30 GPIO_InitStruct.Alternate = GPIO_AF11_ETH; 8000f78: 230b movs r3, #11 8000f7a: 637b str r3, [r7, #52] ; 0x34 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000f7c: f107 0324 add.w r3, r7, #36 ; 0x24 8000f80: 4619 mov r1, r3 8000f82: 4817 ldr r0, [pc, #92] ; (8000fe0 ) 8000f84: f000 fef8 bl 8001d78 GPIO_InitStruct.Pin = RMII_TXD1_Pin; 8000f88: f44f 5300 mov.w r3, #8192 ; 0x2000 8000f8c: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000f8e: 2302 movs r3, #2 8000f90: 62bb str r3, [r7, #40] ; 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000f92: 2300 movs r3, #0 8000f94: 62fb str r3, [r7, #44] ; 0x2c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8000f96: 2303 movs r3, #3 8000f98: 633b str r3, [r7, #48] ; 0x30 GPIO_InitStruct.Alternate = GPIO_AF11_ETH; 8000f9a: 230b movs r3, #11 8000f9c: 637b str r3, [r7, #52] ; 0x34 HAL_GPIO_Init(RMII_TXD1_GPIO_Port, &GPIO_InitStruct); 8000f9e: f107 0324 add.w r3, r7, #36 ; 0x24 8000fa2: 4619 mov r1, r3 8000fa4: 480f ldr r0, [pc, #60] ; (8000fe4 ) 8000fa6: f000 fee7 bl 8001d78 GPIO_InitStruct.Pin = RMII_TX_EN_Pin|RMII_TXD0_Pin; 8000faa: f44f 5320 mov.w r3, #10240 ; 0x2800 8000fae: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000fb0: 2302 movs r3, #2 8000fb2: 62bb str r3, [r7, #40] ; 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000fb4: 2300 movs r3, #0 8000fb6: 62fb str r3, [r7, #44] ; 0x2c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8000fb8: 2303 movs r3, #3 8000fba: 633b str r3, [r7, #48] ; 0x30 GPIO_InitStruct.Alternate = GPIO_AF11_ETH; 8000fbc: 230b movs r3, #11 8000fbe: 637b str r3, [r7, #52] ; 0x34 HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); 8000fc0: f107 0324 add.w r3, r7, #36 ; 0x24 8000fc4: 4619 mov r1, r3 8000fc6: 4808 ldr r0, [pc, #32] ; (8000fe8 ) 8000fc8: f000 fed6 bl 8001d78 /* USER CODE END ETH_MspInit 1 */ } } 8000fcc: bf00 nop 8000fce: 3738 adds r7, #56 ; 0x38 8000fd0: 46bd mov sp, r7 8000fd2: bd80 pop {r7, pc} 8000fd4: 40028000 .word 0x40028000 8000fd8: 40023800 .word 0x40023800 8000fdc: 40020800 .word 0x40020800 8000fe0: 40020000 .word 0x40020000 8000fe4: 40020400 .word 0x40020400 8000fe8: 40021800 .word 0x40021800 08000fec : * This function configures the hardware resources used in this example * @param hrng: RNG handle pointer * @retval None */ void HAL_RNG_MspInit(RNG_HandleTypeDef* hrng) { 8000fec: b480 push {r7} 8000fee: b085 sub sp, #20 8000ff0: af00 add r7, sp, #0 8000ff2: 6078 str r0, [r7, #4] if(hrng->Instance==RNG) 8000ff4: 687b ldr r3, [r7, #4] 8000ff6: 681b ldr r3, [r3, #0] 8000ff8: 4a0b ldr r2, [pc, #44] ; (8001028 ) 8000ffa: 4293 cmp r3, r2 8000ffc: d10d bne.n 800101a { /* USER CODE BEGIN RNG_MspInit 0 */ /* USER CODE END RNG_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_RNG_CLK_ENABLE(); 8000ffe: 2300 movs r3, #0 8001000: 60fb str r3, [r7, #12] 8001002: 4b0a ldr r3, [pc, #40] ; (800102c ) 8001004: 6b5b ldr r3, [r3, #52] ; 0x34 8001006: 4a09 ldr r2, [pc, #36] ; (800102c ) 8001008: f043 0340 orr.w r3, r3, #64 ; 0x40 800100c: 6353 str r3, [r2, #52] ; 0x34 800100e: 4b07 ldr r3, [pc, #28] ; (800102c ) 8001010: 6b5b ldr r3, [r3, #52] ; 0x34 8001012: f003 0340 and.w r3, r3, #64 ; 0x40 8001016: 60fb str r3, [r7, #12] 8001018: 68fb ldr r3, [r7, #12] /* USER CODE END RNG_MspInit 1 */ } } 800101a: bf00 nop 800101c: 3714 adds r7, #20 800101e: 46bd mov sp, r7 8001020: f85d 7b04 ldr.w r7, [sp], #4 8001024: 4770 bx lr 8001026: bf00 nop 8001028: 50060800 .word 0x50060800 800102c: 40023800 .word 0x40023800 08001030 : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { 8001030: b580 push {r7, lr} 8001032: b08a sub sp, #40 ; 0x28 8001034: af00 add r7, sp, #0 8001036: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001038: f107 0314 add.w r3, r7, #20 800103c: 2200 movs r2, #0 800103e: 601a str r2, [r3, #0] 8001040: 605a str r2, [r3, #4] 8001042: 609a str r2, [r3, #8] 8001044: 60da str r2, [r3, #12] 8001046: 611a str r2, [r3, #16] if(huart->Instance==USART3) 8001048: 687b ldr r3, [r7, #4] 800104a: 681b ldr r3, [r3, #0] 800104c: 4a1d ldr r2, [pc, #116] ; (80010c4 ) 800104e: 4293 cmp r3, r2 8001050: d134 bne.n 80010bc { /* USER CODE BEGIN USART3_MspInit 0 */ /* USER CODE END USART3_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART3_CLK_ENABLE(); 8001052: 2300 movs r3, #0 8001054: 613b str r3, [r7, #16] 8001056: 4b1c ldr r3, [pc, #112] ; (80010c8 ) 8001058: 6c1b ldr r3, [r3, #64] ; 0x40 800105a: 4a1b ldr r2, [pc, #108] ; (80010c8 ) 800105c: f443 2380 orr.w r3, r3, #262144 ; 0x40000 8001060: 6413 str r3, [r2, #64] ; 0x40 8001062: 4b19 ldr r3, [pc, #100] ; (80010c8 ) 8001064: 6c1b ldr r3, [r3, #64] ; 0x40 8001066: f403 2380 and.w r3, r3, #262144 ; 0x40000 800106a: 613b str r3, [r7, #16] 800106c: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOD_CLK_ENABLE(); 800106e: 2300 movs r3, #0 8001070: 60fb str r3, [r7, #12] 8001072: 4b15 ldr r3, [pc, #84] ; (80010c8 ) 8001074: 6b1b ldr r3, [r3, #48] ; 0x30 8001076: 4a14 ldr r2, [pc, #80] ; (80010c8 ) 8001078: f043 0308 orr.w r3, r3, #8 800107c: 6313 str r3, [r2, #48] ; 0x30 800107e: 4b12 ldr r3, [pc, #72] ; (80010c8 ) 8001080: 6b1b ldr r3, [r3, #48] ; 0x30 8001082: f003 0308 and.w r3, r3, #8 8001086: 60fb str r3, [r7, #12] 8001088: 68fb ldr r3, [r7, #12] /**USART3 GPIO Configuration PD8 ------> USART3_TX PD9 ------> USART3_RX */ GPIO_InitStruct.Pin = STLK_RX_Pin|STLK_TX_Pin; 800108a: f44f 7340 mov.w r3, #768 ; 0x300 800108e: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001090: 2302 movs r3, #2 8001092: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001094: 2300 movs r3, #0 8001096: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001098: 2303 movs r3, #3 800109a: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF7_USART3; 800109c: 2307 movs r3, #7 800109e: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 80010a0: f107 0314 add.w r3, r7, #20 80010a4: 4619 mov r1, r3 80010a6: 4809 ldr r0, [pc, #36] ; (80010cc ) 80010a8: f000 fe66 bl 8001d78 /* USART3 interrupt Init */ HAL_NVIC_SetPriority(USART3_IRQn, 0, 0); 80010ac: 2200 movs r2, #0 80010ae: 2100 movs r1, #0 80010b0: 2027 movs r0, #39 ; 0x27 80010b2: f000 fa48 bl 8001546 HAL_NVIC_EnableIRQ(USART3_IRQn); 80010b6: 2027 movs r0, #39 ; 0x27 80010b8: f000 fa61 bl 800157e /* USER CODE END USART3_MspInit 1 */ } } 80010bc: bf00 nop 80010be: 3728 adds r7, #40 ; 0x28 80010c0: 46bd mov sp, r7 80010c2: bd80 pop {r7, pc} 80010c4: 40004800 .word 0x40004800 80010c8: 40023800 .word 0x40023800 80010cc: 40020c00 .word 0x40020c00 080010d0 : * This function configures the hardware resources used in this example * @param hpcd: PCD handle pointer * @retval None */ void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd) { 80010d0: b580 push {r7, lr} 80010d2: b08a sub sp, #40 ; 0x28 80010d4: af00 add r7, sp, #0 80010d6: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80010d8: f107 0314 add.w r3, r7, #20 80010dc: 2200 movs r2, #0 80010de: 601a str r2, [r3, #0] 80010e0: 605a str r2, [r3, #4] 80010e2: 609a str r2, [r3, #8] 80010e4: 60da str r2, [r3, #12] 80010e6: 611a str r2, [r3, #16] if(hpcd->Instance==USB_OTG_FS) 80010e8: 687b ldr r3, [r7, #4] 80010ea: 681b ldr r3, [r3, #0] 80010ec: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000 80010f0: d13f bne.n 8001172 { /* USER CODE BEGIN USB_OTG_FS_MspInit 0 */ /* USER CODE END USB_OTG_FS_MspInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 80010f2: 2300 movs r3, #0 80010f4: 613b str r3, [r7, #16] 80010f6: 4b21 ldr r3, [pc, #132] ; (800117c ) 80010f8: 6b1b ldr r3, [r3, #48] ; 0x30 80010fa: 4a20 ldr r2, [pc, #128] ; (800117c ) 80010fc: f043 0301 orr.w r3, r3, #1 8001100: 6313 str r3, [r2, #48] ; 0x30 8001102: 4b1e ldr r3, [pc, #120] ; (800117c ) 8001104: 6b1b ldr r3, [r3, #48] ; 0x30 8001106: f003 0301 and.w r3, r3, #1 800110a: 613b str r3, [r7, #16] 800110c: 693b ldr r3, [r7, #16] PA9 ------> USB_OTG_FS_VBUS PA10 ------> USB_OTG_FS_ID PA11 ------> USB_OTG_FS_DM PA12 ------> USB_OTG_FS_DP */ GPIO_InitStruct.Pin = USB_SOF_Pin|USB_ID_Pin|USB_DM_Pin|USB_DP_Pin; 800110e: f44f 53e8 mov.w r3, #7424 ; 0x1d00 8001112: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001114: 2302 movs r3, #2 8001116: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001118: 2300 movs r3, #0 800111a: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 800111c: 2303 movs r3, #3 800111e: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; 8001120: 230a movs r3, #10 8001122: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001124: f107 0314 add.w r3, r7, #20 8001128: 4619 mov r1, r3 800112a: 4815 ldr r0, [pc, #84] ; (8001180 ) 800112c: f000 fe24 bl 8001d78 GPIO_InitStruct.Pin = USB_VBUS_Pin; 8001130: f44f 7300 mov.w r3, #512 ; 0x200 8001134: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8001136: 2300 movs r3, #0 8001138: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800113a: 2300 movs r3, #0 800113c: 61fb str r3, [r7, #28] HAL_GPIO_Init(USB_VBUS_GPIO_Port, &GPIO_InitStruct); 800113e: f107 0314 add.w r3, r7, #20 8001142: 4619 mov r1, r3 8001144: 480e ldr r0, [pc, #56] ; (8001180 ) 8001146: f000 fe17 bl 8001d78 /* Peripheral clock enable */ __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); 800114a: 4b0c ldr r3, [pc, #48] ; (800117c ) 800114c: 6b5b ldr r3, [r3, #52] ; 0x34 800114e: 4a0b ldr r2, [pc, #44] ; (800117c ) 8001150: f043 0380 orr.w r3, r3, #128 ; 0x80 8001154: 6353 str r3, [r2, #52] ; 0x34 8001156: 2300 movs r3, #0 8001158: 60fb str r3, [r7, #12] 800115a: 4b08 ldr r3, [pc, #32] ; (800117c ) 800115c: 6c5b ldr r3, [r3, #68] ; 0x44 800115e: 4a07 ldr r2, [pc, #28] ; (800117c ) 8001160: f443 4380 orr.w r3, r3, #16384 ; 0x4000 8001164: 6453 str r3, [r2, #68] ; 0x44 8001166: 4b05 ldr r3, [pc, #20] ; (800117c ) 8001168: 6c5b ldr r3, [r3, #68] ; 0x44 800116a: f403 4380 and.w r3, r3, #16384 ; 0x4000 800116e: 60fb str r3, [r7, #12] 8001170: 68fb ldr r3, [r7, #12] /* USER CODE END USB_OTG_FS_MspInit 1 */ } } 8001172: bf00 nop 8001174: 3728 adds r7, #40 ; 0x28 8001176: 46bd mov sp, r7 8001178: bd80 pop {r7, pc} 800117a: bf00 nop 800117c: 40023800 .word 0x40023800 8001180: 40020000 .word 0x40020000 08001184 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8001184: b480 push {r7} 8001186: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8001188: e7fe b.n 8001188 0800118a : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 800118a: b480 push {r7} 800118c: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 800118e: e7fe b.n 800118e 08001190 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8001190: b480 push {r7} 8001192: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8001194: e7fe b.n 8001194 08001196 : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 8001196: b480 push {r7} 8001198: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 800119a: e7fe b.n 800119a 0800119c : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 800119c: b480 push {r7} 800119e: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 80011a0: e7fe b.n 80011a0 080011a2 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 80011a2: b480 push {r7} 80011a4: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 80011a6: bf00 nop 80011a8: 46bd mov sp, r7 80011aa: f85d 7b04 ldr.w r7, [sp], #4 80011ae: 4770 bx lr 080011b0 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 80011b0: b480 push {r7} 80011b2: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 80011b4: bf00 nop 80011b6: 46bd mov sp, r7 80011b8: f85d 7b04 ldr.w r7, [sp], #4 80011bc: 4770 bx lr 080011be : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 80011be: b480 push {r7} 80011c0: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 80011c2: bf00 nop 80011c4: 46bd mov sp, r7 80011c6: f85d 7b04 ldr.w r7, [sp], #4 80011ca: 4770 bx lr 080011cc : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 80011cc: b580 push {r7, lr} 80011ce: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 80011d0: f000 f89a bl 8001308 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 80011d4: bf00 nop 80011d6: bd80 pop {r7, pc} 080011d8 : /** * @brief This function handles USART3 global interrupt. */ void USART3_IRQHandler(void) { 80011d8: b580 push {r7, lr} 80011da: af00 add r7, sp, #0 /* USER CODE BEGIN USART3_IRQn 0 */ /* USER CODE END USART3_IRQn 0 */ HAL_UART_IRQHandler(&huart3); 80011dc: 4802 ldr r0, [pc, #8] ; (80011e8 ) 80011de: f001 feed bl 8002fbc /* USER CODE BEGIN USART3_IRQn 1 */ /* USER CODE END USART3_IRQn 1 */ } 80011e2: bf00 nop 80011e4: bd80 pop {r7, pc} 80011e6: bf00 nop 80011e8: 20000b24 .word 0x20000b24 080011ec : * configuration. * @param None * @retval None */ void SystemInit(void) { 80011ec: b480 push {r7} 80011ee: af00 add r7, sp, #0 /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ 80011f0: 4b06 ldr r3, [pc, #24] ; (800120c ) 80011f2: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 80011f6: 4a05 ldr r2, [pc, #20] ; (800120c ) 80011f8: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 80011fc: f8c2 3088 str.w r3, [r2, #136] ; 0x88 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #endif /* USER_VECT_TAB_ADDRESS */ } 8001200: bf00 nop 8001202: 46bd mov sp, r7 8001204: f85d 7b04 ldr.w r7, [sp], #4 8001208: 4770 bx lr 800120a: bf00 nop 800120c: e000ed00 .word 0xe000ed00 08001210 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ 8001210: f8df d034 ldr.w sp, [pc, #52] ; 8001248 /* Call the clock system initialization function.*/ bl SystemInit 8001214: f7ff ffea bl 80011ec /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8001218: 480c ldr r0, [pc, #48] ; (800124c ) ldr r1, =_edata 800121a: 490d ldr r1, [pc, #52] ; (8001250 ) ldr r2, =_sidata 800121c: 4a0d ldr r2, [pc, #52] ; (8001254 ) movs r3, #0 800121e: 2300 movs r3, #0 b LoopCopyDataInit 8001220: e002 b.n 8001228 08001222 : CopyDataInit: ldr r4, [r2, r3] 8001222: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8001224: 50c4 str r4, [r0, r3] adds r3, r3, #4 8001226: 3304 adds r3, #4 08001228 : LoopCopyDataInit: adds r4, r0, r3 8001228: 18c4 adds r4, r0, r3 cmp r4, r1 800122a: 428c cmp r4, r1 bcc CopyDataInit 800122c: d3f9 bcc.n 8001222 /* Zero fill the bss segment. */ ldr r2, =_sbss 800122e: 4a0a ldr r2, [pc, #40] ; (8001258 ) ldr r4, =_ebss 8001230: 4c0a ldr r4, [pc, #40] ; (800125c ) movs r3, #0 8001232: 2300 movs r3, #0 b LoopFillZerobss 8001234: e001 b.n 800123a 08001236 : FillZerobss: str r3, [r2] 8001236: 6013 str r3, [r2, #0] adds r2, r2, #4 8001238: 3204 adds r2, #4 0800123a : LoopFillZerobss: cmp r2, r4 800123a: 42a2 cmp r2, r4 bcc FillZerobss 800123c: d3fb bcc.n 8001236 /* Call static constructors */ bl __libc_init_array 800123e: f003 f8fd bl 800443c <__libc_init_array> /* Call the application's entry point.*/ bl main 8001242: f7ff fb93 bl 800096c

bx lr 8001246: 4770 bx lr ldr sp, =_estack /* set stack pointer */ 8001248: 20030000 .word 0x20030000 ldr r0, =_sdata 800124c: 20000000 .word 0x20000000 ldr r1, =_edata 8001250: 200006c8 .word 0x200006c8 ldr r2, =_sidata 8001254: 08004594 .word 0x08004594 ldr r2, =_sbss 8001258: 200006c8 .word 0x200006c8 ldr r4, =_ebss 800125c: 200011f4 .word 0x200011f4 08001260 : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8001260: e7fe b.n 8001260 ... 08001264 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8001264: b580 push {r7, lr} 8001266: af00 add r7, sp, #0 /* Configure Flash prefetch, Instruction cache, Data cache */ #if (INSTRUCTION_CACHE_ENABLE != 0U) __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); 8001268: 4b0e ldr r3, [pc, #56] ; (80012a4 ) 800126a: 681b ldr r3, [r3, #0] 800126c: 4a0d ldr r2, [pc, #52] ; (80012a4 ) 800126e: f443 7300 orr.w r3, r3, #512 ; 0x200 8001272: 6013 str r3, [r2, #0] #endif /* INSTRUCTION_CACHE_ENABLE */ #if (DATA_CACHE_ENABLE != 0U) __HAL_FLASH_DATA_CACHE_ENABLE(); 8001274: 4b0b ldr r3, [pc, #44] ; (80012a4 ) 8001276: 681b ldr r3, [r3, #0] 8001278: 4a0a ldr r2, [pc, #40] ; (80012a4 ) 800127a: f443 6380 orr.w r3, r3, #1024 ; 0x400 800127e: 6013 str r3, [r2, #0] #endif /* DATA_CACHE_ENABLE */ #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8001280: 4b08 ldr r3, [pc, #32] ; (80012a4 ) 8001282: 681b ldr r3, [r3, #0] 8001284: 4a07 ldr r2, [pc, #28] ; (80012a4 ) 8001286: f443 7380 orr.w r3, r3, #256 ; 0x100 800128a: 6013 str r3, [r2, #0] #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 800128c: 2003 movs r0, #3 800128e: f000 f94f bl 8001530 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 8001292: 2000 movs r0, #0 8001294: f000 f808 bl 80012a8 /* Init the low level hardware */ HAL_MspInit(); 8001298: f7ff fdba bl 8000e10 /* Return function status */ return HAL_OK; 800129c: 2300 movs r3, #0 } 800129e: 4618 mov r0, r3 80012a0: bd80 pop {r7, pc} 80012a2: bf00 nop 80012a4: 40023c00 .word 0x40023c00 080012a8 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 80012a8: b580 push {r7, lr} 80012aa: b082 sub sp, #8 80012ac: af00 add r7, sp, #0 80012ae: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 80012b0: 4b12 ldr r3, [pc, #72] ; (80012fc ) 80012b2: 681a ldr r2, [r3, #0] 80012b4: 4b12 ldr r3, [pc, #72] ; (8001300 ) 80012b6: 781b ldrb r3, [r3, #0] 80012b8: 4619 mov r1, r3 80012ba: f44f 737a mov.w r3, #1000 ; 0x3e8 80012be: fbb3 f3f1 udiv r3, r3, r1 80012c2: fbb2 f3f3 udiv r3, r2, r3 80012c6: 4618 mov r0, r3 80012c8: f000 f967 bl 800159a 80012cc: 4603 mov r3, r0 80012ce: 2b00 cmp r3, #0 80012d0: d001 beq.n 80012d6 { return HAL_ERROR; 80012d2: 2301 movs r3, #1 80012d4: e00e b.n 80012f4 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 80012d6: 687b ldr r3, [r7, #4] 80012d8: 2b0f cmp r3, #15 80012da: d80a bhi.n 80012f2 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 80012dc: 2200 movs r2, #0 80012de: 6879 ldr r1, [r7, #4] 80012e0: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 80012e4: f000 f92f bl 8001546 uwTickPrio = TickPriority; 80012e8: 4a06 ldr r2, [pc, #24] ; (8001304 ) 80012ea: 687b ldr r3, [r7, #4] 80012ec: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 80012ee: 2300 movs r3, #0 80012f0: e000 b.n 80012f4 return HAL_ERROR; 80012f2: 2301 movs r3, #1 } 80012f4: 4618 mov r0, r3 80012f6: 3708 adds r7, #8 80012f8: 46bd mov sp, r7 80012fa: bd80 pop {r7, pc} 80012fc: 200006b8 .word 0x200006b8 8001300: 200006c0 .word 0x200006c0 8001304: 200006bc .word 0x200006bc 08001308 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8001308: b480 push {r7} 800130a: af00 add r7, sp, #0 uwTick += uwTickFreq; 800130c: 4b06 ldr r3, [pc, #24] ; (8001328 ) 800130e: 781b ldrb r3, [r3, #0] 8001310: 461a mov r2, r3 8001312: 4b06 ldr r3, [pc, #24] ; (800132c ) 8001314: 681b ldr r3, [r3, #0] 8001316: 4413 add r3, r2 8001318: 4a04 ldr r2, [pc, #16] ; (800132c ) 800131a: 6013 str r3, [r2, #0] } 800131c: bf00 nop 800131e: 46bd mov sp, r7 8001320: f85d 7b04 ldr.w r7, [sp], #4 8001324: 4770 bx lr 8001326: bf00 nop 8001328: 200006c0 .word 0x200006c0 800132c: 20001058 .word 0x20001058 08001330 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8001330: b480 push {r7} 8001332: af00 add r7, sp, #0 return uwTick; 8001334: 4b03 ldr r3, [pc, #12] ; (8001344 ) 8001336: 681b ldr r3, [r3, #0] } 8001338: 4618 mov r0, r3 800133a: 46bd mov sp, r7 800133c: f85d 7b04 ldr.w r7, [sp], #4 8001340: 4770 bx lr 8001342: bf00 nop 8001344: 20001058 .word 0x20001058 08001348 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 8001348: b580 push {r7, lr} 800134a: b084 sub sp, #16 800134c: af00 add r7, sp, #0 800134e: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8001350: f7ff ffee bl 8001330 8001354: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 8001356: 687b ldr r3, [r7, #4] 8001358: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 800135a: 68fb ldr r3, [r7, #12] 800135c: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff 8001360: d005 beq.n 800136e { wait += (uint32_t)(uwTickFreq); 8001362: 4b0a ldr r3, [pc, #40] ; (800138c ) 8001364: 781b ldrb r3, [r3, #0] 8001366: 461a mov r2, r3 8001368: 68fb ldr r3, [r7, #12] 800136a: 4413 add r3, r2 800136c: 60fb str r3, [r7, #12] } while((HAL_GetTick() - tickstart) < wait) 800136e: bf00 nop 8001370: f7ff ffde bl 8001330 8001374: 4602 mov r2, r0 8001376: 68bb ldr r3, [r7, #8] 8001378: 1ad3 subs r3, r2, r3 800137a: 68fa ldr r2, [r7, #12] 800137c: 429a cmp r2, r3 800137e: d8f7 bhi.n 8001370 { } } 8001380: bf00 nop 8001382: bf00 nop 8001384: 3710 adds r7, #16 8001386: 46bd mov sp, r7 8001388: bd80 pop {r7, pc} 800138a: bf00 nop 800138c: 200006c0 .word 0x200006c0 08001390 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001390: b480 push {r7} 8001392: b085 sub sp, #20 8001394: af00 add r7, sp, #0 8001396: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8001398: 687b ldr r3, [r7, #4] 800139a: f003 0307 and.w r3, r3, #7 800139e: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 80013a0: 4b0c ldr r3, [pc, #48] ; (80013d4 <__NVIC_SetPriorityGrouping+0x44>) 80013a2: 68db ldr r3, [r3, #12] 80013a4: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 80013a6: 68ba ldr r2, [r7, #8] 80013a8: f64f 03ff movw r3, #63743 ; 0xf8ff 80013ac: 4013 ands r3, r2 80013ae: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 80013b0: 68fb ldr r3, [r7, #12] 80013b2: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 80013b4: 68bb ldr r3, [r7, #8] 80013b6: 4313 orrs r3, r2 reg_value = (reg_value | 80013b8: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 80013bc: f443 3300 orr.w r3, r3, #131072 ; 0x20000 80013c0: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 80013c2: 4a04 ldr r2, [pc, #16] ; (80013d4 <__NVIC_SetPriorityGrouping+0x44>) 80013c4: 68bb ldr r3, [r7, #8] 80013c6: 60d3 str r3, [r2, #12] } 80013c8: bf00 nop 80013ca: 3714 adds r7, #20 80013cc: 46bd mov sp, r7 80013ce: f85d 7b04 ldr.w r7, [sp], #4 80013d2: 4770 bx lr 80013d4: e000ed00 .word 0xe000ed00 080013d8 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 80013d8: b480 push {r7} 80013da: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 80013dc: 4b04 ldr r3, [pc, #16] ; (80013f0 <__NVIC_GetPriorityGrouping+0x18>) 80013de: 68db ldr r3, [r3, #12] 80013e0: 0a1b lsrs r3, r3, #8 80013e2: f003 0307 and.w r3, r3, #7 } 80013e6: 4618 mov r0, r3 80013e8: 46bd mov sp, r7 80013ea: f85d 7b04 ldr.w r7, [sp], #4 80013ee: 4770 bx lr 80013f0: e000ed00 .word 0xe000ed00 080013f4 <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 80013f4: b480 push {r7} 80013f6: b083 sub sp, #12 80013f8: af00 add r7, sp, #0 80013fa: 4603 mov r3, r0 80013fc: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 80013fe: f997 3007 ldrsb.w r3, [r7, #7] 8001402: 2b00 cmp r3, #0 8001404: db0b blt.n 800141e <__NVIC_EnableIRQ+0x2a> { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8001406: 79fb ldrb r3, [r7, #7] 8001408: f003 021f and.w r2, r3, #31 800140c: 4907 ldr r1, [pc, #28] ; (800142c <__NVIC_EnableIRQ+0x38>) 800140e: f997 3007 ldrsb.w r3, [r7, #7] 8001412: 095b lsrs r3, r3, #5 8001414: 2001 movs r0, #1 8001416: fa00 f202 lsl.w r2, r0, r2 800141a: f841 2023 str.w r2, [r1, r3, lsl #2] __COMPILER_BARRIER(); } } 800141e: bf00 nop 8001420: 370c adds r7, #12 8001422: 46bd mov sp, r7 8001424: f85d 7b04 ldr.w r7, [sp], #4 8001428: 4770 bx lr 800142a: bf00 nop 800142c: e000e100 .word 0xe000e100 08001430 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8001430: b480 push {r7} 8001432: b083 sub sp, #12 8001434: af00 add r7, sp, #0 8001436: 4603 mov r3, r0 8001438: 6039 str r1, [r7, #0] 800143a: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 800143c: f997 3007 ldrsb.w r3, [r7, #7] 8001440: 2b00 cmp r3, #0 8001442: db0a blt.n 800145a <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001444: 683b ldr r3, [r7, #0] 8001446: b2da uxtb r2, r3 8001448: 490c ldr r1, [pc, #48] ; (800147c <__NVIC_SetPriority+0x4c>) 800144a: f997 3007 ldrsb.w r3, [r7, #7] 800144e: 0112 lsls r2, r2, #4 8001450: b2d2 uxtb r2, r2 8001452: 440b add r3, r1 8001454: f883 2300 strb.w r2, [r3, #768] ; 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8001458: e00a b.n 8001470 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800145a: 683b ldr r3, [r7, #0] 800145c: b2da uxtb r2, r3 800145e: 4908 ldr r1, [pc, #32] ; (8001480 <__NVIC_SetPriority+0x50>) 8001460: 79fb ldrb r3, [r7, #7] 8001462: f003 030f and.w r3, r3, #15 8001466: 3b04 subs r3, #4 8001468: 0112 lsls r2, r2, #4 800146a: b2d2 uxtb r2, r2 800146c: 440b add r3, r1 800146e: 761a strb r2, [r3, #24] } 8001470: bf00 nop 8001472: 370c adds r7, #12 8001474: 46bd mov sp, r7 8001476: f85d 7b04 ldr.w r7, [sp], #4 800147a: 4770 bx lr 800147c: e000e100 .word 0xe000e100 8001480: e000ed00 .word 0xe000ed00 08001484 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 8001484: b480 push {r7} 8001486: b089 sub sp, #36 ; 0x24 8001488: af00 add r7, sp, #0 800148a: 60f8 str r0, [r7, #12] 800148c: 60b9 str r1, [r7, #8] 800148e: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8001490: 68fb ldr r3, [r7, #12] 8001492: f003 0307 and.w r3, r3, #7 8001496: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8001498: 69fb ldr r3, [r7, #28] 800149a: f1c3 0307 rsb r3, r3, #7 800149e: 2b04 cmp r3, #4 80014a0: bf28 it cs 80014a2: 2304 movcs r3, #4 80014a4: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 80014a6: 69fb ldr r3, [r7, #28] 80014a8: 3304 adds r3, #4 80014aa: 2b06 cmp r3, #6 80014ac: d902 bls.n 80014b4 80014ae: 69fb ldr r3, [r7, #28] 80014b0: 3b03 subs r3, #3 80014b2: e000 b.n 80014b6 80014b4: 2300 movs r3, #0 80014b6: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80014b8: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff 80014bc: 69bb ldr r3, [r7, #24] 80014be: fa02 f303 lsl.w r3, r2, r3 80014c2: 43da mvns r2, r3 80014c4: 68bb ldr r3, [r7, #8] 80014c6: 401a ands r2, r3 80014c8: 697b ldr r3, [r7, #20] 80014ca: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 80014cc: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff 80014d0: 697b ldr r3, [r7, #20] 80014d2: fa01 f303 lsl.w r3, r1, r3 80014d6: 43d9 mvns r1, r3 80014d8: 687b ldr r3, [r7, #4] 80014da: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80014dc: 4313 orrs r3, r2 ); } 80014de: 4618 mov r0, r3 80014e0: 3724 adds r7, #36 ; 0x24 80014e2: 46bd mov sp, r7 80014e4: f85d 7b04 ldr.w r7, [sp], #4 80014e8: 4770 bx lr ... 080014ec : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 80014ec: b580 push {r7, lr} 80014ee: b082 sub sp, #8 80014f0: af00 add r7, sp, #0 80014f2: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 80014f4: 687b ldr r3, [r7, #4] 80014f6: 3b01 subs r3, #1 80014f8: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 80014fc: d301 bcc.n 8001502 { return (1UL); /* Reload value impossible */ 80014fe: 2301 movs r3, #1 8001500: e00f b.n 8001522 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8001502: 4a0a ldr r2, [pc, #40] ; (800152c ) 8001504: 687b ldr r3, [r7, #4] 8001506: 3b01 subs r3, #1 8001508: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 800150a: 210f movs r1, #15 800150c: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8001510: f7ff ff8e bl 8001430 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8001514: 4b05 ldr r3, [pc, #20] ; (800152c ) 8001516: 2200 movs r2, #0 8001518: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 800151a: 4b04 ldr r3, [pc, #16] ; (800152c ) 800151c: 2207 movs r2, #7 800151e: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8001520: 2300 movs r3, #0 } 8001522: 4618 mov r0, r3 8001524: 3708 adds r7, #8 8001526: 46bd mov sp, r7 8001528: bd80 pop {r7, pc} 800152a: bf00 nop 800152c: e000e010 .word 0xe000e010 08001530 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001530: b580 push {r7, lr} 8001532: b082 sub sp, #8 8001534: af00 add r7, sp, #0 8001536: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8001538: 6878 ldr r0, [r7, #4] 800153a: f7ff ff29 bl 8001390 <__NVIC_SetPriorityGrouping> } 800153e: bf00 nop 8001540: 3708 adds r7, #8 8001542: 46bd mov sp, r7 8001544: bd80 pop {r7, pc} 08001546 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8001546: b580 push {r7, lr} 8001548: b086 sub sp, #24 800154a: af00 add r7, sp, #0 800154c: 4603 mov r3, r0 800154e: 60b9 str r1, [r7, #8] 8001550: 607a str r2, [r7, #4] 8001552: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 8001554: 2300 movs r3, #0 8001556: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8001558: f7ff ff3e bl 80013d8 <__NVIC_GetPriorityGrouping> 800155c: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 800155e: 687a ldr r2, [r7, #4] 8001560: 68b9 ldr r1, [r7, #8] 8001562: 6978 ldr r0, [r7, #20] 8001564: f7ff ff8e bl 8001484 8001568: 4602 mov r2, r0 800156a: f997 300f ldrsb.w r3, [r7, #15] 800156e: 4611 mov r1, r2 8001570: 4618 mov r0, r3 8001572: f7ff ff5d bl 8001430 <__NVIC_SetPriority> } 8001576: bf00 nop 8001578: 3718 adds r7, #24 800157a: 46bd mov sp, r7 800157c: bd80 pop {r7, pc} 0800157e : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 800157e: b580 push {r7, lr} 8001580: b082 sub sp, #8 8001582: af00 add r7, sp, #0 8001584: 4603 mov r3, r0 8001586: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 8001588: f997 3007 ldrsb.w r3, [r7, #7] 800158c: 4618 mov r0, r3 800158e: f7ff ff31 bl 80013f4 <__NVIC_EnableIRQ> } 8001592: bf00 nop 8001594: 3708 adds r7, #8 8001596: 46bd mov sp, r7 8001598: bd80 pop {r7, pc} 0800159a : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 800159a: b580 push {r7, lr} 800159c: b082 sub sp, #8 800159e: af00 add r7, sp, #0 80015a0: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 80015a2: 6878 ldr r0, [r7, #4] 80015a4: f7ff ffa2 bl 80014ec 80015a8: 4603 mov r3, r0 } 80015aa: 4618 mov r0, r3 80015ac: 3708 adds r7, #8 80015ae: 46bd mov sp, r7 80015b0: bd80 pop {r7, pc} 080015b2 : * and the Stream will be effectively disabled only after the transfer of * this single data is finished. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 80015b2: b580 push {r7, lr} 80015b4: b084 sub sp, #16 80015b6: af00 add r7, sp, #0 80015b8: 6078 str r0, [r7, #4] /* calculate DMA base and stream number */ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; 80015ba: 687b ldr r3, [r7, #4] 80015bc: 6d9b ldr r3, [r3, #88] ; 0x58 80015be: 60fb str r3, [r7, #12] uint32_t tickstart = HAL_GetTick(); 80015c0: f7ff feb6 bl 8001330 80015c4: 60b8 str r0, [r7, #8] if(hdma->State != HAL_DMA_STATE_BUSY) 80015c6: 687b ldr r3, [r7, #4] 80015c8: f893 3035 ldrb.w r3, [r3, #53] ; 0x35 80015cc: b2db uxtb r3, r3 80015ce: 2b02 cmp r3, #2 80015d0: d008 beq.n 80015e4 { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 80015d2: 687b ldr r3, [r7, #4] 80015d4: 2280 movs r2, #128 ; 0x80 80015d6: 655a str r2, [r3, #84] ; 0x54 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80015d8: 687b ldr r3, [r7, #4] 80015da: 2200 movs r2, #0 80015dc: f883 2034 strb.w r2, [r3, #52] ; 0x34 return HAL_ERROR; 80015e0: 2301 movs r3, #1 80015e2: e052 b.n 800168a } else { /* Disable all the transfer interrupts */ hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); 80015e4: 687b ldr r3, [r7, #4] 80015e6: 681b ldr r3, [r3, #0] 80015e8: 681a ldr r2, [r3, #0] 80015ea: 687b ldr r3, [r7, #4] 80015ec: 681b ldr r3, [r3, #0] 80015ee: f022 0216 bic.w r2, r2, #22 80015f2: 601a str r2, [r3, #0] hdma->Instance->FCR &= ~(DMA_IT_FE); 80015f4: 687b ldr r3, [r7, #4] 80015f6: 681b ldr r3, [r3, #0] 80015f8: 695a ldr r2, [r3, #20] 80015fa: 687b ldr r3, [r7, #4] 80015fc: 681b ldr r3, [r3, #0] 80015fe: f022 0280 bic.w r2, r2, #128 ; 0x80 8001602: 615a str r2, [r3, #20] if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) 8001604: 687b ldr r3, [r7, #4] 8001606: 6c1b ldr r3, [r3, #64] ; 0x40 8001608: 2b00 cmp r3, #0 800160a: d103 bne.n 8001614 800160c: 687b ldr r3, [r7, #4] 800160e: 6c9b ldr r3, [r3, #72] ; 0x48 8001610: 2b00 cmp r3, #0 8001612: d007 beq.n 8001624 { hdma->Instance->CR &= ~(DMA_IT_HT); 8001614: 687b ldr r3, [r7, #4] 8001616: 681b ldr r3, [r3, #0] 8001618: 681a ldr r2, [r3, #0] 800161a: 687b ldr r3, [r7, #4] 800161c: 681b ldr r3, [r3, #0] 800161e: f022 0208 bic.w r2, r2, #8 8001622: 601a str r2, [r3, #0] } /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 8001624: 687b ldr r3, [r7, #4] 8001626: 681b ldr r3, [r3, #0] 8001628: 681a ldr r2, [r3, #0] 800162a: 687b ldr r3, [r7, #4] 800162c: 681b ldr r3, [r3, #0] 800162e: f022 0201 bic.w r2, r2, #1 8001632: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) 8001634: e013 b.n 800165e { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 8001636: f7ff fe7b bl 8001330 800163a: 4602 mov r2, r0 800163c: 68bb ldr r3, [r7, #8] 800163e: 1ad3 subs r3, r2, r3 8001640: 2b05 cmp r3, #5 8001642: d90c bls.n 800165e { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 8001644: 687b ldr r3, [r7, #4] 8001646: 2220 movs r2, #32 8001648: 655a str r2, [r3, #84] ; 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_TIMEOUT; 800164a: 687b ldr r3, [r7, #4] 800164c: 2203 movs r2, #3 800164e: f883 2035 strb.w r2, [r3, #53] ; 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8001652: 687b ldr r3, [r7, #4] 8001654: 2200 movs r2, #0 8001656: f883 2034 strb.w r2, [r3, #52] ; 0x34 return HAL_TIMEOUT; 800165a: 2303 movs r3, #3 800165c: e015 b.n 800168a while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) 800165e: 687b ldr r3, [r7, #4] 8001660: 681b ldr r3, [r3, #0] 8001662: 681b ldr r3, [r3, #0] 8001664: f003 0301 and.w r3, r3, #1 8001668: 2b00 cmp r3, #0 800166a: d1e4 bne.n 8001636 } } /* Clear all interrupt flags at correct offset within the register */ regs->IFCR = 0x3FU << hdma->StreamIndex; 800166c: 687b ldr r3, [r7, #4] 800166e: 6ddb ldr r3, [r3, #92] ; 0x5c 8001670: 223f movs r2, #63 ; 0x3f 8001672: 409a lsls r2, r3 8001674: 68fb ldr r3, [r7, #12] 8001676: 609a str r2, [r3, #8] /* Change the DMA state*/ hdma->State = HAL_DMA_STATE_READY; 8001678: 687b ldr r3, [r7, #4] 800167a: 2201 movs r2, #1 800167c: f883 2035 strb.w r2, [r3, #53] ; 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8001680: 687b ldr r3, [r7, #4] 8001682: 2200 movs r2, #0 8001684: f883 2034 strb.w r2, [r3, #52] ; 0x34 } return HAL_OK; 8001688: 2300 movs r3, #0 } 800168a: 4618 mov r0, r3 800168c: 3710 adds r7, #16 800168e: 46bd mov sp, r7 8001690: bd80 pop {r7, pc} 08001692 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 8001692: b480 push {r7} 8001694: b083 sub sp, #12 8001696: af00 add r7, sp, #0 8001698: 6078 str r0, [r7, #4] if(hdma->State != HAL_DMA_STATE_BUSY) 800169a: 687b ldr r3, [r7, #4] 800169c: f893 3035 ldrb.w r3, [r3, #53] ; 0x35 80016a0: b2db uxtb r3, r3 80016a2: 2b02 cmp r3, #2 80016a4: d004 beq.n 80016b0 { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 80016a6: 687b ldr r3, [r7, #4] 80016a8: 2280 movs r2, #128 ; 0x80 80016aa: 655a str r2, [r3, #84] ; 0x54 return HAL_ERROR; 80016ac: 2301 movs r3, #1 80016ae: e00c b.n 80016ca } else { /* Set Abort State */ hdma->State = HAL_DMA_STATE_ABORT; 80016b0: 687b ldr r3, [r7, #4] 80016b2: 2205 movs r2, #5 80016b4: f883 2035 strb.w r2, [r3, #53] ; 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 80016b8: 687b ldr r3, [r7, #4] 80016ba: 681b ldr r3, [r3, #0] 80016bc: 681a ldr r2, [r3, #0] 80016be: 687b ldr r3, [r7, #4] 80016c0: 681b ldr r3, [r3, #0] 80016c2: f022 0201 bic.w r2, r2, #1 80016c6: 601a str r2, [r3, #0] } return HAL_OK; 80016c8: 2300 movs r3, #0 } 80016ca: 4618 mov r0, r3 80016cc: 370c adds r7, #12 80016ce: 46bd mov sp, r7 80016d0: f85d 7b04 ldr.w r7, [sp], #4 80016d4: 4770 bx lr ... 080016d8 : * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) { 80016d8: b580 push {r7, lr} 80016da: b084 sub sp, #16 80016dc: af00 add r7, sp, #0 80016de: 6078 str r0, [r7, #4] uint32_t tickstart; if (heth == NULL) 80016e0: 687b ldr r3, [r7, #4] 80016e2: 2b00 cmp r3, #0 80016e4: d101 bne.n 80016ea { return HAL_ERROR; 80016e6: 2301 movs r3, #1 80016e8: e08a b.n 8001800 } if (heth->gState == HAL_ETH_STATE_RESET) 80016ea: 687b ldr r3, [r7, #4] 80016ec: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 80016f0: 2b00 cmp r3, #0 80016f2: d106 bne.n 8001702 { heth->gState = HAL_ETH_STATE_BUSY; 80016f4: 687b ldr r3, [r7, #4] 80016f6: 2220 movs r2, #32 80016f8: f8c3 2084 str.w r2, [r3, #132] ; 0x84 /* Init the low level hardware */ heth->MspInitCallback(heth); #else /* Init the low level hardware : GPIO, CLOCK, NVIC. */ HAL_ETH_MspInit(heth); 80016fc: 6878 ldr r0, [r7, #4] 80016fe: f7ff fbaf bl 8000e60 #endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */ } __HAL_RCC_SYSCFG_CLK_ENABLE(); 8001702: 2300 movs r3, #0 8001704: 60bb str r3, [r7, #8] 8001706: 4b40 ldr r3, [pc, #256] ; (8001808 ) 8001708: 6c5b ldr r3, [r3, #68] ; 0x44 800170a: 4a3f ldr r2, [pc, #252] ; (8001808 ) 800170c: f443 4380 orr.w r3, r3, #16384 ; 0x4000 8001710: 6453 str r3, [r2, #68] ; 0x44 8001712: 4b3d ldr r3, [pc, #244] ; (8001808 ) 8001714: 6c5b ldr r3, [r3, #68] ; 0x44 8001716: f403 4380 and.w r3, r3, #16384 ; 0x4000 800171a: 60bb str r3, [r7, #8] 800171c: 68bb ldr r3, [r7, #8] /* Select MII or RMII Mode*/ SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL); 800171e: 4b3b ldr r3, [pc, #236] ; (800180c ) 8001720: 685b ldr r3, [r3, #4] 8001722: 4a3a ldr r2, [pc, #232] ; (800180c ) 8001724: f423 0300 bic.w r3, r3, #8388608 ; 0x800000 8001728: 6053 str r3, [r2, #4] SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface; 800172a: 4b38 ldr r3, [pc, #224] ; (800180c ) 800172c: 685a ldr r2, [r3, #4] 800172e: 687b ldr r3, [r7, #4] 8001730: 689b ldr r3, [r3, #8] 8001732: 4936 ldr r1, [pc, #216] ; (800180c ) 8001734: 4313 orrs r3, r2 8001736: 604b str r3, [r1, #4] /* Dummy read to sync SYSCFG with ETH */ (void)SYSCFG->PMC; 8001738: 4b34 ldr r3, [pc, #208] ; (800180c ) 800173a: 685b ldr r3, [r3, #4] /* Ethernet Software reset */ /* Set the SWR bit: resets all MAC subsystem internal registers and logic */ /* After reset all the registers holds their respective reset values */ SET_BIT(heth->Instance->DMABMR, ETH_DMABMR_SR); 800173c: 687b ldr r3, [r7, #4] 800173e: 681b ldr r3, [r3, #0] 8001740: f503 5380 add.w r3, r3, #4096 ; 0x1000 8001744: 681b ldr r3, [r3, #0] 8001746: 687a ldr r2, [r7, #4] 8001748: 6812 ldr r2, [r2, #0] 800174a: f043 0301 orr.w r3, r3, #1 800174e: f502 5280 add.w r2, r2, #4096 ; 0x1000 8001752: 6013 str r3, [r2, #0] /* Get tick */ tickstart = HAL_GetTick(); 8001754: f7ff fdec bl 8001330 8001758: 60f8 str r0, [r7, #12] /* Wait for software reset */ while (READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_SR) > 0U) 800175a: e011 b.n 8001780 { if (((HAL_GetTick() - tickstart) > ETH_SWRESET_TIMEOUT)) 800175c: f7ff fde8 bl 8001330 8001760: 4602 mov r2, r0 8001762: 68fb ldr r3, [r7, #12] 8001764: 1ad3 subs r3, r2, r3 8001766: f5b3 7ffa cmp.w r3, #500 ; 0x1f4 800176a: d909 bls.n 8001780 { /* Set Error Code */ heth->ErrorCode = HAL_ETH_ERROR_TIMEOUT; 800176c: 687b ldr r3, [r7, #4] 800176e: 2204 movs r2, #4 8001770: f8c3 2088 str.w r2, [r3, #136] ; 0x88 /* Set State as Error */ heth->gState = HAL_ETH_STATE_ERROR; 8001774: 687b ldr r3, [r7, #4] 8001776: 22e0 movs r2, #224 ; 0xe0 8001778: f8c3 2084 str.w r2, [r3, #132] ; 0x84 /* Return Error */ return HAL_ERROR; 800177c: 2301 movs r3, #1 800177e: e03f b.n 8001800 while (READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_SR) > 0U) 8001780: 687b ldr r3, [r7, #4] 8001782: 681b ldr r3, [r3, #0] 8001784: f503 5380 add.w r3, r3, #4096 ; 0x1000 8001788: 681b ldr r3, [r3, #0] 800178a: f003 0301 and.w r3, r3, #1 800178e: 2b00 cmp r3, #0 8001790: d1e4 bne.n 800175c } } /*------------------ MAC, MTL and DMA default Configuration ----------------*/ ETH_MACDMAConfig(heth); 8001792: 6878 ldr r0, [r7, #4] 8001794: f000 f97a bl 8001a8c /*------------------ DMA Tx Descriptors Configuration ----------------------*/ ETH_DMATxDescListInit(heth); 8001798: 6878 ldr r0, [r7, #4] 800179a: f000 fa25 bl 8001be8 /*------------------ DMA Rx Descriptors Configuration ----------------------*/ ETH_DMARxDescListInit(heth); 800179e: 6878 ldr r0, [r7, #4] 80017a0: f000 fa7b bl 8001c9a /*--------------------- ETHERNET MAC Address Configuration ------------------*/ ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr); 80017a4: 687b ldr r3, [r7, #4] 80017a6: 685b ldr r3, [r3, #4] 80017a8: 461a mov r2, r3 80017aa: 2100 movs r1, #0 80017ac: 6878 ldr r0, [r7, #4] 80017ae: f000 f9e3 bl 8001b78 /* Disable MMC Interrupts */ SET_BIT(heth->Instance->MACIMR, ETH_MACIMR_TSTIM | ETH_MACIMR_PMTIM); 80017b2: 687b ldr r3, [r7, #4] 80017b4: 681b ldr r3, [r3, #0] 80017b6: 6bda ldr r2, [r3, #60] ; 0x3c 80017b8: 687b ldr r3, [r7, #4] 80017ba: 681b ldr r3, [r3, #0] 80017bc: f442 7202 orr.w r2, r2, #520 ; 0x208 80017c0: 63da str r2, [r3, #60] ; 0x3c /* Disable Rx MMC Interrupts */ SET_BIT(heth->Instance->MMCRIMR, ETH_MMCRIMR_RGUFM | ETH_MMCRIMR_RFAEM | \ 80017c2: 687b ldr r3, [r7, #4] 80017c4: 681b ldr r3, [r3, #0] 80017c6: f8d3 310c ldr.w r3, [r3, #268] ; 0x10c 80017ca: 687a ldr r2, [r7, #4] 80017cc: 6812 ldr r2, [r2, #0] 80017ce: f443 3300 orr.w r3, r3, #131072 ; 0x20000 80017d2: f043 0360 orr.w r3, r3, #96 ; 0x60 80017d6: f8c2 310c str.w r3, [r2, #268] ; 0x10c ETH_MMCRIMR_RFCEM); /* Disable Tx MMC Interrupts */ SET_BIT(heth->Instance->MMCTIMR, ETH_MMCTIMR_TGFM | ETH_MMCTIMR_TGFMSCM | \ 80017da: 687b ldr r3, [r7, #4] 80017dc: 681b ldr r3, [r3, #0] 80017de: f8d3 2110 ldr.w r2, [r3, #272] ; 0x110 80017e2: 687b ldr r3, [r7, #4] 80017e4: 681b ldr r3, [r3, #0] 80017e6: f442 1203 orr.w r2, r2, #2146304 ; 0x20c000 80017ea: f8c3 2110 str.w r2, [r3, #272] ; 0x110 ETH_MMCTIMR_TGFSCM); heth->ErrorCode = HAL_ETH_ERROR_NONE; 80017ee: 687b ldr r3, [r7, #4] 80017f0: 2200 movs r2, #0 80017f2: f8c3 2088 str.w r2, [r3, #136] ; 0x88 heth->gState = HAL_ETH_STATE_READY; 80017f6: 687b ldr r3, [r7, #4] 80017f8: 2210 movs r2, #16 80017fa: f8c3 2084 str.w r2, [r3, #132] ; 0x84 return HAL_OK; 80017fe: 2300 movs r3, #0 } 8001800: 4618 mov r0, r3 8001802: 3710 adds r7, #16 8001804: 46bd mov sp, r7 8001806: bd80 pop {r7, pc} 8001808: 40023800 .word 0x40023800 800180c: 40013800 .word 0x40013800 08001810 : HAL_Delay(ETH_REG_WRITE_DELAY); (heth->Instance)->DMAOMR = tmpreg; } static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, const ETH_MACConfigTypeDef *macconf) { 8001810: b580 push {r7, lr} 8001812: b084 sub sp, #16 8001814: af00 add r7, sp, #0 8001816: 6078 str r0, [r7, #4] 8001818: 6039 str r1, [r7, #0] uint32_t tmpreg1; /*------------------------ ETHERNET MACCR Configuration --------------------*/ /* Get the ETHERNET MACCR value */ tmpreg1 = (heth->Instance)->MACCR; 800181a: 687b ldr r3, [r7, #4] 800181c: 681b ldr r3, [r3, #0] 800181e: 681b ldr r3, [r3, #0] 8001820: 60fb str r3, [r7, #12] /* Clear CSTF, WD, PCE, PS, TE and RE bits */ tmpreg1 &= ETH_MACCR_CLEAR_MASK; 8001822: 68fa ldr r2, [r7, #12] 8001824: 4b53 ldr r3, [pc, #332] ; (8001974 ) 8001826: 4013 ands r3, r2 8001828: 60fb str r3, [r7, #12] tmpreg1 |= (uint32_t)(((uint32_t)macconf->CRCStripTypePacket << 25U) | 800182a: 683b ldr r3, [r7, #0] 800182c: 7b9b ldrb r3, [r3, #14] 800182e: 065b lsls r3, r3, #25 ((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 23U) | 8001830: 683a ldr r2, [r7, #0] 8001832: 7c12 ldrb r2, [r2, #16] 8001834: 2a00 cmp r2, #0 8001836: d102 bne.n 800183e 8001838: f44f 0200 mov.w r2, #8388608 ; 0x800000 800183c: e000 b.n 8001840 800183e: 2200 movs r2, #0 tmpreg1 |= (uint32_t)(((uint32_t)macconf->CRCStripTypePacket << 25U) | 8001840: 4313 orrs r3, r2 ((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 22U) | 8001842: 683a ldr r2, [r7, #0] 8001844: 7c52 ldrb r2, [r2, #17] 8001846: 2a00 cmp r2, #0 8001848: d102 bne.n 8001850 800184a: f44f 0280 mov.w r2, #4194304 ; 0x400000 800184e: e000 b.n 8001852 8001850: 2200 movs r2, #0 ((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 23U) | 8001852: 431a orrs r2, r3 (uint32_t)macconf->InterPacketGapVal | 8001854: 683b ldr r3, [r7, #0] 8001856: 689b ldr r3, [r3, #8] ((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 22U) | 8001858: 431a orrs r2, r3 ((uint32_t)macconf->CarrierSenseDuringTransmit << 16U) | 800185a: 683b ldr r3, [r7, #0] 800185c: 7fdb ldrb r3, [r3, #31] 800185e: 041b lsls r3, r3, #16 (uint32_t)macconf->InterPacketGapVal | 8001860: 431a orrs r2, r3 macconf->Speed | 8001862: 683b ldr r3, [r7, #0] 8001864: 695b ldr r3, [r3, #20] ((uint32_t)macconf->CarrierSenseDuringTransmit << 16U) | 8001866: 4313 orrs r3, r2 ((uint32_t)((macconf->ReceiveOwn == DISABLE) ? 1U : 0U) << 13U) | 8001868: 683a ldr r2, [r7, #0] 800186a: 7f92 ldrb r2, [r2, #30] 800186c: 2a00 cmp r2, #0 800186e: d102 bne.n 8001876 8001870: f44f 5200 mov.w r2, #8192 ; 0x2000 8001874: e000 b.n 8001878 8001876: 2200 movs r2, #0 macconf->Speed | 8001878: 431a orrs r2, r3 ((uint32_t)macconf->LoopbackMode << 12U) | 800187a: 683b ldr r3, [r7, #0] 800187c: 7f1b ldrb r3, [r3, #28] 800187e: 031b lsls r3, r3, #12 ((uint32_t)((macconf->ReceiveOwn == DISABLE) ? 1U : 0U) << 13U) | 8001880: 431a orrs r2, r3 macconf->DuplexMode | 8001882: 683b ldr r3, [r7, #0] 8001884: 699b ldr r3, [r3, #24] ((uint32_t)macconf->LoopbackMode << 12U) | 8001886: 431a orrs r2, r3 ((uint32_t)macconf->ChecksumOffload << 10U) | 8001888: 683b ldr r3, [r7, #0] 800188a: 791b ldrb r3, [r3, #4] 800188c: 029b lsls r3, r3, #10 macconf->DuplexMode | 800188e: 4313 orrs r3, r2 ((uint32_t)((macconf->RetryTransmission == DISABLE) ? 1U : 0U) << 9U) | 8001890: 683a ldr r2, [r7, #0] 8001892: f892 2020 ldrb.w r2, [r2, #32] 8001896: 2a00 cmp r2, #0 8001898: d102 bne.n 80018a0 800189a: f44f 7200 mov.w r2, #512 ; 0x200 800189e: e000 b.n 80018a2 80018a0: 2200 movs r2, #0 ((uint32_t)macconf->ChecksumOffload << 10U) | 80018a2: 431a orrs r2, r3 ((uint32_t)macconf->AutomaticPadCRCStrip << 7U) | 80018a4: 683b ldr r3, [r7, #0] 80018a6: 7bdb ldrb r3, [r3, #15] 80018a8: 01db lsls r3, r3, #7 ((uint32_t)((macconf->RetryTransmission == DISABLE) ? 1U : 0U) << 9U) | 80018aa: 431a orrs r2, r3 macconf->BackOffLimit | 80018ac: 683b ldr r3, [r7, #0] 80018ae: 6a5b ldr r3, [r3, #36] ; 0x24 ((uint32_t)macconf->AutomaticPadCRCStrip << 7U) | 80018b0: 431a orrs r2, r3 ((uint32_t)macconf->DeferralCheck << 4U)); 80018b2: 683b ldr r3, [r7, #0] 80018b4: f893 3028 ldrb.w r3, [r3, #40] ; 0x28 80018b8: 011b lsls r3, r3, #4 tmpreg1 |= (uint32_t)(((uint32_t)macconf->CRCStripTypePacket << 25U) | 80018ba: 4313 orrs r3, r2 80018bc: 68fa ldr r2, [r7, #12] 80018be: 4313 orrs r3, r2 80018c0: 60fb str r3, [r7, #12] /* Write to ETHERNET MACCR */ (heth->Instance)->MACCR = (uint32_t)tmpreg1; 80018c2: 687b ldr r3, [r7, #4] 80018c4: 681b ldr r3, [r3, #0] 80018c6: 68fa ldr r2, [r7, #12] 80018c8: 601a str r2, [r3, #0] /* Wait until the write operation will be taken into account : at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->MACCR; 80018ca: 687b ldr r3, [r7, #4] 80018cc: 681b ldr r3, [r3, #0] 80018ce: 681b ldr r3, [r3, #0] 80018d0: 60fb str r3, [r7, #12] HAL_Delay(ETH_REG_WRITE_DELAY); 80018d2: 2001 movs r0, #1 80018d4: f7ff fd38 bl 8001348 (heth->Instance)->MACCR = tmpreg1; 80018d8: 687b ldr r3, [r7, #4] 80018da: 681b ldr r3, [r3, #0] 80018dc: 68fa ldr r2, [r7, #12] 80018de: 601a str r2, [r3, #0] /*----------------------- ETHERNET MACFCR Configuration --------------------*/ /* Get the ETHERNET MACFCR value */ tmpreg1 = (heth->Instance)->MACFCR; 80018e0: 687b ldr r3, [r7, #4] 80018e2: 681b ldr r3, [r3, #0] 80018e4: 699b ldr r3, [r3, #24] 80018e6: 60fb str r3, [r7, #12] /* Clear xx bits */ tmpreg1 &= ETH_MACFCR_CLEAR_MASK; 80018e8: 68fa ldr r2, [r7, #12] 80018ea: f64f 7341 movw r3, #65345 ; 0xff41 80018ee: 4013 ands r3, r2 80018f0: 60fb str r3, [r7, #12] tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) | 80018f2: 683b ldr r3, [r7, #0] 80018f4: 6c9b ldr r3, [r3, #72] ; 0x48 80018f6: 041b lsls r3, r3, #16 ((uint32_t)((macconf->ZeroQuantaPause == DISABLE) ? 1U : 0U) << 7U) | 80018f8: 683a ldr r2, [r7, #0] 80018fa: f892 204c ldrb.w r2, [r2, #76] ; 0x4c 80018fe: 2a00 cmp r2, #0 8001900: d101 bne.n 8001906 8001902: 2280 movs r2, #128 ; 0x80 8001904: e000 b.n 8001908 8001906: 2200 movs r2, #0 tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) | 8001908: 431a orrs r2, r3 macconf->PauseLowThreshold | 800190a: 683b ldr r3, [r7, #0] 800190c: 6d1b ldr r3, [r3, #80] ; 0x50 ((uint32_t)((macconf->ZeroQuantaPause == DISABLE) ? 1U : 0U) << 7U) | 800190e: 4313 orrs r3, r2 ((uint32_t)((macconf->UnicastPausePacketDetect == ENABLE) ? 1U : 0U) << 3U) | 8001910: 683a ldr r2, [r7, #0] 8001912: f892 2055 ldrb.w r2, [r2, #85] ; 0x55 8001916: 2a01 cmp r2, #1 8001918: d101 bne.n 800191e 800191a: 2208 movs r2, #8 800191c: e000 b.n 8001920 800191e: 2200 movs r2, #0 macconf->PauseLowThreshold | 8001920: 4313 orrs r3, r2 ((uint32_t)((macconf->ReceiveFlowControl == ENABLE) ? 1U : 0U) << 2U) | 8001922: 683a ldr r2, [r7, #0] 8001924: f892 2056 ldrb.w r2, [r2, #86] ; 0x56 8001928: 2a01 cmp r2, #1 800192a: d101 bne.n 8001930 800192c: 2204 movs r2, #4 800192e: e000 b.n 8001932 8001930: 2200 movs r2, #0 ((uint32_t)((macconf->UnicastPausePacketDetect == ENABLE) ? 1U : 0U) << 3U) | 8001932: 4313 orrs r3, r2 ((uint32_t)((macconf->TransmitFlowControl == ENABLE) ? 1U : 0U) << 1U)); 8001934: 683a ldr r2, [r7, #0] 8001936: f892 2054 ldrb.w r2, [r2, #84] ; 0x54 800193a: 2a01 cmp r2, #1 800193c: d101 bne.n 8001942 800193e: 2202 movs r2, #2 8001940: e000 b.n 8001944 8001942: 2200 movs r2, #0 tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) | 8001944: 4313 orrs r3, r2 8001946: 68fa ldr r2, [r7, #12] 8001948: 4313 orrs r3, r2 800194a: 60fb str r3, [r7, #12] /* Write to ETHERNET MACFCR */ (heth->Instance)->MACFCR = (uint32_t)tmpreg1; 800194c: 687b ldr r3, [r7, #4] 800194e: 681b ldr r3, [r3, #0] 8001950: 68fa ldr r2, [r7, #12] 8001952: 619a str r2, [r3, #24] /* Wait until the write operation will be taken into account : at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->MACFCR; 8001954: 687b ldr r3, [r7, #4] 8001956: 681b ldr r3, [r3, #0] 8001958: 699b ldr r3, [r3, #24] 800195a: 60fb str r3, [r7, #12] HAL_Delay(ETH_REG_WRITE_DELAY); 800195c: 2001 movs r0, #1 800195e: f7ff fcf3 bl 8001348 (heth->Instance)->MACFCR = tmpreg1; 8001962: 687b ldr r3, [r7, #4] 8001964: 681b ldr r3, [r3, #0] 8001966: 68fa ldr r2, [r7, #12] 8001968: 619a str r2, [r3, #24] } 800196a: bf00 nop 800196c: 3710 adds r7, #16 800196e: 46bd mov sp, r7 8001970: bd80 pop {r7, pc} 8001972: bf00 nop 8001974: fd20810f .word 0xfd20810f 08001978 : static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, const ETH_DMAConfigTypeDef *dmaconf) { 8001978: b580 push {r7, lr} 800197a: b084 sub sp, #16 800197c: af00 add r7, sp, #0 800197e: 6078 str r0, [r7, #4] 8001980: 6039 str r1, [r7, #0] uint32_t tmpreg1; /*----------------------- ETHERNET DMAOMR Configuration --------------------*/ /* Get the ETHERNET DMAOMR value */ tmpreg1 = (heth->Instance)->DMAOMR; 8001982: 687b ldr r3, [r7, #4] 8001984: 681b ldr r3, [r3, #0] 8001986: f503 5380 add.w r3, r3, #4096 ; 0x1000 800198a: 699b ldr r3, [r3, #24] 800198c: 60fb str r3, [r7, #12] /* Clear xx bits */ tmpreg1 &= ETH_DMAOMR_CLEAR_MASK; 800198e: 68fa ldr r2, [r7, #12] 8001990: 4b3d ldr r3, [pc, #244] ; (8001a88 ) 8001992: 4013 ands r3, r2 8001994: 60fb str r3, [r7, #12] tmpreg1 |= (uint32_t)(((uint32_t)((dmaconf->DropTCPIPChecksumErrorFrame == DISABLE) ? 1U : 0U) << 26U) | 8001996: 683b ldr r3, [r7, #0] 8001998: 7b1b ldrb r3, [r3, #12] 800199a: 2b00 cmp r3, #0 800199c: d102 bne.n 80019a4 800199e: f04f 6280 mov.w r2, #67108864 ; 0x4000000 80019a2: e000 b.n 80019a6 80019a4: 2200 movs r2, #0 ((uint32_t)dmaconf->ReceiveStoreForward << 25U) | 80019a6: 683b ldr r3, [r7, #0] 80019a8: 7b5b ldrb r3, [r3, #13] 80019aa: 065b lsls r3, r3, #25 tmpreg1 |= (uint32_t)(((uint32_t)((dmaconf->DropTCPIPChecksumErrorFrame == DISABLE) ? 1U : 0U) << 26U) | 80019ac: 4313 orrs r3, r2 ((uint32_t)((dmaconf->FlushRxPacket == DISABLE) ? 1U : 0U) << 20U) | 80019ae: 683a ldr r2, [r7, #0] 80019b0: 7f52 ldrb r2, [r2, #29] 80019b2: 2a00 cmp r2, #0 80019b4: d102 bne.n 80019bc 80019b6: f44f 1280 mov.w r2, #1048576 ; 0x100000 80019ba: e000 b.n 80019be 80019bc: 2200 movs r2, #0 ((uint32_t)dmaconf->ReceiveStoreForward << 25U) | 80019be: 431a orrs r2, r3 ((uint32_t)dmaconf->TransmitStoreForward << 21U) | 80019c0: 683b ldr r3, [r7, #0] 80019c2: 7b9b ldrb r3, [r3, #14] 80019c4: 055b lsls r3, r3, #21 ((uint32_t)((dmaconf->FlushRxPacket == DISABLE) ? 1U : 0U) << 20U) | 80019c6: 431a orrs r2, r3 dmaconf->TransmitThresholdControl | 80019c8: 683b ldr r3, [r7, #0] 80019ca: 695b ldr r3, [r3, #20] ((uint32_t)dmaconf->TransmitStoreForward << 21U) | 80019cc: 431a orrs r2, r3 ((uint32_t)dmaconf->ForwardErrorFrames << 7U) | 80019ce: 683b ldr r3, [r7, #0] 80019d0: 7f1b ldrb r3, [r3, #28] 80019d2: 01db lsls r3, r3, #7 dmaconf->TransmitThresholdControl | 80019d4: 431a orrs r2, r3 ((uint32_t)dmaconf->ForwardUndersizedGoodFrames << 6U) | 80019d6: 683b ldr r3, [r7, #0] 80019d8: 7f9b ldrb r3, [r3, #30] 80019da: 019b lsls r3, r3, #6 ((uint32_t)dmaconf->ForwardErrorFrames << 7U) | 80019dc: 431a orrs r2, r3 dmaconf->ReceiveThresholdControl | 80019de: 683b ldr r3, [r7, #0] 80019e0: 6a1b ldr r3, [r3, #32] ((uint32_t)dmaconf->ForwardUndersizedGoodFrames << 6U) | 80019e2: 431a orrs r2, r3 ((uint32_t)dmaconf->SecondFrameOperate << 2U)); 80019e4: 683b ldr r3, [r7, #0] 80019e6: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 80019ea: 009b lsls r3, r3, #2 tmpreg1 |= (uint32_t)(((uint32_t)((dmaconf->DropTCPIPChecksumErrorFrame == DISABLE) ? 1U : 0U) << 26U) | 80019ec: 4313 orrs r3, r2 80019ee: 68fa ldr r2, [r7, #12] 80019f0: 4313 orrs r3, r2 80019f2: 60fb str r3, [r7, #12] /* Write to ETHERNET DMAOMR */ (heth->Instance)->DMAOMR = (uint32_t)tmpreg1; 80019f4: 687b ldr r3, [r7, #4] 80019f6: 681b ldr r3, [r3, #0] 80019f8: f503 5380 add.w r3, r3, #4096 ; 0x1000 80019fc: 461a mov r2, r3 80019fe: 68fb ldr r3, [r7, #12] 8001a00: 6193 str r3, [r2, #24] /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->DMAOMR; 8001a02: 687b ldr r3, [r7, #4] 8001a04: 681b ldr r3, [r3, #0] 8001a06: f503 5380 add.w r3, r3, #4096 ; 0x1000 8001a0a: 699b ldr r3, [r3, #24] 8001a0c: 60fb str r3, [r7, #12] HAL_Delay(ETH_REG_WRITE_DELAY); 8001a0e: 2001 movs r0, #1 8001a10: f7ff fc9a bl 8001348 (heth->Instance)->DMAOMR = tmpreg1; 8001a14: 687b ldr r3, [r7, #4] 8001a16: 681b ldr r3, [r3, #0] 8001a18: f503 5380 add.w r3, r3, #4096 ; 0x1000 8001a1c: 461a mov r2, r3 8001a1e: 68fb ldr r3, [r7, #12] 8001a20: 6193 str r3, [r2, #24] /*----------------------- ETHERNET DMABMR Configuration --------------------*/ (heth->Instance)->DMABMR = (uint32_t)(((uint32_t)dmaconf->AddressAlignedBeats << 25U) | 8001a22: 683b ldr r3, [r7, #0] 8001a24: 791b ldrb r3, [r3, #4] 8001a26: 065a lsls r2, r3, #25 dmaconf->BurstMode | 8001a28: 683b ldr r3, [r7, #0] 8001a2a: 689b ldr r3, [r3, #8] (heth->Instance)->DMABMR = (uint32_t)(((uint32_t)dmaconf->AddressAlignedBeats << 25U) | 8001a2c: 431a orrs r2, r3 dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or 8001a2e: 683b ldr r3, [r7, #0] 8001a30: 699b ldr r3, [r3, #24] dmaconf->BurstMode | 8001a32: 431a orrs r2, r3 Rx it is applied for the other */ dmaconf->TxDMABurstLength | 8001a34: 683b ldr r3, [r7, #0] 8001a36: 691b ldr r3, [r3, #16] dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or 8001a38: 431a orrs r2, r3 ((uint32_t)dmaconf->EnhancedDescriptorFormat << 7U) | 8001a3a: 683b ldr r3, [r7, #0] 8001a3c: f893 3025 ldrb.w r3, [r3, #37] ; 0x25 8001a40: 01db lsls r3, r3, #7 dmaconf->TxDMABurstLength | 8001a42: 431a orrs r2, r3 (dmaconf->DescriptorSkipLength << 2U) | 8001a44: 683b ldr r3, [r7, #0] 8001a46: 6a9b ldr r3, [r3, #40] ; 0x28 8001a48: 009b lsls r3, r3, #2 ((uint32_t)dmaconf->EnhancedDescriptorFormat << 7U) | 8001a4a: 431a orrs r2, r3 dmaconf->DMAArbitration | 8001a4c: 683b ldr r3, [r7, #0] 8001a4e: 681b ldr r3, [r3, #0] (dmaconf->DescriptorSkipLength << 2U) | 8001a50: 4313 orrs r3, r2 (heth->Instance)->DMABMR = (uint32_t)(((uint32_t)dmaconf->AddressAlignedBeats << 25U) | 8001a52: 687a ldr r2, [r7, #4] 8001a54: 6812 ldr r2, [r2, #0] 8001a56: f443 0300 orr.w r3, r3, #8388608 ; 0x800000 8001a5a: f502 5280 add.w r2, r2, #4096 ; 0x1000 8001a5e: 6013 str r3, [r2, #0] ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->DMABMR; 8001a60: 687b ldr r3, [r7, #4] 8001a62: 681b ldr r3, [r3, #0] 8001a64: f503 5380 add.w r3, r3, #4096 ; 0x1000 8001a68: 681b ldr r3, [r3, #0] 8001a6a: 60fb str r3, [r7, #12] HAL_Delay(ETH_REG_WRITE_DELAY); 8001a6c: 2001 movs r0, #1 8001a6e: f7ff fc6b bl 8001348 (heth->Instance)->DMABMR = tmpreg1; 8001a72: 687b ldr r3, [r7, #4] 8001a74: 681b ldr r3, [r3, #0] 8001a76: f503 5380 add.w r3, r3, #4096 ; 0x1000 8001a7a: 461a mov r2, r3 8001a7c: 68fb ldr r3, [r7, #12] 8001a7e: 6013 str r3, [r2, #0] } 8001a80: bf00 nop 8001a82: 3710 adds r7, #16 8001a84: 46bd mov sp, r7 8001a86: bd80 pop {r7, pc} 8001a88: f8de3f23 .word 0xf8de3f23 08001a8c : * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth) { 8001a8c: b580 push {r7, lr} 8001a8e: b0a6 sub sp, #152 ; 0x98 8001a90: af00 add r7, sp, #0 8001a92: 6078 str r0, [r7, #4] ETH_MACConfigTypeDef macDefaultConf; ETH_DMAConfigTypeDef dmaDefaultConf; /*--------------- ETHERNET MAC registers default Configuration --------------*/ macDefaultConf.Watchdog = ENABLE; 8001a94: 2301 movs r3, #1 8001a96: f887 3044 strb.w r3, [r7, #68] ; 0x44 macDefaultConf.Jabber = ENABLE; 8001a9a: 2301 movs r3, #1 8001a9c: f887 3045 strb.w r3, [r7, #69] ; 0x45 macDefaultConf.InterPacketGapVal = ETH_INTERFRAMEGAP_96BIT; 8001aa0: 2300 movs r3, #0 8001aa2: 63fb str r3, [r7, #60] ; 0x3c macDefaultConf.CarrierSenseDuringTransmit = DISABLE; 8001aa4: 2300 movs r3, #0 8001aa6: f887 3053 strb.w r3, [r7, #83] ; 0x53 macDefaultConf.ReceiveOwn = ENABLE; 8001aaa: 2301 movs r3, #1 8001aac: f887 3052 strb.w r3, [r7, #82] ; 0x52 macDefaultConf.LoopbackMode = DISABLE; 8001ab0: 2300 movs r3, #0 8001ab2: f887 3050 strb.w r3, [r7, #80] ; 0x50 macDefaultConf.CRCStripTypePacket = ENABLE; 8001ab6: 2301 movs r3, #1 8001ab8: f887 3042 strb.w r3, [r7, #66] ; 0x42 macDefaultConf.ChecksumOffload = ENABLE; 8001abc: 2301 movs r3, #1 8001abe: f887 3038 strb.w r3, [r7, #56] ; 0x38 macDefaultConf.RetryTransmission = DISABLE; 8001ac2: 2300 movs r3, #0 8001ac4: f887 3054 strb.w r3, [r7, #84] ; 0x54 macDefaultConf.AutomaticPadCRCStrip = DISABLE; 8001ac8: 2300 movs r3, #0 8001aca: f887 3043 strb.w r3, [r7, #67] ; 0x43 macDefaultConf.BackOffLimit = ETH_BACKOFFLIMIT_10; 8001ace: 2300 movs r3, #0 8001ad0: 65bb str r3, [r7, #88] ; 0x58 macDefaultConf.DeferralCheck = DISABLE; 8001ad2: 2300 movs r3, #0 8001ad4: f887 305c strb.w r3, [r7, #92] ; 0x5c macDefaultConf.PauseTime = 0x0U; 8001ad8: 2300 movs r3, #0 8001ada: 67fb str r3, [r7, #124] ; 0x7c macDefaultConf.ZeroQuantaPause = DISABLE; 8001adc: 2300 movs r3, #0 8001ade: f887 3080 strb.w r3, [r7, #128] ; 0x80 macDefaultConf.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4; 8001ae2: 2300 movs r3, #0 8001ae4: f8c7 3084 str.w r3, [r7, #132] ; 0x84 macDefaultConf.ReceiveFlowControl = DISABLE; 8001ae8: 2300 movs r3, #0 8001aea: f887 308a strb.w r3, [r7, #138] ; 0x8a macDefaultConf.TransmitFlowControl = DISABLE; 8001aee: 2300 movs r3, #0 8001af0: f887 3088 strb.w r3, [r7, #136] ; 0x88 macDefaultConf.Speed = ETH_SPEED_100M; 8001af4: f44f 4380 mov.w r3, #16384 ; 0x4000 8001af8: 64bb str r3, [r7, #72] ; 0x48 macDefaultConf.DuplexMode = ETH_FULLDUPLEX_MODE; 8001afa: f44f 6300 mov.w r3, #2048 ; 0x800 8001afe: 64fb str r3, [r7, #76] ; 0x4c macDefaultConf.UnicastPausePacketDetect = DISABLE; 8001b00: 2300 movs r3, #0 8001b02: f887 3089 strb.w r3, [r7, #137] ; 0x89 /* MAC default configuration */ ETH_SetMACConfig(heth, &macDefaultConf); 8001b06: f107 0334 add.w r3, r7, #52 ; 0x34 8001b0a: 4619 mov r1, r3 8001b0c: 6878 ldr r0, [r7, #4] 8001b0e: f7ff fe7f bl 8001810 /*--------------- ETHERNET DMA registers default Configuration --------------*/ dmaDefaultConf.DropTCPIPChecksumErrorFrame = ENABLE; 8001b12: 2301 movs r3, #1 8001b14: 753b strb r3, [r7, #20] dmaDefaultConf.ReceiveStoreForward = ENABLE; 8001b16: 2301 movs r3, #1 8001b18: 757b strb r3, [r7, #21] dmaDefaultConf.FlushRxPacket = ENABLE; 8001b1a: 2301 movs r3, #1 8001b1c: f887 3025 strb.w r3, [r7, #37] ; 0x25 dmaDefaultConf.TransmitStoreForward = ENABLE; 8001b20: 2301 movs r3, #1 8001b22: 75bb strb r3, [r7, #22] dmaDefaultConf.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES; 8001b24: 2300 movs r3, #0 8001b26: 61fb str r3, [r7, #28] dmaDefaultConf.ForwardErrorFrames = DISABLE; 8001b28: 2300 movs r3, #0 8001b2a: f887 3024 strb.w r3, [r7, #36] ; 0x24 dmaDefaultConf.ForwardUndersizedGoodFrames = DISABLE; 8001b2e: 2300 movs r3, #0 8001b30: f887 3026 strb.w r3, [r7, #38] ; 0x26 dmaDefaultConf.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES; 8001b34: 2300 movs r3, #0 8001b36: 62bb str r3, [r7, #40] ; 0x28 dmaDefaultConf.SecondFrameOperate = ENABLE; 8001b38: 2301 movs r3, #1 8001b3a: f887 302c strb.w r3, [r7, #44] ; 0x2c dmaDefaultConf.AddressAlignedBeats = ENABLE; 8001b3e: 2301 movs r3, #1 8001b40: 733b strb r3, [r7, #12] dmaDefaultConf.BurstMode = ETH_BURSTLENGTH_FIXED; 8001b42: f44f 3380 mov.w r3, #65536 ; 0x10000 8001b46: 613b str r3, [r7, #16] dmaDefaultConf.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT; 8001b48: f44f 0380 mov.w r3, #4194304 ; 0x400000 8001b4c: 623b str r3, [r7, #32] dmaDefaultConf.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT; 8001b4e: f44f 5300 mov.w r3, #8192 ; 0x2000 8001b52: 61bb str r3, [r7, #24] dmaDefaultConf.EnhancedDescriptorFormat = ENABLE; 8001b54: 2301 movs r3, #1 8001b56: f887 302d strb.w r3, [r7, #45] ; 0x2d dmaDefaultConf.DescriptorSkipLength = 0x0U; 8001b5a: 2300 movs r3, #0 8001b5c: 633b str r3, [r7, #48] ; 0x30 dmaDefaultConf.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1; 8001b5e: 2300 movs r3, #0 8001b60: 60bb str r3, [r7, #8] /* DMA default configuration */ ETH_SetDMAConfig(heth, &dmaDefaultConf); 8001b62: f107 0308 add.w r3, r7, #8 8001b66: 4619 mov r1, r3 8001b68: 6878 ldr r0, [r7, #4] 8001b6a: f7ff ff05 bl 8001978 } 8001b6e: bf00 nop 8001b70: 3798 adds r7, #152 ; 0x98 8001b72: 46bd mov sp, r7 8001b74: bd80 pop {r7, pc} ... 08001b78 : * @arg ETH_MAC_Address3: MAC Address3 * @param Addr Pointer to MAC address buffer data (6 bytes) * @retval HAL status */ static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr) { 8001b78: b480 push {r7} 8001b7a: b087 sub sp, #28 8001b7c: af00 add r7, sp, #0 8001b7e: 60f8 str r0, [r7, #12] 8001b80: 60b9 str r1, [r7, #8] 8001b82: 607a str r2, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(heth); /* Calculate the selected MAC address high register */ tmpreg1 = ((uint32_t)Addr[5U] << 8U) | (uint32_t)Addr[4U]; 8001b84: 687b ldr r3, [r7, #4] 8001b86: 3305 adds r3, #5 8001b88: 781b ldrb r3, [r3, #0] 8001b8a: 021b lsls r3, r3, #8 8001b8c: 687a ldr r2, [r7, #4] 8001b8e: 3204 adds r2, #4 8001b90: 7812 ldrb r2, [r2, #0] 8001b92: 4313 orrs r3, r2 8001b94: 617b str r3, [r7, #20] /* Load the selected MAC address high register */ (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg1; 8001b96: 68ba ldr r2, [r7, #8] 8001b98: 4b11 ldr r3, [pc, #68] ; (8001be0 ) 8001b9a: 4413 add r3, r2 8001b9c: 461a mov r2, r3 8001b9e: 697b ldr r3, [r7, #20] 8001ba0: 6013 str r3, [r2, #0] /* Calculate the selected MAC address low register */ tmpreg1 = ((uint32_t)Addr[3U] << 24U) | ((uint32_t)Addr[2U] << 16U) | ((uint32_t)Addr[1U] << 8U) | Addr[0U]; 8001ba2: 687b ldr r3, [r7, #4] 8001ba4: 3303 adds r3, #3 8001ba6: 781b ldrb r3, [r3, #0] 8001ba8: 061a lsls r2, r3, #24 8001baa: 687b ldr r3, [r7, #4] 8001bac: 3302 adds r3, #2 8001bae: 781b ldrb r3, [r3, #0] 8001bb0: 041b lsls r3, r3, #16 8001bb2: 431a orrs r2, r3 8001bb4: 687b ldr r3, [r7, #4] 8001bb6: 3301 adds r3, #1 8001bb8: 781b ldrb r3, [r3, #0] 8001bba: 021b lsls r3, r3, #8 8001bbc: 4313 orrs r3, r2 8001bbe: 687a ldr r2, [r7, #4] 8001bc0: 7812 ldrb r2, [r2, #0] 8001bc2: 4313 orrs r3, r2 8001bc4: 617b str r3, [r7, #20] /* Load the selected MAC address low register */ (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg1; 8001bc6: 68ba ldr r2, [r7, #8] 8001bc8: 4b06 ldr r3, [pc, #24] ; (8001be4 ) 8001bca: 4413 add r3, r2 8001bcc: 461a mov r2, r3 8001bce: 697b ldr r3, [r7, #20] 8001bd0: 6013 str r3, [r2, #0] } 8001bd2: bf00 nop 8001bd4: 371c adds r7, #28 8001bd6: 46bd mov sp, r7 8001bd8: f85d 7b04 ldr.w r7, [sp], #4 8001bdc: 4770 bx lr 8001bde: bf00 nop 8001be0: 40028040 .word 0x40028040 8001be4: 40028044 .word 0x40028044 08001be8 : * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth) { 8001be8: b480 push {r7} 8001bea: b085 sub sp, #20 8001bec: af00 add r7, sp, #0 8001bee: 6078 str r0, [r7, #4] ETH_DMADescTypeDef *dmatxdesc; uint32_t i; /* Fill each DMATxDesc descriptor with the right values */ for (i = 0; i < (uint32_t)ETH_TX_DESC_CNT; i++) 8001bf0: 2300 movs r3, #0 8001bf2: 60fb str r3, [r7, #12] 8001bf4: e03e b.n 8001c74 { dmatxdesc = heth->Init.TxDesc + i; 8001bf6: 687b ldr r3, [r7, #4] 8001bf8: 68d9 ldr r1, [r3, #12] 8001bfa: 68fa ldr r2, [r7, #12] 8001bfc: 4613 mov r3, r2 8001bfe: 009b lsls r3, r3, #2 8001c00: 4413 add r3, r2 8001c02: 00db lsls r3, r3, #3 8001c04: 440b add r3, r1 8001c06: 60bb str r3, [r7, #8] WRITE_REG(dmatxdesc->DESC0, 0x0U); 8001c08: 68bb ldr r3, [r7, #8] 8001c0a: 2200 movs r2, #0 8001c0c: 601a str r2, [r3, #0] WRITE_REG(dmatxdesc->DESC1, 0x0U); 8001c0e: 68bb ldr r3, [r7, #8] 8001c10: 2200 movs r2, #0 8001c12: 605a str r2, [r3, #4] WRITE_REG(dmatxdesc->DESC2, 0x0U); 8001c14: 68bb ldr r3, [r7, #8] 8001c16: 2200 movs r2, #0 8001c18: 609a str r2, [r3, #8] WRITE_REG(dmatxdesc->DESC3, 0x0U); 8001c1a: 68bb ldr r3, [r7, #8] 8001c1c: 2200 movs r2, #0 8001c1e: 60da str r2, [r3, #12] WRITE_REG(heth->TxDescList.TxDesc[i], (uint32_t)dmatxdesc); 8001c20: 68b9 ldr r1, [r7, #8] 8001c22: 687b ldr r3, [r7, #4] 8001c24: 68fa ldr r2, [r7, #12] 8001c26: 3206 adds r2, #6 8001c28: f843 1022 str.w r1, [r3, r2, lsl #2] /* Set Second Address Chained bit */ SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_TCH); 8001c2c: 68bb ldr r3, [r7, #8] 8001c2e: 681b ldr r3, [r3, #0] 8001c30: f443 1280 orr.w r2, r3, #1048576 ; 0x100000 8001c34: 68bb ldr r3, [r7, #8] 8001c36: 601a str r2, [r3, #0] if (i < ((uint32_t)ETH_TX_DESC_CNT - 1U)) 8001c38: 68fb ldr r3, [r7, #12] 8001c3a: 2b02 cmp r3, #2 8001c3c: d80c bhi.n 8001c58 { WRITE_REG(dmatxdesc->DESC3, (uint32_t)(heth->Init.TxDesc + i + 1U)); 8001c3e: 687b ldr r3, [r7, #4] 8001c40: 68d9 ldr r1, [r3, #12] 8001c42: 68fb ldr r3, [r7, #12] 8001c44: 1c5a adds r2, r3, #1 8001c46: 4613 mov r3, r2 8001c48: 009b lsls r3, r3, #2 8001c4a: 4413 add r3, r2 8001c4c: 00db lsls r3, r3, #3 8001c4e: 440b add r3, r1 8001c50: 461a mov r2, r3 8001c52: 68bb ldr r3, [r7, #8] 8001c54: 60da str r2, [r3, #12] 8001c56: e004 b.n 8001c62 } else { WRITE_REG(dmatxdesc->DESC3, (uint32_t)(heth->Init.TxDesc)); 8001c58: 687b ldr r3, [r7, #4] 8001c5a: 68db ldr r3, [r3, #12] 8001c5c: 461a mov r2, r3 8001c5e: 68bb ldr r3, [r7, #8] 8001c60: 60da str r2, [r3, #12] } /* Set the DMA Tx descriptors checksum insertion */ SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL); 8001c62: 68bb ldr r3, [r7, #8] 8001c64: 681b ldr r3, [r3, #0] 8001c66: f443 0240 orr.w r2, r3, #12582912 ; 0xc00000 8001c6a: 68bb ldr r3, [r7, #8] 8001c6c: 601a str r2, [r3, #0] for (i = 0; i < (uint32_t)ETH_TX_DESC_CNT; i++) 8001c6e: 68fb ldr r3, [r7, #12] 8001c70: 3301 adds r3, #1 8001c72: 60fb str r3, [r7, #12] 8001c74: 68fb ldr r3, [r7, #12] 8001c76: 2b03 cmp r3, #3 8001c78: d9bd bls.n 8001bf6 } heth->TxDescList.CurTxDesc = 0; 8001c7a: 687b ldr r3, [r7, #4] 8001c7c: 2200 movs r2, #0 8001c7e: 629a str r2, [r3, #40] ; 0x28 /* Set Transmit Descriptor List Address */ WRITE_REG(heth->Instance->DMATDLAR, (uint32_t) heth->Init.TxDesc); 8001c80: 687b ldr r3, [r7, #4] 8001c82: 68da ldr r2, [r3, #12] 8001c84: 687b ldr r3, [r7, #4] 8001c86: 681b ldr r3, [r3, #0] 8001c88: f503 5380 add.w r3, r3, #4096 ; 0x1000 8001c8c: 611a str r2, [r3, #16] } 8001c8e: bf00 nop 8001c90: 3714 adds r7, #20 8001c92: 46bd mov sp, r7 8001c94: f85d 7b04 ldr.w r7, [sp], #4 8001c98: 4770 bx lr 08001c9a : * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth) { 8001c9a: b480 push {r7} 8001c9c: b085 sub sp, #20 8001c9e: af00 add r7, sp, #0 8001ca0: 6078 str r0, [r7, #4] ETH_DMADescTypeDef *dmarxdesc; uint32_t i; for (i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++) 8001ca2: 2300 movs r3, #0 8001ca4: 60fb str r3, [r7, #12] 8001ca6: e048 b.n 8001d3a { dmarxdesc = heth->Init.RxDesc + i; 8001ca8: 687b ldr r3, [r7, #4] 8001caa: 6919 ldr r1, [r3, #16] 8001cac: 68fa ldr r2, [r7, #12] 8001cae: 4613 mov r3, r2 8001cb0: 009b lsls r3, r3, #2 8001cb2: 4413 add r3, r2 8001cb4: 00db lsls r3, r3, #3 8001cb6: 440b add r3, r1 8001cb8: 60bb str r3, [r7, #8] WRITE_REG(dmarxdesc->DESC0, 0x0U); 8001cba: 68bb ldr r3, [r7, #8] 8001cbc: 2200 movs r2, #0 8001cbe: 601a str r2, [r3, #0] WRITE_REG(dmarxdesc->DESC1, 0x0U); 8001cc0: 68bb ldr r3, [r7, #8] 8001cc2: 2200 movs r2, #0 8001cc4: 605a str r2, [r3, #4] WRITE_REG(dmarxdesc->DESC2, 0x0U); 8001cc6: 68bb ldr r3, [r7, #8] 8001cc8: 2200 movs r2, #0 8001cca: 609a str r2, [r3, #8] WRITE_REG(dmarxdesc->DESC3, 0x0U); 8001ccc: 68bb ldr r3, [r7, #8] 8001cce: 2200 movs r2, #0 8001cd0: 60da str r2, [r3, #12] WRITE_REG(dmarxdesc->BackupAddr0, 0x0U); 8001cd2: 68bb ldr r3, [r7, #8] 8001cd4: 2200 movs r2, #0 8001cd6: 621a str r2, [r3, #32] WRITE_REG(dmarxdesc->BackupAddr1, 0x0U); 8001cd8: 68bb ldr r3, [r7, #8] 8001cda: 2200 movs r2, #0 8001cdc: 625a str r2, [r3, #36] ; 0x24 /* Set Own bit of the Rx descriptor Status */ dmarxdesc->DESC0 = ETH_DMARXDESC_OWN; 8001cde: 68bb ldr r3, [r7, #8] 8001ce0: f04f 4200 mov.w r2, #2147483648 ; 0x80000000 8001ce4: 601a str r2, [r3, #0] /* Set Buffer1 size and Second Address Chained bit */ dmarxdesc->DESC1 = heth->Init.RxBuffLen | ETH_DMARXDESC_RCH; 8001ce6: 687b ldr r3, [r7, #4] 8001ce8: 695b ldr r3, [r3, #20] 8001cea: f443 4280 orr.w r2, r3, #16384 ; 0x4000 8001cee: 68bb ldr r3, [r7, #8] 8001cf0: 605a str r2, [r3, #4] /* Enable Ethernet DMA Rx Descriptor interrupt */ dmarxdesc->DESC1 &= ~ETH_DMARXDESC_DIC; 8001cf2: 68bb ldr r3, [r7, #8] 8001cf4: 685b ldr r3, [r3, #4] 8001cf6: f023 4200 bic.w r2, r3, #2147483648 ; 0x80000000 8001cfa: 68bb ldr r3, [r7, #8] 8001cfc: 605a str r2, [r3, #4] /* Set Rx descritors addresses */ WRITE_REG(heth->RxDescList.RxDesc[i], (uint32_t)dmarxdesc); 8001cfe: 68b9 ldr r1, [r7, #8] 8001d00: 687b ldr r3, [r7, #4] 8001d02: 68fa ldr r2, [r7, #12] 8001d04: 3212 adds r2, #18 8001d06: f843 1022 str.w r1, [r3, r2, lsl #2] if (i < ((uint32_t)ETH_RX_DESC_CNT - 1U)) 8001d0a: 68fb ldr r3, [r7, #12] 8001d0c: 2b02 cmp r3, #2 8001d0e: d80c bhi.n 8001d2a { WRITE_REG(dmarxdesc->DESC3, (uint32_t)(heth->Init.RxDesc + i + 1U)); 8001d10: 687b ldr r3, [r7, #4] 8001d12: 6919 ldr r1, [r3, #16] 8001d14: 68fb ldr r3, [r7, #12] 8001d16: 1c5a adds r2, r3, #1 8001d18: 4613 mov r3, r2 8001d1a: 009b lsls r3, r3, #2 8001d1c: 4413 add r3, r2 8001d1e: 00db lsls r3, r3, #3 8001d20: 440b add r3, r1 8001d22: 461a mov r2, r3 8001d24: 68bb ldr r3, [r7, #8] 8001d26: 60da str r2, [r3, #12] 8001d28: e004 b.n 8001d34 } else { WRITE_REG(dmarxdesc->DESC3, (uint32_t)(heth->Init.RxDesc)); 8001d2a: 687b ldr r3, [r7, #4] 8001d2c: 691b ldr r3, [r3, #16] 8001d2e: 461a mov r2, r3 8001d30: 68bb ldr r3, [r7, #8] 8001d32: 60da str r2, [r3, #12] for (i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++) 8001d34: 68fb ldr r3, [r7, #12] 8001d36: 3301 adds r3, #1 8001d38: 60fb str r3, [r7, #12] 8001d3a: 68fb ldr r3, [r7, #12] 8001d3c: 2b03 cmp r3, #3 8001d3e: d9b3 bls.n 8001ca8 } } WRITE_REG(heth->RxDescList.RxDescIdx, 0U); 8001d40: 687b ldr r3, [r7, #4] 8001d42: 2200 movs r2, #0 8001d44: 65da str r2, [r3, #92] ; 0x5c WRITE_REG(heth->RxDescList.RxDescCnt, 0U); 8001d46: 687b ldr r3, [r7, #4] 8001d48: 2200 movs r2, #0 8001d4a: 661a str r2, [r3, #96] ; 0x60 WRITE_REG(heth->RxDescList.RxBuildDescIdx, 0U); 8001d4c: 687b ldr r3, [r7, #4] 8001d4e: 2200 movs r2, #0 8001d50: 669a str r2, [r3, #104] ; 0x68 WRITE_REG(heth->RxDescList.RxBuildDescCnt, 0U); 8001d52: 687b ldr r3, [r7, #4] 8001d54: 2200 movs r2, #0 8001d56: 66da str r2, [r3, #108] ; 0x6c WRITE_REG(heth->RxDescList.ItMode, 0U); 8001d58: 687b ldr r3, [r7, #4] 8001d5a: 2200 movs r2, #0 8001d5c: 659a str r2, [r3, #88] ; 0x58 /* Set Receive Descriptor List Address */ WRITE_REG(heth->Instance->DMARDLAR, (uint32_t) heth->Init.RxDesc); 8001d5e: 687b ldr r3, [r7, #4] 8001d60: 691a ldr r2, [r3, #16] 8001d62: 687b ldr r3, [r7, #4] 8001d64: 681b ldr r3, [r3, #0] 8001d66: f503 5380 add.w r3, r3, #4096 ; 0x1000 8001d6a: 60da str r2, [r3, #12] } 8001d6c: bf00 nop 8001d6e: 3714 adds r7, #20 8001d70: 46bd mov sp, r7 8001d72: f85d 7b04 ldr.w r7, [sp], #4 8001d76: 4770 bx lr 08001d78 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8001d78: b480 push {r7} 8001d7a: b089 sub sp, #36 ; 0x24 8001d7c: af00 add r7, sp, #0 8001d7e: 6078 str r0, [r7, #4] 8001d80: 6039 str r1, [r7, #0] uint32_t position; uint32_t ioposition = 0x00U; 8001d82: 2300 movs r3, #0 8001d84: 617b str r3, [r7, #20] uint32_t iocurrent = 0x00U; 8001d86: 2300 movs r3, #0 8001d88: 613b str r3, [r7, #16] uint32_t temp = 0x00U; 8001d8a: 2300 movs r3, #0 8001d8c: 61bb str r3, [r7, #24] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ for(position = 0U; position < GPIO_NUMBER; position++) 8001d8e: 2300 movs r3, #0 8001d90: 61fb str r3, [r7, #28] 8001d92: e177 b.n 8002084 { /* Get the IO position */ ioposition = 0x01U << position; 8001d94: 2201 movs r2, #1 8001d96: 69fb ldr r3, [r7, #28] 8001d98: fa02 f303 lsl.w r3, r2, r3 8001d9c: 617b str r3, [r7, #20] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 8001d9e: 683b ldr r3, [r7, #0] 8001da0: 681b ldr r3, [r3, #0] 8001da2: 697a ldr r2, [r7, #20] 8001da4: 4013 ands r3, r2 8001da6: 613b str r3, [r7, #16] if(iocurrent == ioposition) 8001da8: 693a ldr r2, [r7, #16] 8001daa: 697b ldr r3, [r7, #20] 8001dac: 429a cmp r2, r3 8001dae: f040 8166 bne.w 800207e { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ 8001db2: 683b ldr r3, [r7, #0] 8001db4: 685b ldr r3, [r3, #4] 8001db6: f003 0303 and.w r3, r3, #3 8001dba: 2b01 cmp r3, #1 8001dbc: d005 beq.n 8001dca (GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8001dbe: 683b ldr r3, [r7, #0] 8001dc0: 685b ldr r3, [r3, #4] 8001dc2: f003 0303 and.w r3, r3, #3 if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ 8001dc6: 2b02 cmp r3, #2 8001dc8: d130 bne.n 8001e2c { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 8001dca: 687b ldr r3, [r7, #4] 8001dcc: 689b ldr r3, [r3, #8] 8001dce: 61bb str r3, [r7, #24] temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); 8001dd0: 69fb ldr r3, [r7, #28] 8001dd2: 005b lsls r3, r3, #1 8001dd4: 2203 movs r2, #3 8001dd6: fa02 f303 lsl.w r3, r2, r3 8001dda: 43db mvns r3, r3 8001ddc: 69ba ldr r2, [r7, #24] 8001dde: 4013 ands r3, r2 8001de0: 61bb str r3, [r7, #24] temp |= (GPIO_Init->Speed << (position * 2U)); 8001de2: 683b ldr r3, [r7, #0] 8001de4: 68da ldr r2, [r3, #12] 8001de6: 69fb ldr r3, [r7, #28] 8001de8: 005b lsls r3, r3, #1 8001dea: fa02 f303 lsl.w r3, r2, r3 8001dee: 69ba ldr r2, [r7, #24] 8001df0: 4313 orrs r3, r2 8001df2: 61bb str r3, [r7, #24] GPIOx->OSPEEDR = temp; 8001df4: 687b ldr r3, [r7, #4] 8001df6: 69ba ldr r2, [r7, #24] 8001df8: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 8001dfa: 687b ldr r3, [r7, #4] 8001dfc: 685b ldr r3, [r3, #4] 8001dfe: 61bb str r3, [r7, #24] temp &= ~(GPIO_OTYPER_OT_0 << position) ; 8001e00: 2201 movs r2, #1 8001e02: 69fb ldr r3, [r7, #28] 8001e04: fa02 f303 lsl.w r3, r2, r3 8001e08: 43db mvns r3, r3 8001e0a: 69ba ldr r2, [r7, #24] 8001e0c: 4013 ands r3, r2 8001e0e: 61bb str r3, [r7, #24] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 8001e10: 683b ldr r3, [r7, #0] 8001e12: 685b ldr r3, [r3, #4] 8001e14: 091b lsrs r3, r3, #4 8001e16: f003 0201 and.w r2, r3, #1 8001e1a: 69fb ldr r3, [r7, #28] 8001e1c: fa02 f303 lsl.w r3, r2, r3 8001e20: 69ba ldr r2, [r7, #24] 8001e22: 4313 orrs r3, r2 8001e24: 61bb str r3, [r7, #24] GPIOx->OTYPER = temp; 8001e26: 687b ldr r3, [r7, #4] 8001e28: 69ba ldr r2, [r7, #24] 8001e2a: 605a str r2, [r3, #4] } if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 8001e2c: 683b ldr r3, [r7, #0] 8001e2e: 685b ldr r3, [r3, #4] 8001e30: f003 0303 and.w r3, r3, #3 8001e34: 2b03 cmp r3, #3 8001e36: d017 beq.n 8001e68 { /* Check the parameters */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 8001e38: 687b ldr r3, [r7, #4] 8001e3a: 68db ldr r3, [r3, #12] 8001e3c: 61bb str r3, [r7, #24] temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); 8001e3e: 69fb ldr r3, [r7, #28] 8001e40: 005b lsls r3, r3, #1 8001e42: 2203 movs r2, #3 8001e44: fa02 f303 lsl.w r3, r2, r3 8001e48: 43db mvns r3, r3 8001e4a: 69ba ldr r2, [r7, #24] 8001e4c: 4013 ands r3, r2 8001e4e: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Pull) << (position * 2U)); 8001e50: 683b ldr r3, [r7, #0] 8001e52: 689a ldr r2, [r3, #8] 8001e54: 69fb ldr r3, [r7, #28] 8001e56: 005b lsls r3, r3, #1 8001e58: fa02 f303 lsl.w r3, r2, r3 8001e5c: 69ba ldr r2, [r7, #24] 8001e5e: 4313 orrs r3, r2 8001e60: 61bb str r3, [r7, #24] GPIOx->PUPDR = temp; 8001e62: 687b ldr r3, [r7, #4] 8001e64: 69ba ldr r2, [r7, #24] 8001e66: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8001e68: 683b ldr r3, [r7, #0] 8001e6a: 685b ldr r3, [r3, #4] 8001e6c: f003 0303 and.w r3, r3, #3 8001e70: 2b02 cmp r3, #2 8001e72: d123 bne.n 8001ebc { /* Check the Alternate function parameter */ assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; 8001e74: 69fb ldr r3, [r7, #28] 8001e76: 08da lsrs r2, r3, #3 8001e78: 687b ldr r3, [r7, #4] 8001e7a: 3208 adds r2, #8 8001e7c: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8001e80: 61bb str r3, [r7, #24] temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; 8001e82: 69fb ldr r3, [r7, #28] 8001e84: f003 0307 and.w r3, r3, #7 8001e88: 009b lsls r3, r3, #2 8001e8a: 220f movs r2, #15 8001e8c: fa02 f303 lsl.w r3, r2, r3 8001e90: 43db mvns r3, r3 8001e92: 69ba ldr r2, [r7, #24] 8001e94: 4013 ands r3, r2 8001e96: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U)); 8001e98: 683b ldr r3, [r7, #0] 8001e9a: 691a ldr r2, [r3, #16] 8001e9c: 69fb ldr r3, [r7, #28] 8001e9e: f003 0307 and.w r3, r3, #7 8001ea2: 009b lsls r3, r3, #2 8001ea4: fa02 f303 lsl.w r3, r2, r3 8001ea8: 69ba ldr r2, [r7, #24] 8001eaa: 4313 orrs r3, r2 8001eac: 61bb str r3, [r7, #24] GPIOx->AFR[position >> 3U] = temp; 8001eae: 69fb ldr r3, [r7, #28] 8001eb0: 08da lsrs r2, r3, #3 8001eb2: 687b ldr r3, [r7, #4] 8001eb4: 3208 adds r2, #8 8001eb6: 69b9 ldr r1, [r7, #24] 8001eb8: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 8001ebc: 687b ldr r3, [r7, #4] 8001ebe: 681b ldr r3, [r3, #0] 8001ec0: 61bb str r3, [r7, #24] temp &= ~(GPIO_MODER_MODER0 << (position * 2U)); 8001ec2: 69fb ldr r3, [r7, #28] 8001ec4: 005b lsls r3, r3, #1 8001ec6: 2203 movs r2, #3 8001ec8: fa02 f303 lsl.w r3, r2, r3 8001ecc: 43db mvns r3, r3 8001ece: 69ba ldr r2, [r7, #24] 8001ed0: 4013 ands r3, r2 8001ed2: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 8001ed4: 683b ldr r3, [r7, #0] 8001ed6: 685b ldr r3, [r3, #4] 8001ed8: f003 0203 and.w r2, r3, #3 8001edc: 69fb ldr r3, [r7, #28] 8001ede: 005b lsls r3, r3, #1 8001ee0: fa02 f303 lsl.w r3, r2, r3 8001ee4: 69ba ldr r2, [r7, #24] 8001ee6: 4313 orrs r3, r2 8001ee8: 61bb str r3, [r7, #24] GPIOx->MODER = temp; 8001eea: 687b ldr r3, [r7, #4] 8001eec: 69ba ldr r2, [r7, #24] 8001eee: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) != 0x00U) 8001ef0: 683b ldr r3, [r7, #0] 8001ef2: 685b ldr r3, [r3, #4] 8001ef4: f403 3340 and.w r3, r3, #196608 ; 0x30000 8001ef8: 2b00 cmp r3, #0 8001efa: f000 80c0 beq.w 800207e { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8001efe: 2300 movs r3, #0 8001f00: 60fb str r3, [r7, #12] 8001f02: 4b66 ldr r3, [pc, #408] ; (800209c ) 8001f04: 6c5b ldr r3, [r3, #68] ; 0x44 8001f06: 4a65 ldr r2, [pc, #404] ; (800209c ) 8001f08: f443 4380 orr.w r3, r3, #16384 ; 0x4000 8001f0c: 6453 str r3, [r2, #68] ; 0x44 8001f0e: 4b63 ldr r3, [pc, #396] ; (800209c ) 8001f10: 6c5b ldr r3, [r3, #68] ; 0x44 8001f12: f403 4380 and.w r3, r3, #16384 ; 0x4000 8001f16: 60fb str r3, [r7, #12] 8001f18: 68fb ldr r3, [r7, #12] temp = SYSCFG->EXTICR[position >> 2U]; 8001f1a: 4a61 ldr r2, [pc, #388] ; (80020a0 ) 8001f1c: 69fb ldr r3, [r7, #28] 8001f1e: 089b lsrs r3, r3, #2 8001f20: 3302 adds r3, #2 8001f22: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8001f26: 61bb str r3, [r7, #24] temp &= ~(0x0FU << (4U * (position & 0x03U))); 8001f28: 69fb ldr r3, [r7, #28] 8001f2a: f003 0303 and.w r3, r3, #3 8001f2e: 009b lsls r3, r3, #2 8001f30: 220f movs r2, #15 8001f32: fa02 f303 lsl.w r3, r2, r3 8001f36: 43db mvns r3, r3 8001f38: 69ba ldr r2, [r7, #24] 8001f3a: 4013 ands r3, r2 8001f3c: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); 8001f3e: 687b ldr r3, [r7, #4] 8001f40: 4a58 ldr r2, [pc, #352] ; (80020a4 ) 8001f42: 4293 cmp r3, r2 8001f44: d037 beq.n 8001fb6 8001f46: 687b ldr r3, [r7, #4] 8001f48: 4a57 ldr r2, [pc, #348] ; (80020a8 ) 8001f4a: 4293 cmp r3, r2 8001f4c: d031 beq.n 8001fb2 8001f4e: 687b ldr r3, [r7, #4] 8001f50: 4a56 ldr r2, [pc, #344] ; (80020ac ) 8001f52: 4293 cmp r3, r2 8001f54: d02b beq.n 8001fae 8001f56: 687b ldr r3, [r7, #4] 8001f58: 4a55 ldr r2, [pc, #340] ; (80020b0 ) 8001f5a: 4293 cmp r3, r2 8001f5c: d025 beq.n 8001faa 8001f5e: 687b ldr r3, [r7, #4] 8001f60: 4a54 ldr r2, [pc, #336] ; (80020b4 ) 8001f62: 4293 cmp r3, r2 8001f64: d01f beq.n 8001fa6 8001f66: 687b ldr r3, [r7, #4] 8001f68: 4a53 ldr r2, [pc, #332] ; (80020b8 ) 8001f6a: 4293 cmp r3, r2 8001f6c: d019 beq.n 8001fa2 8001f6e: 687b ldr r3, [r7, #4] 8001f70: 4a52 ldr r2, [pc, #328] ; (80020bc ) 8001f72: 4293 cmp r3, r2 8001f74: d013 beq.n 8001f9e