: /** * @brief The application entry point. * @retval int */ int main(void) { 800096c: b5b0 push {r4, r5, r7, lr} 800096e: b094 sub sp, #80 ; 0x50 8000970: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8000972: f000 fcb7 bl 80012e4 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8000976: f000 f863 bl 8000a40 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 800097a: f000 f9af bl 8000cdc MX_ETH_Init(); 800097e: f000 f8c9 bl 8000b14 MX_USART3_UART_Init(); 8000982: f000 f929 bl 8000bd8 MX_USB_OTG_FS_PCD_Init(); 8000986: f000 f97b bl 8000c80 MX_RNG_Init(); 800098a: f000 f911 bl 8000bb0 MX_USART6_UART_Init(); 800098e: f000 f94d bl 8000c2c /* USER CODE BEGIN 2 */ init_entropy(); 8000992: f7ff fdb1 bl 80004f8 while (1) { /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ HAL_StatusTypeDef status = HAL_UART_Receive(&huart6, buf_recv, sizeof(struct cmd), 100); 8000996: f107 011c add.w r1, r7, #28 800099a: 2364 movs r3, #100 ; 0x64 800099c: 2208 movs r2, #8 800099e: 4826 ldr r0, [pc, #152] ; (8000a38 ) 80009a0: f002 f9f7 bl 8002d92 80009a4: 4603 mov r3, r0 80009a6: f887 304f strb.w r3, [r7, #79] ; 0x4f if (status == HAL_OK){ 80009aa: f897 304f ldrb.w r3, [r7, #79] ; 0x4f 80009ae: 2b00 cmp r3, #0 80009b0: d1f1 bne.n 8000996 struct cmd *s_cmd = (struct cmd *)buf_recv; 80009b2: f107 031c add.w r3, r7, #28 80009b6: 64bb str r3, [r7, #72] ; 0x48 if (s_cmd->cmd == CSPRNG_CMD_GET_RNG){ 80009b8: 6cbb ldr r3, [r7, #72] ; 0x48 80009ba: 685b ldr r3, [r3, #4] 80009bc: 2b10 cmp r3, #16 80009be: d1ea bne.n 8000996 struct prng s_prng = {0}; 80009c0: 463b mov r3, r7 80009c2: 2200 movs r2, #0 80009c4: 601a str r2, [r3, #0] 80009c6: 605a str r2, [r3, #4] 80009c8: 609a str r2, [r3, #8] 80009ca: 60da str r2, [r3, #12] 80009cc: 611a str r2, [r3, #16] 80009ce: 615a str r2, [r3, #20] memset(buffer, 0, sizeof(struct prng)); 80009d0: f107 0324 add.w r3, r7, #36 ; 0x24 80009d4: 2218 movs r2, #24 80009d6: 2100 movs r1, #0 80009d8: 4618 mov r0, r3 80009da: f003 f8a7 bl 8003b2c HAL_GPIO_WritePin(GPIOB, GPIO_PIN_0, GPIO_PIN_SET); 80009de: 2201 movs r2, #1 80009e0: 2101 movs r1, #1 80009e2: 4816 ldr r0, [pc, #88] ; (8000a3c ) 80009e4: f001 faf6 bl 8001fd4 unsigned long long random = bbs(&s_prng.p, &s_prng.q, &s_prng.seed); 80009e8: 463b mov r3, r7 80009ea: f103 0208 add.w r2, r3, #8 80009ee: 463b mov r3, r7 80009f0: 1d19 adds r1, r3, #4 80009f2: 463b mov r3, r7 80009f4: 4618 mov r0, r3 80009f6: f7ff fe91 bl 800071c 80009fa: e9c7 0110 strd r0, r1, [r7, #64] ; 0x40 s_prng.output = random; 80009fe: e9d7 2310 ldrd r2, r3, [r7, #64] ; 0x40 8000a02: e9c7 2304 strd r2, r3, [r7, #16] memcpy(buffer, &s_prng, sizeof(struct prng)); 8000a06: f107 0424 add.w r4, r7, #36 ; 0x24 8000a0a: 463d mov r5, r7 8000a0c: cd0f ldmia r5!, {r0, r1, r2, r3} 8000a0e: c40f stmia r4!, {r0, r1, r2, r3} 8000a10: e895 0003 ldmia.w r5, {r0, r1} 8000a14: e884 0003 stmia.w r4, {r0, r1} HAL_StatusTypeDef s = HAL_UART_Transmit(&huart6, buffer, sizeof(struct prng), 0xF); 8000a18: f107 0124 add.w r1, r7, #36 ; 0x24 8000a1c: 230f movs r3, #15 8000a1e: 2218 movs r2, #24 8000a20: 4805 ldr r0, [pc, #20] ; (8000a38 ) 8000a22: f002 f92b bl 8002c7c 8000a26: 4603 mov r3, r0 8000a28: f887 303f strb.w r3, [r7, #63] ; 0x3f // We have finished, we disable the pin HAL_GPIO_WritePin(GPIOB, GPIO_PIN_0, GPIO_PIN_RESET); 8000a2c: 2200 movs r2, #0 8000a2e: 2101 movs r1, #1 8000a30: 4802 ldr r0, [pc, #8] ; (8000a3c ) 8000a32: f001 facf bl 8001fd4 { 8000a36: e7ae b.n 8000996 8000a38: 20000b6c .word 0x20000b6c 8000a3c: 40020400 .word 0x40020400 08000a40 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8000a40: b580 push {r7, lr} 8000a42: b094 sub sp, #80 ; 0x50 8000a44: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8000a46: f107 0320 add.w r3, r7, #32 8000a4a: 2230 movs r2, #48 ; 0x30 8000a4c: 2100 movs r1, #0 8000a4e: 4618 mov r0, r3 8000a50: f003 f86c bl 8003b2c RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000a54: f107 030c add.w r3, r7, #12 8000a58: 2200 movs r2, #0 8000a5a: 601a str r2, [r3, #0] 8000a5c: 605a str r2, [r3, #4] 8000a5e: 609a str r2, [r3, #8] 8000a60: 60da str r2, [r3, #12] 8000a62: 611a str r2, [r3, #16] /** Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); 8000a64: 2300 movs r3, #0 8000a66: 60bb str r3, [r7, #8] 8000a68: 4b28 ldr r3, [pc, #160] ; (8000b0c ) 8000a6a: 6c1b ldr r3, [r3, #64] ; 0x40 8000a6c: 4a27 ldr r2, [pc, #156] ; (8000b0c ) 8000a6e: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8000a72: 6413 str r3, [r2, #64] ; 0x40 8000a74: 4b25 ldr r3, [pc, #148] ; (8000b0c ) 8000a76: 6c1b ldr r3, [r3, #64] ; 0x40 8000a78: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8000a7c: 60bb str r3, [r7, #8] 8000a7e: 68bb ldr r3, [r7, #8] __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 8000a80: 2300 movs r3, #0 8000a82: 607b str r3, [r7, #4] 8000a84: 4b22 ldr r3, [pc, #136] ; (8000b10 ) 8000a86: 681b ldr r3, [r3, #0] 8000a88: 4a21 ldr r2, [pc, #132] ; (8000b10 ) 8000a8a: f443 4340 orr.w r3, r3, #49152 ; 0xc000 8000a8e: 6013 str r3, [r2, #0] 8000a90: 4b1f ldr r3, [pc, #124] ; (8000b10 ) 8000a92: 681b ldr r3, [r3, #0] 8000a94: f403 4340 and.w r3, r3, #49152 ; 0xc000 8000a98: 607b str r3, [r7, #4] 8000a9a: 687b ldr r3, [r7, #4] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 8000a9c: 2301 movs r3, #1 8000a9e: 623b str r3, [r7, #32] RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; 8000aa0: f44f 23a0 mov.w r3, #327680 ; 0x50000 8000aa4: 627b str r3, [r7, #36] ; 0x24 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8000aa6: 2302 movs r3, #2 8000aa8: 63bb str r3, [r7, #56] ; 0x38 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 8000aaa: f44f 0380 mov.w r3, #4194304 ; 0x400000 8000aae: 63fb str r3, [r7, #60] ; 0x3c RCC_OscInitStruct.PLL.PLLM = 4; 8000ab0: 2304 movs r3, #4 8000ab2: 643b str r3, [r7, #64] ; 0x40 RCC_OscInitStruct.PLL.PLLN = 168; 8000ab4: 23a8 movs r3, #168 ; 0xa8 8000ab6: 647b str r3, [r7, #68] ; 0x44 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 8000ab8: 2302 movs r3, #2 8000aba: 64bb str r3, [r7, #72] ; 0x48 RCC_OscInitStruct.PLL.PLLQ = 7; 8000abc: 2307 movs r3, #7 8000abe: 64fb str r3, [r7, #76] ; 0x4c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8000ac0: f107 0320 add.w r3, r7, #32 8000ac4: 4618 mov r0, r3 8000ac6: f001 fbc7 bl 8002258 8000aca: 4603 mov r3, r0 8000acc: 2b00 cmp r3, #0 8000ace: d001 beq.n 8000ad4 { Error_Handler(); 8000ad0: f000 f9b2 bl 8000e38 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8000ad4: 230f movs r3, #15 8000ad6: 60fb str r3, [r7, #12] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 8000ad8: 2302 movs r3, #2 8000ada: 613b str r3, [r7, #16] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 8000adc: 2300 movs r3, #0 8000ade: 617b str r3, [r7, #20] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; 8000ae0: f44f 53a0 mov.w r3, #5120 ; 0x1400 8000ae4: 61bb str r3, [r7, #24] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; 8000ae6: f44f 5380 mov.w r3, #4096 ; 0x1000 8000aea: 61fb str r3, [r7, #28] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) 8000aec: f107 030c add.w r3, r7, #12 8000af0: 2105 movs r1, #5 8000af2: 4618 mov r0, r3 8000af4: f001 fe28 bl 8002748 8000af8: 4603 mov r3, r0 8000afa: 2b00 cmp r3, #0 8000afc: d001 beq.n 8000b02 { Error_Handler(); 8000afe: f000 f99b bl 8000e38 } } 8000b02: bf00 nop 8000b04: 3750 adds r7, #80 ; 0x50 8000b06: 46bd mov sp, r7 8000b08: bd80 pop {r7, pc} 8000b0a: bf00 nop 8000b0c: 40023800 .word 0x40023800 8000b10: 40007000 .word 0x40007000 08000b14 : * @brief ETH Initialization Function * @param None * @retval None */ static void MX_ETH_Init(void) { 8000b14: b580 push {r7, lr} 8000b16: af00 add r7, sp, #0 static uint8_t MACAddr[6]; /* USER CODE BEGIN ETH_Init 1 */ /* USER CODE END ETH_Init 1 */ heth.Instance = ETH; 8000b18: 4b1f ldr r3, [pc, #124] ; (8000b98 ) 8000b1a: 4a20 ldr r2, [pc, #128] ; (8000b9c ) 8000b1c: 601a str r2, [r3, #0] MACAddr[0] = 0x00; 8000b1e: 4b20 ldr r3, [pc, #128] ; (8000ba0 ) 8000b20: 2200 movs r2, #0 8000b22: 701a strb r2, [r3, #0] MACAddr[1] = 0x80; 8000b24: 4b1e ldr r3, [pc, #120] ; (8000ba0 ) 8000b26: 2280 movs r2, #128 ; 0x80 8000b28: 705a strb r2, [r3, #1] MACAddr[2] = 0xE1; 8000b2a: 4b1d ldr r3, [pc, #116] ; (8000ba0 ) 8000b2c: 22e1 movs r2, #225 ; 0xe1 8000b2e: 709a strb r2, [r3, #2] MACAddr[3] = 0x00; 8000b30: 4b1b ldr r3, [pc, #108] ; (8000ba0 ) 8000b32: 2200 movs r2, #0 8000b34: 70da strb r2, [r3, #3] MACAddr[4] = 0x00; 8000b36: 4b1a ldr r3, [pc, #104] ; (8000ba0 ) 8000b38: 2200 movs r2, #0 8000b3a: 711a strb r2, [r3, #4] MACAddr[5] = 0x00; 8000b3c: 4b18 ldr r3, [pc, #96] ; (8000ba0 ) 8000b3e: 2200 movs r2, #0 8000b40: 715a strb r2, [r3, #5] heth.Init.MACAddr = &MACAddr[0]; 8000b42: 4b15 ldr r3, [pc, #84] ; (8000b98 ) 8000b44: 4a16 ldr r2, [pc, #88] ; (8000ba0 ) 8000b46: 605a str r2, [r3, #4] heth.Init.MediaInterface = HAL_ETH_RMII_MODE; 8000b48: 4b13 ldr r3, [pc, #76] ; (8000b98 ) 8000b4a: f44f 0200 mov.w r2, #8388608 ; 0x800000 8000b4e: 609a str r2, [r3, #8] heth.Init.TxDesc = DMATxDscrTab; 8000b50: 4b11 ldr r3, [pc, #68] ; (8000b98 ) 8000b52: 4a14 ldr r2, [pc, #80] ; (8000ba4 ) 8000b54: 60da str r2, [r3, #12] heth.Init.RxDesc = DMARxDscrTab; 8000b56: 4b10 ldr r3, [pc, #64] ; (8000b98 ) 8000b58: 4a13 ldr r2, [pc, #76] ; (8000ba8 ) 8000b5a: 611a str r2, [r3, #16] heth.Init.RxBuffLen = 1524; 8000b5c: 4b0e ldr r3, [pc, #56] ; (8000b98 ) 8000b5e: f240 52f4 movw r2, #1524 ; 0x5f4 8000b62: 615a str r2, [r3, #20] /* USER CODE BEGIN MACADDRESS */ /* USER CODE END MACADDRESS */ if (HAL_ETH_Init(&heth) != HAL_OK) 8000b64: 480c ldr r0, [pc, #48] ; (8000b98 ) 8000b66: f000 fd39 bl 80015dc 8000b6a: 4603 mov r3, r0 8000b6c: 2b00 cmp r3, #0 8000b6e: d001 beq.n 8000b74 { Error_Handler(); 8000b70: f000 f962 bl 8000e38 } memset(&TxConfig, 0 , sizeof(ETH_TxPacketConfig)); 8000b74: 2238 movs r2, #56 ; 0x38 8000b76: 2100 movs r1, #0 8000b78: 480c ldr r0, [pc, #48] ; (8000bac ) 8000b7a: f002 ffd7 bl 8003b2c TxConfig.Attributes = ETH_TX_PACKETS_FEATURES_CSUM | ETH_TX_PACKETS_FEATURES_CRCPAD; 8000b7e: 4b0b ldr r3, [pc, #44] ; (8000bac ) 8000b80: 2221 movs r2, #33 ; 0x21 8000b82: 601a str r2, [r3, #0] TxConfig.ChecksumCtrl = ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC; 8000b84: 4b09 ldr r3, [pc, #36] ; (8000bac ) 8000b86: f44f 0240 mov.w r2, #12582912 ; 0xc00000 8000b8a: 615a str r2, [r3, #20] TxConfig.CRCPadCtrl = ETH_CRC_PAD_INSERT; 8000b8c: 4b07 ldr r3, [pc, #28] ; (8000bac ) 8000b8e: 2200 movs r2, #0 8000b90: 611a str r2, [r3, #16] /* USER CODE BEGIN ETH_Init 2 */ /* USER CODE END ETH_Init 2 */ } 8000b92: bf00 nop 8000b94: bd80 pop {r7, pc} 8000b96: bf00 nop 8000b98: 20000a64 .word 0x20000a64 8000b9c: 40028000 .word 0x40028000 8000ba0: 20001098 .word 0x20001098 8000ba4: 200009c4 .word 0x200009c4 8000ba8: 20000924 .word 0x20000924 8000bac: 200008ec .word 0x200008ec 08000bb0 : * @brief RNG Initialization Function * @param None * @retval None */ static void MX_RNG_Init(void) { 8000bb0: b580 push {r7, lr} 8000bb2: af00 add r7, sp, #0 /* USER CODE END RNG_Init 0 */ /* USER CODE BEGIN RNG_Init 1 */ /* USER CODE END RNG_Init 1 */ hrng.Instance = RNG; 8000bb4: 4b06 ldr r3, [pc, #24] ; (8000bd0 ) 8000bb6: 4a07 ldr r2, [pc, #28] ; (8000bd4 ) 8000bb8: 601a str r2, [r3, #0] if (HAL_RNG_Init(&hrng) != HAL_OK) 8000bba: 4805 ldr r0, [pc, #20] ; (8000bd0 ) 8000bbc: f001 ffe4 bl 8002b88 8000bc0: 4603 mov r3, r0 8000bc2: 2b00 cmp r3, #0 8000bc4: d001 beq.n 8000bca { Error_Handler(); 8000bc6: f000 f937 bl 8000e38 } /* USER CODE BEGIN RNG_Init 2 */ /* USER CODE END RNG_Init 2 */ } 8000bca: bf00 nop 8000bcc: bd80 pop {r7, pc} 8000bce: bf00 nop 8000bd0: 20000b14 .word 0x20000b14 8000bd4: 50060800 .word 0x50060800 08000bd8 : * @brief USART3 Initialization Function * @param None * @retval None */ static void MX_USART3_UART_Init(void) { 8000bd8: b580 push {r7, lr} 8000bda: af00 add r7, sp, #0 /* USER CODE END USART3_Init 0 */ /* USER CODE BEGIN USART3_Init 1 */ /* USER CODE END USART3_Init 1 */ huart3.Instance = USART3; 8000bdc: 4b11 ldr r3, [pc, #68] ; (8000c24 ) 8000bde: 4a12 ldr r2, [pc, #72] ; (8000c28 ) 8000be0: 601a str r2, [r3, #0] huart3.Init.BaudRate = 115200; 8000be2: 4b10 ldr r3, [pc, #64] ; (8000c24 ) 8000be4: f44f 32e1 mov.w r2, #115200 ; 0x1c200 8000be8: 605a str r2, [r3, #4] huart3.Init.WordLength = UART_WORDLENGTH_8B; 8000bea: 4b0e ldr r3, [pc, #56] ; (8000c24 ) 8000bec: 2200 movs r2, #0 8000bee: 609a str r2, [r3, #8] huart3.Init.StopBits = UART_STOPBITS_1; 8000bf0: 4b0c ldr r3, [pc, #48] ; (8000c24 ) 8000bf2: 2200 movs r2, #0 8000bf4: 60da str r2, [r3, #12] huart3.Init.Parity = UART_PARITY_NONE; 8000bf6: 4b0b ldr r3, [pc, #44] ; (8000c24 ) 8000bf8: 2200 movs r2, #0 8000bfa: 611a str r2, [r3, #16] huart3.Init.Mode = UART_MODE_TX_RX; 8000bfc: 4b09 ldr r3, [pc, #36] ; (8000c24 ) 8000bfe: 220c movs r2, #12 8000c00: 615a str r2, [r3, #20] huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8000c02: 4b08 ldr r3, [pc, #32] ; (8000c24 ) 8000c04: 2200 movs r2, #0 8000c06: 619a str r2, [r3, #24] huart3.Init.OverSampling = UART_OVERSAMPLING_16; 8000c08: 4b06 ldr r3, [pc, #24] ; (8000c24 ) 8000c0a: 2200 movs r2, #0 8000c0c: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart3) != HAL_OK) 8000c0e: 4805 ldr r0, [pc, #20] ; (8000c24 ) 8000c10: f001 ffe4 bl 8002bdc 8000c14: 4603 mov r3, r0 8000c16: 2b00 cmp r3, #0 8000c18: d001 beq.n 8000c1e { Error_Handler(); 8000c1a: f000 f90d bl 8000e38 } /* USER CODE BEGIN USART3_Init 2 */ /* USER CODE END USART3_Init 2 */ } 8000c1e: bf00 nop 8000c20: bd80 pop {r7, pc} 8000c22: bf00 nop 8000c24: 20000b24 .word 0x20000b24 8000c28: 40004800 .word 0x40004800 08000c2c : * @brief USART6 Initialization Function * @param None * @retval None */ static void MX_USART6_UART_Init(void) { 8000c2c: b580 push {r7, lr} 8000c2e: af00 add r7, sp, #0 /* USER CODE END USART6_Init 0 */ /* USER CODE BEGIN USART6_Init 1 */ /* USER CODE END USART6_Init 1 */ huart6.Instance = USART6; 8000c30: 4b11 ldr r3, [pc, #68] ; (8000c78 ) 8000c32: 4a12 ldr r2, [pc, #72] ; (8000c7c ) 8000c34: 601a str r2, [r3, #0] huart6.Init.BaudRate = 115200; 8000c36: 4b10 ldr r3, [pc, #64] ; (8000c78 ) 8000c38: f44f 32e1 mov.w r2, #115200 ; 0x1c200 8000c3c: 605a str r2, [r3, #4] huart6.Init.WordLength = UART_WORDLENGTH_8B; 8000c3e: 4b0e ldr r3, [pc, #56] ; (8000c78 ) 8000c40: 2200 movs r2, #0 8000c42: 609a str r2, [r3, #8] huart6.Init.StopBits = UART_STOPBITS_1; 8000c44: 4b0c ldr r3, [pc, #48] ; (8000c78 ) 8000c46: 2200 movs r2, #0 8000c48: 60da str r2, [r3, #12] huart6.Init.Parity = UART_PARITY_NONE; 8000c4a: 4b0b ldr r3, [pc, #44] ; (8000c78 ) 8000c4c: 2200 movs r2, #0 8000c4e: 611a str r2, [r3, #16] huart6.Init.Mode = UART_MODE_TX_RX; 8000c50: 4b09 ldr r3, [pc, #36] ; (8000c78 ) 8000c52: 220c movs r2, #12 8000c54: 615a str r2, [r3, #20] huart6.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8000c56: 4b08 ldr r3, [pc, #32] ; (8000c78 ) 8000c58: 2200 movs r2, #0 8000c5a: 619a str r2, [r3, #24] huart6.Init.OverSampling = UART_OVERSAMPLING_16; 8000c5c: 4b06 ldr r3, [pc, #24] ; (8000c78 ) 8000c5e: 2200 movs r2, #0 8000c60: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart6) != HAL_OK) 8000c62: 4805 ldr r0, [pc, #20] ; (8000c78 ) 8000c64: f001 ffba bl 8002bdc 8000c68: 4603 mov r3, r0 8000c6a: 2b00 cmp r3, #0 8000c6c: d001 beq.n 8000c72 { Error_Handler(); 8000c6e: f000 f8e3 bl 8000e38 } /* USER CODE BEGIN USART6_Init 2 */ /* USER CODE END USART6_Init 2 */ } 8000c72: bf00 nop 8000c74: bd80 pop {r7, pc} 8000c76: bf00 nop 8000c78: 20000b6c .word 0x20000b6c 8000c7c: 40011400 .word 0x40011400 08000c80 : * @brief USB_OTG_FS Initialization Function * @param None * @retval None */ static void MX_USB_OTG_FS_PCD_Init(void) { 8000c80: b580 push {r7, lr} 8000c82: af00 add r7, sp, #0 /* USER CODE END USB_OTG_FS_Init 0 */ /* USER CODE BEGIN USB_OTG_FS_Init 1 */ /* USER CODE END USB_OTG_FS_Init 1 */ hpcd_USB_OTG_FS.Instance = USB_OTG_FS; 8000c84: 4b14 ldr r3, [pc, #80] ; (8000cd8 ) 8000c86: f04f 42a0 mov.w r2, #1342177280 ; 0x50000000 8000c8a: 601a str r2, [r3, #0] hpcd_USB_OTG_FS.Init.dev_endpoints = 4; 8000c8c: 4b12 ldr r3, [pc, #72] ; (8000cd8 ) 8000c8e: 2204 movs r2, #4 8000c90: 711a strb r2, [r3, #4] hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL; 8000c92: 4b11 ldr r3, [pc, #68] ; (8000cd8 ) 8000c94: 2202 movs r2, #2 8000c96: 71da strb r2, [r3, #7] hpcd_USB_OTG_FS.Init.dma_enable = DISABLE; 8000c98: 4b0f ldr r3, [pc, #60] ; (8000cd8 ) 8000c9a: 2200 movs r2, #0 8000c9c: 719a strb r2, [r3, #6] hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED; 8000c9e: 4b0e ldr r3, [pc, #56] ; (8000cd8 ) 8000ca0: 2202 movs r2, #2 8000ca2: 725a strb r2, [r3, #9] hpcd_USB_OTG_FS.Init.Sof_enable = ENABLE; 8000ca4: 4b0c ldr r3, [pc, #48] ; (8000cd8 ) 8000ca6: 2201 movs r2, #1 8000ca8: 729a strb r2, [r3, #10] hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE; 8000caa: 4b0b ldr r3, [pc, #44] ; (8000cd8 ) 8000cac: 2200 movs r2, #0 8000cae: 72da strb r2, [r3, #11] hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE; 8000cb0: 4b09 ldr r3, [pc, #36] ; (8000cd8 ) 8000cb2: 2200 movs r2, #0 8000cb4: 731a strb r2, [r3, #12] hpcd_USB_OTG_FS.Init.vbus_sensing_enable = ENABLE; 8000cb6: 4b08 ldr r3, [pc, #32] ; (8000cd8 ) 8000cb8: 2201 movs r2, #1 8000cba: 739a strb r2, [r3, #14] hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE; 8000cbc: 4b06 ldr r3, [pc, #24] ; (8000cd8 ) 8000cbe: 2200 movs r2, #0 8000cc0: 73da strb r2, [r3, #15] if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK) 8000cc2: 4805 ldr r0, [pc, #20] ; (8000cd8 ) 8000cc4: f001 f9b9 bl 800203a 8000cc8: 4603 mov r3, r0 8000cca: 2b00 cmp r3, #0 8000ccc: d001 beq.n 8000cd2 { Error_Handler(); 8000cce: f000 f8b3 bl 8000e38 } /* USER CODE BEGIN USB_OTG_FS_Init 2 */ /* USER CODE END USB_OTG_FS_Init 2 */ } 8000cd2: bf00 nop 8000cd4: bd80 pop {r7, pc} 8000cd6: bf00 nop 8000cd8: 20000bb4 .word 0x20000bb4 08000cdc : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 8000cdc: b580 push {r7, lr} 8000cde: b08c sub sp, #48 ; 0x30 8000ce0: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000ce2: f107 031c add.w r3, r7, #28 8000ce6: 2200 movs r2, #0 8000ce8: 601a str r2, [r3, #0] 8000cea: 605a str r2, [r3, #4] 8000cec: 609a str r2, [r3, #8] 8000cee: 60da str r2, [r3, #12] 8000cf0: 611a str r2, [r3, #16] /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); 8000cf2: 2300 movs r3, #0 8000cf4: 61bb str r3, [r7, #24] 8000cf6: 4b4c ldr r3, [pc, #304] ; (8000e28 ) 8000cf8: 6b1b ldr r3, [r3, #48] ; 0x30 8000cfa: 4a4b ldr r2, [pc, #300] ; (8000e28 ) 8000cfc: f043 0304 orr.w r3, r3, #4 8000d00: 6313 str r3, [r2, #48] ; 0x30 8000d02: 4b49 ldr r3, [pc, #292] ; (8000e28 ) 8000d04: 6b1b ldr r3, [r3, #48] ; 0x30 8000d06: f003 0304 and.w r3, r3, #4 8000d0a: 61bb str r3, [r7, #24] 8000d0c: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOH_CLK_ENABLE(); 8000d0e: 2300 movs r3, #0 8000d10: 617b str r3, [r7, #20] 8000d12: 4b45 ldr r3, [pc, #276] ; (8000e28 ) 8000d14: 6b1b ldr r3, [r3, #48] ; 0x30 8000d16: 4a44 ldr r2, [pc, #272] ; (8000e28 ) 8000d18: f043 0380 orr.w r3, r3, #128 ; 0x80 8000d1c: 6313 str r3, [r2, #48] ; 0x30 8000d1e: 4b42 ldr r3, [pc, #264] ; (8000e28 ) 8000d20: 6b1b ldr r3, [r3, #48] ; 0x30 8000d22: f003 0380 and.w r3, r3, #128 ; 0x80 8000d26: 617b str r3, [r7, #20] 8000d28: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 8000d2a: 2300 movs r3, #0 8000d2c: 613b str r3, [r7, #16] 8000d2e: 4b3e ldr r3, [pc, #248] ; (8000e28 ) 8000d30: 6b1b ldr r3, [r3, #48] ; 0x30 8000d32: 4a3d ldr r2, [pc, #244] ; (8000e28 ) 8000d34: f043 0301 orr.w r3, r3, #1 8000d38: 6313 str r3, [r2, #48] ; 0x30 8000d3a: 4b3b ldr r3, [pc, #236] ; (8000e28 ) 8000d3c: 6b1b ldr r3, [r3, #48] ; 0x30 8000d3e: f003 0301 and.w r3, r3, #1 8000d42: 613b str r3, [r7, #16] 8000d44: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 8000d46: 2300 movs r3, #0 8000d48: 60fb str r3, [r7, #12] 8000d4a: 4b37 ldr r3, [pc, #220] ; (8000e28 ) 8000d4c: 6b1b ldr r3, [r3, #48] ; 0x30 8000d4e: 4a36 ldr r2, [pc, #216] ; (8000e28 ) 8000d50: f043 0302 orr.w r3, r3, #2 8000d54: 6313 str r3, [r2, #48] ; 0x30 8000d56: 4b34 ldr r3, [pc, #208] ; (8000e28 ) 8000d58: 6b1b ldr r3, [r3, #48] ; 0x30 8000d5a: f003 0302 and.w r3, r3, #2 8000d5e: 60fb str r3, [r7, #12] 8000d60: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOD_CLK_ENABLE(); 8000d62: 2300 movs r3, #0 8000d64: 60bb str r3, [r7, #8] 8000d66: 4b30 ldr r3, [pc, #192] ; (8000e28 ) 8000d68: 6b1b ldr r3, [r3, #48] ; 0x30 8000d6a: 4a2f ldr r2, [pc, #188] ; (8000e28 ) 8000d6c: f043 0308 orr.w r3, r3, #8 8000d70: 6313 str r3, [r2, #48] ; 0x30 8000d72: 4b2d ldr r3, [pc, #180] ; (8000e28 ) 8000d74: 6b1b ldr r3, [r3, #48] ; 0x30 8000d76: f003 0308 and.w r3, r3, #8 8000d7a: 60bb str r3, [r7, #8] 8000d7c: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOG_CLK_ENABLE(); 8000d7e: 2300 movs r3, #0 8000d80: 607b str r3, [r7, #4] 8000d82: 4b29 ldr r3, [pc, #164] ; (8000e28 ) 8000d84: 6b1b ldr r3, [r3, #48] ; 0x30 8000d86: 4a28 ldr r2, [pc, #160] ; (8000e28 ) 8000d88: f043 0340 orr.w r3, r3, #64 ; 0x40 8000d8c: 6313 str r3, [r2, #48] ; 0x30 8000d8e: 4b26 ldr r3, [pc, #152] ; (8000e28 ) 8000d90: 6b1b ldr r3, [r3, #48] ; 0x30 8000d92: f003 0340 and.w r3, r3, #64 ; 0x40 8000d96: 607b str r3, [r7, #4] 8000d98: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, LD1_Pin|LD3_Pin|LD2_Pin, GPIO_PIN_RESET); 8000d9a: 2200 movs r2, #0 8000d9c: f244 0181 movw r1, #16513 ; 0x4081 8000da0: 4822 ldr r0, [pc, #136] ; (8000e2c ) 8000da2: f001 f917 bl 8001fd4 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(USB_PowerSwitchOn_GPIO_Port, USB_PowerSwitchOn_Pin, GPIO_PIN_RESET); 8000da6: 2200 movs r2, #0 8000da8: 2140 movs r1, #64 ; 0x40 8000daa: 4821 ldr r0, [pc, #132] ; (8000e30 ) 8000dac: f001 f912 bl 8001fd4 /*Configure GPIO pin : USER_Btn_Pin */ GPIO_InitStruct.Pin = USER_Btn_Pin; 8000db0: f44f 5300 mov.w r3, #8192 ; 0x2000 8000db4: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; 8000db6: f44f 1388 mov.w r3, #1114112 ; 0x110000 8000dba: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000dbc: 2300 movs r3, #0 8000dbe: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(USER_Btn_GPIO_Port, &GPIO_InitStruct); 8000dc0: f107 031c add.w r3, r7, #28 8000dc4: 4619 mov r1, r3 8000dc6: 481b ldr r0, [pc, #108] ; (8000e34 ) 8000dc8: f000 ff58 bl 8001c7c /*Configure GPIO pins : LD1_Pin LD3_Pin LD2_Pin */ GPIO_InitStruct.Pin = LD1_Pin|LD3_Pin|LD2_Pin; 8000dcc: f244 0381 movw r3, #16513 ; 0x4081 8000dd0: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000dd2: 2301 movs r3, #1 8000dd4: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000dd6: 2300 movs r3, #0 8000dd8: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000dda: 2300 movs r3, #0 8000ddc: 62bb str r3, [r7, #40] ; 0x28 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8000dde: f107 031c add.w r3, r7, #28 8000de2: 4619 mov r1, r3 8000de4: 4811 ldr r0, [pc, #68] ; (8000e2c ) 8000de6: f000 ff49 bl 8001c7c /*Configure GPIO pin : USB_PowerSwitchOn_Pin */ GPIO_InitStruct.Pin = USB_PowerSwitchOn_Pin; 8000dea: 2340 movs r3, #64 ; 0x40 8000dec: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000dee: 2301 movs r3, #1 8000df0: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000df2: 2300 movs r3, #0 8000df4: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000df6: 2300 movs r3, #0 8000df8: 62bb str r3, [r7, #40] ; 0x28 HAL_GPIO_Init(USB_PowerSwitchOn_GPIO_Port, &GPIO_InitStruct); 8000dfa: f107 031c add.w r3, r7, #28 8000dfe: 4619 mov r1, r3 8000e00: 480b ldr r0, [pc, #44] ; (8000e30 ) 8000e02: f000 ff3b bl 8001c7c /*Configure GPIO pin : USB_OverCurrent_Pin */ GPIO_InitStruct.Pin = USB_OverCurrent_Pin; 8000e06: 2380 movs r3, #128 ; 0x80 8000e08: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8000e0a: 2300 movs r3, #0 8000e0c: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000e0e: 2300 movs r3, #0 8000e10: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(USB_OverCurrent_GPIO_Port, &GPIO_InitStruct); 8000e12: f107 031c add.w r3, r7, #28 8000e16: 4619 mov r1, r3 8000e18: 4805 ldr r0, [pc, #20] ; (8000e30 ) 8000e1a: f000 ff2f bl 8001c7c /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } 8000e1e: bf00 nop 8000e20: 3730 adds r7, #48 ; 0x30 8000e22: 46bd mov sp, r7 8000e24: bd80 pop {r7, pc} 8000e26: bf00 nop 8000e28: 40023800 .word 0x40023800 8000e2c: 40020400 .word 0x40020400 8000e30: 40021800 .word 0x40021800 8000e34: 40020800 .word 0x40020800 08000e38 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8000e38: b480 push {r7} 8000e3a: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting special-purpose register PRIMASK. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8000e3c: b672 cpsid i } 8000e3e: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8000e40: e7fe b.n 8000e40 ... 08000e44 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8000e44: b480 push {r7} 8000e46: b083 sub sp, #12 8000e48: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8000e4a: 2300 movs r3, #0 8000e4c: 607b str r3, [r7, #4] 8000e4e: 4b10 ldr r3, [pc, #64] ; (8000e90 ) 8000e50: 6c5b ldr r3, [r3, #68] ; 0x44 8000e52: 4a0f ldr r2, [pc, #60] ; (8000e90 ) 8000e54: f443 4380 orr.w r3, r3, #16384 ; 0x4000 8000e58: 6453 str r3, [r2, #68] ; 0x44 8000e5a: 4b0d ldr r3, [pc, #52] ; (8000e90 ) 8000e5c: 6c5b ldr r3, [r3, #68] ; 0x44 8000e5e: f403 4380 and.w r3, r3, #16384 ; 0x4000 8000e62: 607b str r3, [r7, #4] 8000e64: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 8000e66: 2300 movs r3, #0 8000e68: 603b str r3, [r7, #0] 8000e6a: 4b09 ldr r3, [pc, #36] ; (8000e90 ) 8000e6c: 6c1b ldr r3, [r3, #64] ; 0x40 8000e6e: 4a08 ldr r2, [pc, #32] ; (8000e90 ) 8000e70: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8000e74: 6413 str r3, [r2, #64] ; 0x40 8000e76: 4b06 ldr r3, [pc, #24] ; (8000e90 ) 8000e78: 6c1b ldr r3, [r3, #64] ; 0x40 8000e7a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8000e7e: 603b str r3, [r7, #0] 8000e80: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8000e82: bf00 nop 8000e84: 370c adds r7, #12 8000e86: 46bd mov sp, r7 8000e88: f85d 7b04 ldr.w r7, [sp], #4 8000e8c: 4770 bx lr 8000e8e: bf00 nop 8000e90: 40023800 .word 0x40023800 08000e94 : * This function configures the hardware resources used in this example * @param heth: ETH handle pointer * @retval None */ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) { 8000e94: b580 push {r7, lr} 8000e96: b08e sub sp, #56 ; 0x38 8000e98: af00 add r7, sp, #0 8000e9a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000e9c: f107 0324 add.w r3, r7, #36 ; 0x24 8000ea0: 2200 movs r2, #0 8000ea2: 601a str r2, [r3, #0] 8000ea4: 605a str r2, [r3, #4] 8000ea6: 609a str r2, [r3, #8] 8000ea8: 60da str r2, [r3, #12] 8000eaa: 611a str r2, [r3, #16] if(heth->Instance==ETH) 8000eac: 687b ldr r3, [r7, #4] 8000eae: 681b ldr r3, [r3, #0] 8000eb0: 4a55 ldr r2, [pc, #340] ; (8001008 ) 8000eb2: 4293 cmp r3, r2 8000eb4: f040 80a4 bne.w 8001000 { /* USER CODE BEGIN ETH_MspInit 0 */ /* USER CODE END ETH_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ETH_CLK_ENABLE(); 8000eb8: 2300 movs r3, #0 8000eba: 623b str r3, [r7, #32] 8000ebc: 4b53 ldr r3, [pc, #332] ; (800100c ) 8000ebe: 6b1b ldr r3, [r3, #48] ; 0x30 8000ec0: 4a52 ldr r2, [pc, #328] ; (800100c ) 8000ec2: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000 8000ec6: 6313 str r3, [r2, #48] ; 0x30 8000ec8: 4b50 ldr r3, [pc, #320] ; (800100c ) 8000eca: 6b1b ldr r3, [r3, #48] ; 0x30 8000ecc: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8000ed0: 623b str r3, [r7, #32] 8000ed2: 6a3b ldr r3, [r7, #32] 8000ed4: 2300 movs r3, #0 8000ed6: 61fb str r3, [r7, #28] 8000ed8: 4b4c ldr r3, [pc, #304] ; (800100c ) 8000eda: 6b1b ldr r3, [r3, #48] ; 0x30 8000edc: 4a4b ldr r2, [pc, #300] ; (800100c ) 8000ede: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 8000ee2: 6313 str r3, [r2, #48] ; 0x30 8000ee4: 4b49 ldr r3, [pc, #292] ; (800100c ) 8000ee6: 6b1b ldr r3, [r3, #48] ; 0x30 8000ee8: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 8000eec: 61fb str r3, [r7, #28] 8000eee: 69fb ldr r3, [r7, #28] 8000ef0: 2300 movs r3, #0 8000ef2: 61bb str r3, [r7, #24] 8000ef4: 4b45 ldr r3, [pc, #276] ; (800100c ) 8000ef6: 6b1b ldr r3, [r3, #48] ; 0x30 8000ef8: 4a44 ldr r2, [pc, #272] ; (800100c ) 8000efa: f043 6300 orr.w r3, r3, #134217728 ; 0x8000000 8000efe: 6313 str r3, [r2, #48] ; 0x30 8000f00: 4b42 ldr r3, [pc, #264] ; (800100c ) 8000f02: 6b1b ldr r3, [r3, #48] ; 0x30 8000f04: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 8000f08: 61bb str r3, [r7, #24] 8000f0a: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOC_CLK_ENABLE(); 8000f0c: 2300 movs r3, #0 8000f0e: 617b str r3, [r7, #20] 8000f10: 4b3e ldr r3, [pc, #248] ; (800100c ) 8000f12: 6b1b ldr r3, [r3, #48] ; 0x30 8000f14: 4a3d ldr r2, [pc, #244] ; (800100c ) 8000f16: f043 0304 orr.w r3, r3, #4 8000f1a: 6313 str r3, [r2, #48] ; 0x30 8000f1c: 4b3b ldr r3, [pc, #236] ; (800100c ) 8000f1e: 6b1b ldr r3, [r3, #48] ; 0x30 8000f20: f003 0304 and.w r3, r3, #4 8000f24: 617b str r3, [r7, #20] 8000f26: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 8000f28: 2300 movs r3, #0 8000f2a: 613b str r3, [r7, #16] 8000f2c: 4b37 ldr r3, [pc, #220] ; (800100c ) 8000f2e: 6b1b ldr r3, [r3, #48] ; 0x30 8000f30: 4a36 ldr r2, [pc, #216] ; (800100c ) 8000f32: f043 0301 orr.w r3, r3, #1 8000f36: 6313 str r3, [r2, #48] ; 0x30 8000f38: 4b34 ldr r3, [pc, #208] ; (800100c ) 8000f3a: 6b1b ldr r3, [r3, #48] ; 0x30 8000f3c: f003 0301 and.w r3, r3, #1 8000f40: 613b str r3, [r7, #16] 8000f42: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 8000f44: 2300 movs r3, #0 8000f46: 60fb str r3, [r7, #12] 8000f48: 4b30 ldr r3, [pc, #192] ; (800100c ) 8000f4a: 6b1b ldr r3, [r3, #48] ; 0x30 8000f4c: 4a2f ldr r2, [pc, #188] ; (800100c ) 8000f4e: f043 0302 orr.w r3, r3, #2 8000f52: 6313 str r3, [r2, #48] ; 0x30 8000f54: 4b2d ldr r3, [pc, #180] ; (800100c ) 8000f56: 6b1b ldr r3, [r3, #48] ; 0x30 8000f58: f003 0302 and.w r3, r3, #2 8000f5c: 60fb str r3, [r7, #12] 8000f5e: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOG_CLK_ENABLE(); 8000f60: 2300 movs r3, #0 8000f62: 60bb str r3, [r7, #8] 8000f64: 4b29 ldr r3, [pc, #164] ; (800100c ) 8000f66: 6b1b ldr r3, [r3, #48] ; 0x30 8000f68: 4a28 ldr r2, [pc, #160] ; (800100c ) 8000f6a: f043 0340 orr.w r3, r3, #64 ; 0x40 8000f6e: 6313 str r3, [r2, #48] ; 0x30 8000f70: 4b26 ldr r3, [pc, #152] ; (800100c ) 8000f72: 6b1b ldr r3, [r3, #48] ; 0x30 8000f74: f003 0340 and.w r3, r3, #64 ; 0x40 8000f78: 60bb str r3, [r7, #8] 8000f7a: 68bb ldr r3, [r7, #8] PC5 ------> ETH_RXD1 PB13 ------> ETH_TXD1 PG11 ------> ETH_TX_EN PG13 ------> ETH_TXD0 */ GPIO_InitStruct.Pin = RMII_MDC_Pin|RMII_RXD0_Pin|RMII_RXD1_Pin; 8000f7c: 2332 movs r3, #50 ; 0x32 8000f7e: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000f80: 2302 movs r3, #2 8000f82: 62bb str r3, [r7, #40] ; 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000f84: 2300 movs r3, #0 8000f86: 62fb str r3, [r7, #44] ; 0x2c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8000f88: 2303 movs r3, #3 8000f8a: 633b str r3, [r7, #48] ; 0x30 GPIO_InitStruct.Alternate = GPIO_AF11_ETH; 8000f8c: 230b movs r3, #11 8000f8e: 637b str r3, [r7, #52] ; 0x34 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8000f90: f107 0324 add.w r3, r7, #36 ; 0x24 8000f94: 4619 mov r1, r3 8000f96: 481e ldr r0, [pc, #120] ; (8001010 ) 8000f98: f000 fe70 bl 8001c7c GPIO_InitStruct.Pin = RMII_REF_CLK_Pin|RMII_MDIO_Pin|RMII_CRS_DV_Pin; 8000f9c: 2386 movs r3, #134 ; 0x86 8000f9e: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000fa0: 2302 movs r3, #2 8000fa2: 62bb str r3, [r7, #40] ; 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000fa4: 2300 movs r3, #0 8000fa6: 62fb str r3, [r7, #44] ; 0x2c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8000fa8: 2303 movs r3, #3 8000faa: 633b str r3, [r7, #48] ; 0x30 GPIO_InitStruct.Alternate = GPIO_AF11_ETH; 8000fac: 230b movs r3, #11 8000fae: 637b str r3, [r7, #52] ; 0x34 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000fb0: f107 0324 add.w r3, r7, #36 ; 0x24 8000fb4: 4619 mov r1, r3 8000fb6: 4817 ldr r0, [pc, #92] ; (8001014 ) 8000fb8: f000 fe60 bl 8001c7c GPIO_InitStruct.Pin = RMII_TXD1_Pin; 8000fbc: f44f 5300 mov.w r3, #8192 ; 0x2000 8000fc0: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000fc2: 2302 movs r3, #2 8000fc4: 62bb str r3, [r7, #40] ; 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000fc6: 2300 movs r3, #0 8000fc8: 62fb str r3, [r7, #44] ; 0x2c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8000fca: 2303 movs r3, #3 8000fcc: 633b str r3, [r7, #48] ; 0x30 GPIO_InitStruct.Alternate = GPIO_AF11_ETH; 8000fce: 230b movs r3, #11 8000fd0: 637b str r3, [r7, #52] ; 0x34 HAL_GPIO_Init(RMII_TXD1_GPIO_Port, &GPIO_InitStruct); 8000fd2: f107 0324 add.w r3, r7, #36 ; 0x24 8000fd6: 4619 mov r1, r3 8000fd8: 480f ldr r0, [pc, #60] ; (8001018 ) 8000fda: f000 fe4f bl 8001c7c GPIO_InitStruct.Pin = RMII_TX_EN_Pin|RMII_TXD0_Pin; 8000fde: f44f 5320 mov.w r3, #10240 ; 0x2800 8000fe2: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000fe4: 2302 movs r3, #2 8000fe6: 62bb str r3, [r7, #40] ; 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000fe8: 2300 movs r3, #0 8000fea: 62fb str r3, [r7, #44] ; 0x2c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8000fec: 2303 movs r3, #3 8000fee: 633b str r3, [r7, #48] ; 0x30 GPIO_InitStruct.Alternate = GPIO_AF11_ETH; 8000ff0: 230b movs r3, #11 8000ff2: 637b str r3, [r7, #52] ; 0x34 HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); 8000ff4: f107 0324 add.w r3, r7, #36 ; 0x24 8000ff8: 4619 mov r1, r3 8000ffa: 4808 ldr r0, [pc, #32] ; (800101c ) 8000ffc: f000 fe3e bl 8001c7c /* USER CODE END ETH_MspInit 1 */ } } 8001000: bf00 nop 8001002: 3738 adds r7, #56 ; 0x38 8001004: 46bd mov sp, r7 8001006: bd80 pop {r7, pc} 8001008: 40028000 .word 0x40028000 800100c: 40023800 .word 0x40023800 8001010: 40020800 .word 0x40020800 8001014: 40020000 .word 0x40020000 8001018: 40020400 .word 0x40020400 800101c: 40021800 .word 0x40021800 08001020 : * This function configures the hardware resources used in this example * @param hrng: RNG handle pointer * @retval None */ void HAL_RNG_MspInit(RNG_HandleTypeDef* hrng) { 8001020: b480 push {r7} 8001022: b085 sub sp, #20 8001024: af00 add r7, sp, #0 8001026: 6078 str r0, [r7, #4] if(hrng->Instance==RNG) 8001028: 687b ldr r3, [r7, #4] 800102a: 681b ldr r3, [r3, #0] 800102c: 4a0b ldr r2, [pc, #44] ; (800105c ) 800102e: 4293 cmp r3, r2 8001030: d10d bne.n 800104e { /* USER CODE BEGIN RNG_MspInit 0 */ /* USER CODE END RNG_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_RNG_CLK_ENABLE(); 8001032: 2300 movs r3, #0 8001034: 60fb str r3, [r7, #12] 8001036: 4b0a ldr r3, [pc, #40] ; (8001060 ) 8001038: 6b5b ldr r3, [r3, #52] ; 0x34 800103a: 4a09 ldr r2, [pc, #36] ; (8001060 ) 800103c: f043 0340 orr.w r3, r3, #64 ; 0x40 8001040: 6353 str r3, [r2, #52] ; 0x34 8001042: 4b07 ldr r3, [pc, #28] ; (8001060 ) 8001044: 6b5b ldr r3, [r3, #52] ; 0x34 8001046: f003 0340 and.w r3, r3, #64 ; 0x40 800104a: 60fb str r3, [r7, #12] 800104c: 68fb ldr r3, [r7, #12] /* USER CODE END RNG_MspInit 1 */ } } 800104e: bf00 nop 8001050: 3714 adds r7, #20 8001052: 46bd mov sp, r7 8001054: f85d 7b04 ldr.w r7, [sp], #4 8001058: 4770 bx lr 800105a: bf00 nop 800105c: 50060800 .word 0x50060800 8001060: 40023800 .word 0x40023800 08001064 : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { 8001064: b580 push {r7, lr} 8001066: b08c sub sp, #48 ; 0x30 8001068: af00 add r7, sp, #0 800106a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800106c: f107 031c add.w r3, r7, #28 8001070: 2200 movs r2, #0 8001072: 601a str r2, [r3, #0] 8001074: 605a str r2, [r3, #4] 8001076: 609a str r2, [r3, #8] 8001078: 60da str r2, [r3, #12] 800107a: 611a str r2, [r3, #16] if(huart->Instance==USART3) 800107c: 687b ldr r3, [r7, #4] 800107e: 681b ldr r3, [r3, #0] 8001080: 4a33 ldr r2, [pc, #204] ; (8001150 ) 8001082: 4293 cmp r3, r2 8001084: d12d bne.n 80010e2 { /* USER CODE BEGIN USART3_MspInit 0 */ /* USER CODE END USART3_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART3_CLK_ENABLE(); 8001086: 2300 movs r3, #0 8001088: 61bb str r3, [r7, #24] 800108a: 4b32 ldr r3, [pc, #200] ; (8001154 ) 800108c: 6c1b ldr r3, [r3, #64] ; 0x40 800108e: 4a31 ldr r2, [pc, #196] ; (8001154 ) 8001090: f443 2380 orr.w r3, r3, #262144 ; 0x40000 8001094: 6413 str r3, [r2, #64] ; 0x40 8001096: 4b2f ldr r3, [pc, #188] ; (8001154 ) 8001098: 6c1b ldr r3, [r3, #64] ; 0x40 800109a: f403 2380 and.w r3, r3, #262144 ; 0x40000 800109e: 61bb str r3, [r7, #24] 80010a0: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOD_CLK_ENABLE(); 80010a2: 2300 movs r3, #0 80010a4: 617b str r3, [r7, #20] 80010a6: 4b2b ldr r3, [pc, #172] ; (8001154 ) 80010a8: 6b1b ldr r3, [r3, #48] ; 0x30 80010aa: 4a2a ldr r2, [pc, #168] ; (8001154 ) 80010ac: f043 0308 orr.w r3, r3, #8 80010b0: 6313 str r3, [r2, #48] ; 0x30 80010b2: 4b28 ldr r3, [pc, #160] ; (8001154 ) 80010b4: 6b1b ldr r3, [r3, #48] ; 0x30 80010b6: f003 0308 and.w r3, r3, #8 80010ba: 617b str r3, [r7, #20] 80010bc: 697b ldr r3, [r7, #20] /**USART3 GPIO Configuration PD8 ------> USART3_TX PD9 ------> USART3_RX */ GPIO_InitStruct.Pin = STLK_RX_Pin|STLK_TX_Pin; 80010be: f44f 7340 mov.w r3, #768 ; 0x300 80010c2: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80010c4: 2302 movs r3, #2 80010c6: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 80010c8: 2300 movs r3, #0 80010ca: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 80010cc: 2303 movs r3, #3 80010ce: 62bb str r3, [r7, #40] ; 0x28 GPIO_InitStruct.Alternate = GPIO_AF7_USART3; 80010d0: 2307 movs r3, #7 80010d2: 62fb str r3, [r7, #44] ; 0x2c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 80010d4: f107 031c add.w r3, r7, #28 80010d8: 4619 mov r1, r3 80010da: 481f ldr r0, [pc, #124] ; (8001158 ) 80010dc: f000 fdce bl 8001c7c /* USER CODE BEGIN USART6_MspInit 1 */ /* USER CODE END USART6_MspInit 1 */ } } 80010e0: e031 b.n 8001146 else if(huart->Instance==USART6) 80010e2: 687b ldr r3, [r7, #4] 80010e4: 681b ldr r3, [r3, #0] 80010e6: 4a1d ldr r2, [pc, #116] ; (800115c ) 80010e8: 4293 cmp r3, r2 80010ea: d12c bne.n 8001146 __HAL_RCC_USART6_CLK_ENABLE(); 80010ec: 2300 movs r3, #0 80010ee: 613b str r3, [r7, #16] 80010f0: 4b18 ldr r3, [pc, #96] ; (8001154 ) 80010f2: 6c5b ldr r3, [r3, #68] ; 0x44 80010f4: 4a17 ldr r2, [pc, #92] ; (8001154 ) 80010f6: f043 0320 orr.w r3, r3, #32 80010fa: 6453 str r3, [r2, #68] ; 0x44 80010fc: 4b15 ldr r3, [pc, #84] ; (8001154 ) 80010fe: 6c5b ldr r3, [r3, #68] ; 0x44 8001100: f003 0320 and.w r3, r3, #32 8001104: 613b str r3, [r7, #16] 8001106: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOG_CLK_ENABLE(); 8001108: 2300 movs r3, #0 800110a: 60fb str r3, [r7, #12] 800110c: 4b11 ldr r3, [pc, #68] ; (8001154 ) 800110e: 6b1b ldr r3, [r3, #48] ; 0x30 8001110: 4a10 ldr r2, [pc, #64] ; (8001154 ) 8001112: f043 0340 orr.w r3, r3, #64 ; 0x40 8001116: 6313 str r3, [r2, #48] ; 0x30 8001118: 4b0e ldr r3, [pc, #56] ; (8001154 ) 800111a: 6b1b ldr r3, [r3, #48] ; 0x30 800111c: f003 0340 and.w r3, r3, #64 ; 0x40 8001120: 60fb str r3, [r7, #12] 8001122: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_14; 8001124: f44f 4384 mov.w r3, #16896 ; 0x4200 8001128: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800112a: 2302 movs r3, #2 800112c: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 800112e: 2300 movs r3, #0 8001130: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001132: 2303 movs r3, #3 8001134: 62bb str r3, [r7, #40] ; 0x28 GPIO_InitStruct.Alternate = GPIO_AF8_USART6; 8001136: 2308 movs r3, #8 8001138: 62fb str r3, [r7, #44] ; 0x2c HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); 800113a: f107 031c add.w r3, r7, #28 800113e: 4619 mov r1, r3 8001140: 4807 ldr r0, [pc, #28] ; (8001160 ) 8001142: f000 fd9b bl 8001c7c } 8001146: bf00 nop 8001148: 3730 adds r7, #48 ; 0x30 800114a: 46bd mov sp, r7 800114c: bd80 pop {r7, pc} 800114e: bf00 nop 8001150: 40004800 .word 0x40004800 8001154: 40023800 .word 0x40023800 8001158: 40020c00 .word 0x40020c00 800115c: 40011400 .word 0x40011400 8001160: 40021800 .word 0x40021800 08001164 : * This function configures the hardware resources used in this example * @param hpcd: PCD handle pointer * @retval None */ void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd) { 8001164: b580 push {r7, lr} 8001166: b08a sub sp, #40 ; 0x28 8001168: af00 add r7, sp, #0 800116a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800116c: f107 0314 add.w r3, r7, #20 8001170: 2200 movs r2, #0 8001172: 601a str r2, [r3, #0] 8001174: 605a str r2, [r3, #4] 8001176: 609a str r2, [r3, #8] 8001178: 60da str r2, [r3, #12] 800117a: 611a str r2, [r3, #16] if(hpcd->Instance==USB_OTG_FS) 800117c: 687b ldr r3, [r7, #4] 800117e: 681b ldr r3, [r3, #0] 8001180: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000 8001184: d13f bne.n 8001206 { /* USER CODE BEGIN USB_OTG_FS_MspInit 0 */ /* USER CODE END USB_OTG_FS_MspInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 8001186: 2300 movs r3, #0 8001188: 613b str r3, [r7, #16] 800118a: 4b21 ldr r3, [pc, #132] ; (8001210 ) 800118c: 6b1b ldr r3, [r3, #48] ; 0x30 800118e: 4a20 ldr r2, [pc, #128] ; (8001210 ) 8001190: f043 0301 orr.w r3, r3, #1 8001194: 6313 str r3, [r2, #48] ; 0x30 8001196: 4b1e ldr r3, [pc, #120] ; (8001210 ) 8001198: 6b1b ldr r3, [r3, #48] ; 0x30 800119a: f003 0301 and.w r3, r3, #1 800119e: 613b str r3, [r7, #16] 80011a0: 693b ldr r3, [r7, #16] PA9 ------> USB_OTG_FS_VBUS PA10 ------> USB_OTG_FS_ID PA11 ------> USB_OTG_FS_DM PA12 ------> USB_OTG_FS_DP */ GPIO_InitStruct.Pin = USB_SOF_Pin|USB_ID_Pin|USB_DM_Pin|USB_DP_Pin; 80011a2: f44f 53e8 mov.w r3, #7424 ; 0x1d00 80011a6: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80011a8: 2302 movs r3, #2 80011aa: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80011ac: 2300 movs r3, #0 80011ae: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 80011b0: 2303 movs r3, #3 80011b2: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; 80011b4: 230a movs r3, #10 80011b6: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80011b8: f107 0314 add.w r3, r7, #20 80011bc: 4619 mov r1, r3 80011be: 4815 ldr r0, [pc, #84] ; (8001214 ) 80011c0: f000 fd5c bl 8001c7c GPIO_InitStruct.Pin = USB_VBUS_Pin; 80011c4: f44f 7300 mov.w r3, #512 ; 0x200 80011c8: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80011ca: 2300 movs r3, #0 80011cc: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80011ce: 2300 movs r3, #0 80011d0: 61fb str r3, [r7, #28] HAL_GPIO_Init(USB_VBUS_GPIO_Port, &GPIO_InitStruct); 80011d2: f107 0314 add.w r3, r7, #20 80011d6: 4619 mov r1, r3 80011d8: 480e ldr r0, [pc, #56] ; (8001214 ) 80011da: f000 fd4f bl 8001c7c /* Peripheral clock enable */ __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); 80011de: 4b0c ldr r3, [pc, #48] ; (8001210 ) 80011e0: 6b5b ldr r3, [r3, #52] ; 0x34 80011e2: 4a0b ldr r2, [pc, #44] ; (8001210 ) 80011e4: f043 0380 orr.w r3, r3, #128 ; 0x80 80011e8: 6353 str r3, [r2, #52] ; 0x34 80011ea: 2300 movs r3, #0 80011ec: 60fb str r3, [r7, #12] 80011ee: 4b08 ldr r3, [pc, #32] ; (8001210 ) 80011f0: 6c5b ldr r3, [r3, #68] ; 0x44 80011f2: 4a07 ldr r2, [pc, #28] ; (8001210 ) 80011f4: f443 4380 orr.w r3, r3, #16384 ; 0x4000 80011f8: 6453 str r3, [r2, #68] ; 0x44 80011fa: 4b05 ldr r3, [pc, #20] ; (8001210 ) 80011fc: 6c5b ldr r3, [r3, #68] ; 0x44 80011fe: f403 4380 and.w r3, r3, #16384 ; 0x4000 8001202: 60fb str r3, [r7, #12] 8001204: 68fb ldr r3, [r7, #12] /* USER CODE END USB_OTG_FS_MspInit 1 */ } } 8001206: bf00 nop 8001208: 3728 adds r7, #40 ; 0x28 800120a: 46bd mov sp, r7 800120c: bd80 pop {r7, pc} 800120e: bf00 nop 8001210: 40023800 .word 0x40023800 8001214: 40020000 .word 0x40020000 08001218 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8001218: b480 push {r7} 800121a: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 800121c: e7fe b.n 800121c 0800121e : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 800121e: b480 push {r7} 8001220: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8001222: e7fe b.n 8001222 08001224 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8001224: b480 push {r7} 8001226: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8001228: e7fe b.n 8001228 0800122a : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 800122a: b480 push {r7} 800122c: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 800122e: e7fe b.n 800122e 08001230 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8001230: b480 push {r7} 8001232: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8001234: e7fe b.n 8001234 08001236 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8001236: b480 push {r7} 8001238: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 800123a: bf00 nop 800123c: 46bd mov sp, r7 800123e: f85d 7b04 ldr.w r7, [sp], #4 8001242: 4770 bx lr 08001244 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8001244: b480 push {r7} 8001246: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8001248: bf00 nop 800124a: 46bd mov sp, r7 800124c: f85d 7b04 ldr.w r7, [sp], #4 8001250: 4770 bx lr 08001252 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8001252: b480 push {r7} 8001254: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8001256: bf00 nop 8001258: 46bd mov sp, r7 800125a: f85d 7b04 ldr.w r7, [sp], #4 800125e: 4770 bx lr 08001260 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8001260: b580 push {r7, lr} 8001262: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8001264: f000 f890 bl 8001388 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8001268: bf00 nop 800126a: bd80 pop {r7, pc} 0800126c : * configuration. * @param None * @retval None */ void SystemInit(void) { 800126c: b480 push {r7} 800126e: af00 add r7, sp, #0 /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ 8001270: 4b06 ldr r3, [pc, #24] ; (800128c ) 8001272: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 8001276: 4a05 ldr r2, [pc, #20] ; (800128c ) 8001278: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 800127c: f8c2 3088 str.w r3, [r2, #136] ; 0x88 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #endif /* USER_VECT_TAB_ADDRESS */ } 8001280: bf00 nop 8001282: 46bd mov sp, r7 8001284: f85d 7b04 ldr.w r7, [sp], #4 8001288: 4770 bx lr 800128a: bf00 nop 800128c: e000ed00 .word 0xe000ed00 08001290 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ 8001290: f8df d034 ldr.w sp, [pc, #52] ; 80012c8 /* Call the clock system initialization function.*/ bl SystemInit 8001294: f7ff ffea bl 800126c /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8001298: 480c ldr r0, [pc, #48] ; (80012cc ) ldr r1, =_edata 800129a: 490d ldr r1, [pc, #52] ; (80012d0 ) ldr r2, =_sidata 800129c: 4a0d ldr r2, [pc, #52] ; (80012d4 ) movs r3, #0 800129e: 2300 movs r3, #0 b LoopCopyDataInit 80012a0: e002 b.n 80012a8 080012a2 : CopyDataInit: ldr r4, [r2, r3] 80012a2: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 80012a4: 50c4 str r4, [r0, r3] adds r3, r3, #4 80012a6: 3304 adds r3, #4 080012a8 : LoopCopyDataInit: adds r4, r0, r3 80012a8: 18c4 adds r4, r0, r3 cmp r4, r1 80012aa: 428c cmp r4, r1 bcc CopyDataInit 80012ac: d3f9 bcc.n 80012a2 /* Zero fill the bss segment. */ ldr r2, =_sbss 80012ae: 4a0a ldr r2, [pc, #40] ; (80012d8 ) ldr r4, =_ebss 80012b0: 4c0a ldr r4, [pc, #40] ; (80012dc ) movs r3, #0 80012b2: 2300 movs r3, #0 b LoopFillZerobss 80012b4: e001 b.n 80012ba 080012b6 : FillZerobss: str r3, [r2] 80012b6: 6013 str r3, [r2, #0] adds r2, r2, #4 80012b8: 3204 adds r2, #4 080012ba : LoopFillZerobss: cmp r2, r4 80012ba: 42a2 cmp r2, r4 bcc FillZerobss 80012bc: d3fb bcc.n 80012b6 /* Call static constructors */ bl __libc_init_array 80012be: f002 fc3d bl 8003b3c <__libc_init_array> /* Call the application's entry point.*/ bl main 80012c2: f7ff fb53 bl 800096c

bx lr 80012c6: 4770 bx lr ldr sp, =_estack /* set stack pointer */ 80012c8: 20030000 .word 0x20030000 ldr r0, =_sdata 80012cc: 20000000 .word 0x20000000 ldr r1, =_edata 80012d0: 200006c8 .word 0x200006c8 ldr r2, =_sidata 80012d4: 08003c94 .word 0x08003c94 ldr r2, =_sbss 80012d8: 200006c8 .word 0x200006c8 ldr r4, =_ebss 80012dc: 2000123c .word 0x2000123c 080012e0 : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 80012e0: e7fe b.n 80012e0 ... 080012e4 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 80012e4: b580 push {r7, lr} 80012e6: af00 add r7, sp, #0 /* Configure Flash prefetch, Instruction cache, Data cache */ #if (INSTRUCTION_CACHE_ENABLE != 0U) __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); 80012e8: 4b0e ldr r3, [pc, #56] ; (8001324 ) 80012ea: 681b ldr r3, [r3, #0] 80012ec: 4a0d ldr r2, [pc, #52] ; (8001324 ) 80012ee: f443 7300 orr.w r3, r3, #512 ; 0x200 80012f2: 6013 str r3, [r2, #0] #endif /* INSTRUCTION_CACHE_ENABLE */ #if (DATA_CACHE_ENABLE != 0U) __HAL_FLASH_DATA_CACHE_ENABLE(); 80012f4: 4b0b ldr r3, [pc, #44] ; (8001324 ) 80012f6: 681b ldr r3, [r3, #0] 80012f8: 4a0a ldr r2, [pc, #40] ; (8001324 ) 80012fa: f443 6380 orr.w r3, r3, #1024 ; 0x400 80012fe: 6013 str r3, [r2, #0] #endif /* DATA_CACHE_ENABLE */ #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8001300: 4b08 ldr r3, [pc, #32] ; (8001324 ) 8001302: 681b ldr r3, [r3, #0] 8001304: 4a07 ldr r2, [pc, #28] ; (8001324 ) 8001306: f443 7380 orr.w r3, r3, #256 ; 0x100 800130a: 6013 str r3, [r2, #0] #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 800130c: 2003 movs r0, #3 800130e: f000 f931 bl 8001574 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 8001312: 2000 movs r0, #0 8001314: f000 f808 bl 8001328 /* Init the low level hardware */ HAL_MspInit(); 8001318: f7ff fd94 bl 8000e44 /* Return function status */ return HAL_OK; 800131c: 2300 movs r3, #0 } 800131e: 4618 mov r0, r3 8001320: bd80 pop {r7, pc} 8001322: bf00 nop 8001324: 40023c00 .word 0x40023c00 08001328 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8001328: b580 push {r7, lr} 800132a: b082 sub sp, #8 800132c: af00 add r7, sp, #0 800132e: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 8001330: 4b12 ldr r3, [pc, #72] ; (800137c ) 8001332: 681a ldr r2, [r3, #0] 8001334: 4b12 ldr r3, [pc, #72] ; (8001380 ) 8001336: 781b ldrb r3, [r3, #0] 8001338: 4619 mov r1, r3 800133a: f44f 737a mov.w r3, #1000 ; 0x3e8 800133e: fbb3 f3f1 udiv r3, r3, r1 8001342: fbb2 f3f3 udiv r3, r2, r3 8001346: 4618 mov r0, r3 8001348: f000 f93b bl 80015c2 800134c: 4603 mov r3, r0 800134e: 2b00 cmp r3, #0 8001350: d001 beq.n 8001356 { return HAL_ERROR; 8001352: 2301 movs r3, #1 8001354: e00e b.n 8001374 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8001356: 687b ldr r3, [r7, #4] 8001358: 2b0f cmp r3, #15 800135a: d80a bhi.n 8001372 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 800135c: 2200 movs r2, #0 800135e: 6879 ldr r1, [r7, #4] 8001360: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8001364: f000 f911 bl 800158a uwTickPrio = TickPriority; 8001368: 4a06 ldr r2, [pc, #24] ; (8001384 ) 800136a: 687b ldr r3, [r7, #4] 800136c: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 800136e: 2300 movs r3, #0 8001370: e000 b.n 8001374 return HAL_ERROR; 8001372: 2301 movs r3, #1 } 8001374: 4618 mov r0, r3 8001376: 3708 adds r7, #8 8001378: 46bd mov sp, r7 800137a: bd80 pop {r7, pc} 800137c: 200006b8 .word 0x200006b8 8001380: 200006c0 .word 0x200006c0 8001384: 200006bc .word 0x200006bc 08001388 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8001388: b480 push {r7} 800138a: af00 add r7, sp, #0 uwTick += uwTickFreq; 800138c: 4b06 ldr r3, [pc, #24] ; (80013a8 ) 800138e: 781b ldrb r3, [r3, #0] 8001390: 461a mov r2, r3 8001392: 4b06 ldr r3, [pc, #24] ; (80013ac ) 8001394: 681b ldr r3, [r3, #0] 8001396: 4413 add r3, r2 8001398: 4a04 ldr r2, [pc, #16] ; (80013ac ) 800139a: 6013 str r3, [r2, #0] } 800139c: bf00 nop 800139e: 46bd mov sp, r7 80013a0: f85d 7b04 ldr.w r7, [sp], #4 80013a4: 4770 bx lr 80013a6: bf00 nop 80013a8: 200006c0 .word 0x200006c0 80013ac: 200010a0 .word 0x200010a0 080013b0 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 80013b0: b480 push {r7} 80013b2: af00 add r7, sp, #0 return uwTick; 80013b4: 4b03 ldr r3, [pc, #12] ; (80013c4 ) 80013b6: 681b ldr r3, [r3, #0] } 80013b8: 4618 mov r0, r3 80013ba: 46bd mov sp, r7 80013bc: f85d 7b04 ldr.w r7, [sp], #4 80013c0: 4770 bx lr 80013c2: bf00 nop 80013c4: 200010a0 .word 0x200010a0 080013c8 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 80013c8: b580 push {r7, lr} 80013ca: b084 sub sp, #16 80013cc: af00 add r7, sp, #0 80013ce: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 80013d0: f7ff ffee bl 80013b0 80013d4: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 80013d6: 687b ldr r3, [r7, #4] 80013d8: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 80013da: 68fb ldr r3, [r7, #12] 80013dc: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff 80013e0: d005 beq.n 80013ee { wait += (uint32_t)(uwTickFreq); 80013e2: 4b0a ldr r3, [pc, #40] ; (800140c ) 80013e4: 781b ldrb r3, [r3, #0] 80013e6: 461a mov r2, r3 80013e8: 68fb ldr r3, [r7, #12] 80013ea: 4413 add r3, r2 80013ec: 60fb str r3, [r7, #12] } while((HAL_GetTick() - tickstart) < wait) 80013ee: bf00 nop 80013f0: f7ff ffde bl 80013b0 80013f4: 4602 mov r2, r0 80013f6: 68bb ldr r3, [r7, #8] 80013f8: 1ad3 subs r3, r2, r3 80013fa: 68fa ldr r2, [r7, #12] 80013fc: 429a cmp r2, r3 80013fe: d8f7 bhi.n 80013f0 { } } 8001400: bf00 nop 8001402: bf00 nop 8001404: 3710 adds r7, #16 8001406: 46bd mov sp, r7 8001408: bd80 pop {r7, pc} 800140a: bf00 nop 800140c: 200006c0 .word 0x200006c0 08001410 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001410: b480 push {r7} 8001412: b085 sub sp, #20 8001414: af00 add r7, sp, #0 8001416: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8001418: 687b ldr r3, [r7, #4] 800141a: f003 0307 and.w r3, r3, #7 800141e: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8001420: 4b0c ldr r3, [pc, #48] ; (8001454 <__NVIC_SetPriorityGrouping+0x44>) 8001422: 68db ldr r3, [r3, #12] 8001424: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8001426: 68ba ldr r2, [r7, #8] 8001428: f64f 03ff movw r3, #63743 ; 0xf8ff 800142c: 4013 ands r3, r2 800142e: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8001430: 68fb ldr r3, [r7, #12] 8001432: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8001434: 68bb ldr r3, [r7, #8] 8001436: 4313 orrs r3, r2 reg_value = (reg_value | 8001438: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 800143c: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8001440: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8001442: 4a04 ldr r2, [pc, #16] ; (8001454 <__NVIC_SetPriorityGrouping+0x44>) 8001444: 68bb ldr r3, [r7, #8] 8001446: 60d3 str r3, [r2, #12] } 8001448: bf00 nop 800144a: 3714 adds r7, #20 800144c: 46bd mov sp, r7 800144e: f85d 7b04 ldr.w r7, [sp], #4 8001452: 4770 bx lr 8001454: e000ed00 .word 0xe000ed00 08001458 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8001458: b480 push {r7} 800145a: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 800145c: 4b04 ldr r3, [pc, #16] ; (8001470 <__NVIC_GetPriorityGrouping+0x18>) 800145e: 68db ldr r3, [r3, #12] 8001460: 0a1b lsrs r3, r3, #8 8001462: f003 0307 and.w r3, r3, #7 } 8001466: 4618 mov r0, r3 8001468: 46bd mov sp, r7 800146a: f85d 7b04 ldr.w r7, [sp], #4 800146e: 4770 bx lr 8001470: e000ed00 .word 0xe000ed00 08001474 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8001474: b480 push {r7} 8001476: b083 sub sp, #12 8001478: af00 add r7, sp, #0 800147a: 4603 mov r3, r0 800147c: 6039 str r1, [r7, #0] 800147e: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8001480: f997 3007 ldrsb.w r3, [r7, #7] 8001484: 2b00 cmp r3, #0 8001486: db0a blt.n 800149e <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001488: 683b ldr r3, [r7, #0] 800148a: b2da uxtb r2, r3 800148c: 490c ldr r1, [pc, #48] ; (80014c0 <__NVIC_SetPriority+0x4c>) 800148e: f997 3007 ldrsb.w r3, [r7, #7] 8001492: 0112 lsls r2, r2, #4 8001494: b2d2 uxtb r2, r2 8001496: 440b add r3, r1 8001498: f883 2300 strb.w r2, [r3, #768] ; 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 800149c: e00a b.n 80014b4 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800149e: 683b ldr r3, [r7, #0] 80014a0: b2da uxtb r2, r3 80014a2: 4908 ldr r1, [pc, #32] ; (80014c4 <__NVIC_SetPriority+0x50>) 80014a4: 79fb ldrb r3, [r7, #7] 80014a6: f003 030f and.w r3, r3, #15 80014aa: 3b04 subs r3, #4 80014ac: 0112 lsls r2, r2, #4 80014ae: b2d2 uxtb r2, r2 80014b0: 440b add r3, r1 80014b2: 761a strb r2, [r3, #24] } 80014b4: bf00 nop 80014b6: 370c adds r7, #12 80014b8: 46bd mov sp, r7 80014ba: f85d 7b04 ldr.w r7, [sp], #4 80014be: 4770 bx lr 80014c0: e000e100 .word 0xe000e100 80014c4: e000ed00 .word 0xe000ed00 080014c8 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 80014c8: b480 push {r7} 80014ca: b089 sub sp, #36 ; 0x24 80014cc: af00 add r7, sp, #0 80014ce: 60f8 str r0, [r7, #12] 80014d0: 60b9 str r1, [r7, #8] 80014d2: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80014d4: 68fb ldr r3, [r7, #12] 80014d6: f003 0307 and.w r3, r3, #7 80014da: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 80014dc: 69fb ldr r3, [r7, #28] 80014de: f1c3 0307 rsb r3, r3, #7 80014e2: 2b04 cmp r3, #4 80014e4: bf28 it cs 80014e6: 2304 movcs r3, #4 80014e8: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 80014ea: 69fb ldr r3, [r7, #28] 80014ec: 3304 adds r3, #4 80014ee: 2b06 cmp r3, #6 80014f0: d902 bls.n 80014f8 80014f2: 69fb ldr r3, [r7, #28] 80014f4: 3b03 subs r3, #3 80014f6: e000 b.n 80014fa 80014f8: 2300 movs r3, #0 80014fa: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80014fc: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff 8001500: 69bb ldr r3, [r7, #24] 8001502: fa02 f303 lsl.w r3, r2, r3 8001506: 43da mvns r2, r3 8001508: 68bb ldr r3, [r7, #8] 800150a: 401a ands r2, r3 800150c: 697b ldr r3, [r7, #20] 800150e: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8001510: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff 8001514: 697b ldr r3, [r7, #20] 8001516: fa01 f303 lsl.w r3, r1, r3 800151a: 43d9 mvns r1, r3 800151c: 687b ldr r3, [r7, #4] 800151e: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8001520: 4313 orrs r3, r2 ); } 8001522: 4618 mov r0, r3 8001524: 3724 adds r7, #36 ; 0x24 8001526: 46bd mov sp, r7 8001528: f85d 7b04 ldr.w r7, [sp], #4 800152c: 4770 bx lr ... 08001530 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8001530: b580 push {r7, lr} 8001532: b082 sub sp, #8 8001534: af00 add r7, sp, #0 8001536: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8001538: 687b ldr r3, [r7, #4] 800153a: 3b01 subs r3, #1 800153c: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 8001540: d301 bcc.n 8001546 { return (1UL); /* Reload value impossible */ 8001542: 2301 movs r3, #1 8001544: e00f b.n 8001566 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8001546: 4a0a ldr r2, [pc, #40] ; (8001570 ) 8001548: 687b ldr r3, [r7, #4] 800154a: 3b01 subs r3, #1 800154c: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 800154e: 210f movs r1, #15 8001550: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8001554: f7ff ff8e bl 8001474 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8001558: 4b05 ldr r3, [pc, #20] ; (8001570 ) 800155a: 2200 movs r2, #0 800155c: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 800155e: 4b04 ldr r3, [pc, #16] ; (8001570 ) 8001560: 2207 movs r2, #7 8001562: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8001564: 2300 movs r3, #0 } 8001566: 4618 mov r0, r3 8001568: 3708 adds r7, #8 800156a: 46bd mov sp, r7 800156c: bd80 pop {r7, pc} 800156e: bf00 nop 8001570: e000e010 .word 0xe000e010 08001574 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001574: b580 push {r7, lr} 8001576: b082 sub sp, #8 8001578: af00 add r7, sp, #0 800157a: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 800157c: 6878 ldr r0, [r7, #4] 800157e: f7ff ff47 bl 8001410 <__NVIC_SetPriorityGrouping> } 8001582: bf00 nop 8001584: 3708 adds r7, #8 8001586: 46bd mov sp, r7 8001588: bd80 pop {r7, pc} 0800158a : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 800158a: b580 push {r7, lr} 800158c: b086 sub sp, #24 800158e: af00 add r7, sp, #0 8001590: 4603 mov r3, r0 8001592: 60b9 str r1, [r7, #8] 8001594: 607a str r2, [r7, #4] 8001596: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 8001598: 2300 movs r3, #0 800159a: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 800159c: f7ff ff5c bl 8001458 <__NVIC_GetPriorityGrouping> 80015a0: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 80015a2: 687a ldr r2, [r7, #4] 80015a4: 68b9 ldr r1, [r7, #8] 80015a6: 6978 ldr r0, [r7, #20] 80015a8: f7ff ff8e bl 80014c8 80015ac: 4602 mov r2, r0 80015ae: f997 300f ldrsb.w r3, [r7, #15] 80015b2: 4611 mov r1, r2 80015b4: 4618 mov r0, r3 80015b6: f7ff ff5d bl 8001474 <__NVIC_SetPriority> } 80015ba: bf00 nop 80015bc: 3718 adds r7, #24 80015be: 46bd mov sp, r7 80015c0: bd80 pop {r7, pc} 080015c2 : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 80015c2: b580 push {r7, lr} 80015c4: b082 sub sp, #8 80015c6: af00 add r7, sp, #0 80015c8: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 80015ca: 6878 ldr r0, [r7, #4] 80015cc: f7ff ffb0 bl 8001530 80015d0: 4603 mov r3, r0 } 80015d2: 4618 mov r0, r3 80015d4: 3708 adds r7, #8 80015d6: 46bd mov sp, r7 80015d8: bd80 pop {r7, pc} ... 080015dc : * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) { 80015dc: b580 push {r7, lr} 80015de: b084 sub sp, #16 80015e0: af00 add r7, sp, #0 80015e2: 6078 str r0, [r7, #4] uint32_t tickstart; if (heth == NULL) 80015e4: 687b ldr r3, [r7, #4] 80015e6: 2b00 cmp r3, #0 80015e8: d101 bne.n 80015ee { return HAL_ERROR; 80015ea: 2301 movs r3, #1 80015ec: e08a b.n 8001704 } if (heth->gState == HAL_ETH_STATE_RESET) 80015ee: 687b ldr r3, [r7, #4] 80015f0: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 80015f4: 2b00 cmp r3, #0 80015f6: d106 bne.n 8001606 { heth->gState = HAL_ETH_STATE_BUSY; 80015f8: 687b ldr r3, [r7, #4] 80015fa: 2220 movs r2, #32 80015fc: f8c3 2084 str.w r2, [r3, #132] ; 0x84 /* Init the low level hardware */ heth->MspInitCallback(heth); #else /* Init the low level hardware : GPIO, CLOCK, NVIC. */ HAL_ETH_MspInit(heth); 8001600: 6878 ldr r0, [r7, #4] 8001602: f7ff fc47 bl 8000e94 #endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */ } __HAL_RCC_SYSCFG_CLK_ENABLE(); 8001606: 2300 movs r3, #0 8001608: 60bb str r3, [r7, #8] 800160a: 4b40 ldr r3, [pc, #256] ; (800170c ) 800160c: 6c5b ldr r3, [r3, #68] ; 0x44 800160e: 4a3f ldr r2, [pc, #252] ; (800170c ) 8001610: f443 4380 orr.w r3, r3, #16384 ; 0x4000 8001614: 6453 str r3, [r2, #68] ; 0x44 8001616: 4b3d ldr r3, [pc, #244] ; (800170c ) 8001618: 6c5b ldr r3, [r3, #68] ; 0x44 800161a: f403 4380 and.w r3, r3, #16384 ; 0x4000 800161e: 60bb str r3, [r7, #8] 8001620: 68bb ldr r3, [r7, #8] /* Select MII or RMII Mode*/ SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL); 8001622: 4b3b ldr r3, [pc, #236] ; (8001710 ) 8001624: 685b ldr r3, [r3, #4] 8001626: 4a3a ldr r2, [pc, #232] ; (8001710 ) 8001628: f423 0300 bic.w r3, r3, #8388608 ; 0x800000 800162c: 6053 str r3, [r2, #4] SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface; 800162e: 4b38 ldr r3, [pc, #224] ; (8001710 ) 8001630: 685a ldr r2, [r3, #4] 8001632: 687b ldr r3, [r7, #4] 8001634: 689b ldr r3, [r3, #8] 8001636: 4936 ldr r1, [pc, #216] ; (8001710 ) 8001638: 4313 orrs r3, r2 800163a: 604b str r3, [r1, #4] /* Dummy read to sync SYSCFG with ETH */ (void)SYSCFG->PMC; 800163c: 4b34 ldr r3, [pc, #208] ; (8001710 ) 800163e: 685b ldr r3, [r3, #4] /* Ethernet Software reset */ /* Set the SWR bit: resets all MAC subsystem internal registers and logic */ /* After reset all the registers holds their respective reset values */ SET_BIT(heth->Instance->DMABMR, ETH_DMABMR_SR); 8001640: 687b ldr r3, [r7, #4] 8001642: 681b ldr r3, [r3, #0] 8001644: f503 5380 add.w r3, r3, #4096 ; 0x1000 8001648: 681b ldr r3, [r3, #0] 800164a: 687a ldr r2, [r7, #4] 800164c: 6812 ldr r2, [r2, #0] 800164e: f043 0301 orr.w r3, r3, #1 8001652: f502 5280 add.w r2, r2, #4096 ; 0x1000 8001656: 6013 str r3, [r2, #0] /* Get tick */ tickstart = HAL_GetTick(); 8001658: f7ff feaa bl 80013b0 800165c: 60f8 str r0, [r7, #12] /* Wait for software reset */ while (READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_SR) > 0U) 800165e: e011 b.n 8001684 { if (((HAL_GetTick() - tickstart) > ETH_SWRESET_TIMEOUT)) 8001660: f7ff fea6 bl 80013b0 8001664: 4602 mov r2, r0 8001666: 68fb ldr r3, [r7, #12] 8001668: 1ad3 subs r3, r2, r3 800166a: f5b3 7ffa cmp.w r3, #500 ; 0x1f4 800166e: d909 bls.n 8001684 { /* Set Error Code */ heth->ErrorCode = HAL_ETH_ERROR_TIMEOUT; 8001670: 687b ldr r3, [r7, #4] 8001672: 2204 movs r2, #4 8001674: f8c3 2088 str.w r2, [r3, #136] ; 0x88 /* Set State as Error */ heth->gState = HAL_ETH_STATE_ERROR; 8001678: 687b ldr r3, [r7, #4] 800167a: 22e0 movs r2, #224 ; 0xe0 800167c: f8c3 2084 str.w r2, [r3, #132] ; 0x84 /* Return Error */ return HAL_ERROR; 8001680: 2301 movs r3, #1 8001682: e03f b.n 8001704 while (READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_SR) > 0U) 8001684: 687b ldr r3, [r7, #4] 8001686: 681b ldr r3, [r3, #0] 8001688: f503 5380 add.w r3, r3, #4096 ; 0x1000 800168c: 681b ldr r3, [r3, #0] 800168e: f003 0301 and.w r3, r3, #1 8001692: 2b00 cmp r3, #0 8001694: d1e4 bne.n 8001660 } } /*------------------ MAC, MTL and DMA default Configuration ----------------*/ ETH_MACDMAConfig(heth); 8001696: 6878 ldr r0, [r7, #4] 8001698: f000 f97a bl 8001990 /*------------------ DMA Tx Descriptors Configuration ----------------------*/ ETH_DMATxDescListInit(heth); 800169c: 6878 ldr r0, [r7, #4] 800169e: f000 fa25 bl 8001aec /*------------------ DMA Rx Descriptors Configuration ----------------------*/ ETH_DMARxDescListInit(heth); 80016a2: 6878 ldr r0, [r7, #4] 80016a4: f000 fa7b bl 8001b9e /*--------------------- ETHERNET MAC Address Configuration ------------------*/ ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr); 80016a8: 687b ldr r3, [r7, #4] 80016aa: 685b ldr r3, [r3, #4] 80016ac: 461a mov r2, r3 80016ae: 2100 movs r1, #0 80016b0: 6878 ldr r0, [r7, #4] 80016b2: f000 f9e3 bl 8001a7c /* Disable MMC Interrupts */ SET_BIT(heth->Instance->MACIMR, ETH_MACIMR_TSTIM | ETH_MACIMR_PMTIM); 80016b6: 687b ldr r3, [r7, #4] 80016b8: 681b ldr r3, [r3, #0] 80016ba: 6bda ldr r2, [r3, #60] ; 0x3c 80016bc: 687b ldr r3, [r7, #4] 80016be: 681b ldr r3, [r3, #0] 80016c0: f442 7202 orr.w r2, r2, #520 ; 0x208 80016c4: 63da str r2, [r3, #60] ; 0x3c /* Disable Rx MMC Interrupts */ SET_BIT(heth->Instance->MMCRIMR, ETH_MMCRIMR_RGUFM | ETH_MMCRIMR_RFAEM | \ 80016c6: 687b ldr r3, [r7, #4] 80016c8: 681b ldr r3, [r3, #0] 80016ca: f8d3 310c ldr.w r3, [r3, #268] ; 0x10c 80016ce: 687a ldr r2, [r7, #4] 80016d0: 6812 ldr r2, [r2, #0] 80016d2: f443 3300 orr.w r3, r3, #131072 ; 0x20000 80016d6: f043 0360 orr.w r3, r3, #96 ; 0x60 80016da: f8c2 310c str.w r3, [r2, #268] ; 0x10c ETH_MMCRIMR_RFCEM); /* Disable Tx MMC Interrupts */ SET_BIT(heth->Instance->MMCTIMR, ETH_MMCTIMR_TGFM | ETH_MMCTIMR_TGFMSCM | \ 80016de: 687b ldr r3, [r7, #4] 80016e0: 681b ldr r3, [r3, #0] 80016e2: f8d3 2110 ldr.w r2, [r3, #272] ; 0x110 80016e6: 687b ldr r3, [r7, #4] 80016e8: 681b ldr r3, [r3, #0] 80016ea: f442 1203 orr.w r2, r2, #2146304 ; 0x20c000 80016ee: f8c3 2110 str.w r2, [r3, #272] ; 0x110 ETH_MMCTIMR_TGFSCM); heth->ErrorCode = HAL_ETH_ERROR_NONE; 80016f2: 687b ldr r3, [r7, #4] 80016f4: 2200 movs r2, #0 80016f6: f8c3 2088 str.w r2, [r3, #136] ; 0x88 heth->gState = HAL_ETH_STATE_READY; 80016fa: 687b ldr r3, [r7, #4] 80016fc: 2210 movs r2, #16 80016fe: f8c3 2084 str.w r2, [r3, #132] ; 0x84 return HAL_OK; 8001702: 2300 movs r3, #0 } 8001704: 4618 mov r0, r3 8001706: 3710 adds r7, #16 8001708: 46bd mov sp, r7 800170a: bd80 pop {r7, pc} 800170c: 40023800 .word 0x40023800 8001710: 40013800 .word 0x40013800 08001714 : HAL_Delay(ETH_REG_WRITE_DELAY); (heth->Instance)->DMAOMR = tmpreg; } static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, const ETH_MACConfigTypeDef *macconf) { 8001714: b580 push {r7, lr} 8001716: b084 sub sp, #16 8001718: af00 add r7, sp, #0 800171a: 6078 str r0, [r7, #4] 800171c: 6039 str r1, [r7, #0] uint32_t tmpreg1; /*------------------------ ETHERNET MACCR Configuration --------------------*/ /* Get the ETHERNET MACCR value */ tmpreg1 = (heth->Instance)->MACCR; 800171e: 687b ldr r3, [r7, #4] 8001720: 681b ldr r3, [r3, #0] 8001722: 681b ldr r3, [r3, #0] 8001724: 60fb str r3, [r7, #12] /* Clear CSTF, WD, PCE, PS, TE and RE bits */ tmpreg1 &= ETH_MACCR_CLEAR_MASK; 8001726: 68fa ldr r2, [r7, #12] 8001728: 4b53 ldr r3, [pc, #332] ; (8001878 ) 800172a: 4013 ands r3, r2 800172c: 60fb str r3, [r7, #12] tmpreg1 |= (uint32_t)(((uint32_t)macconf->CRCStripTypePacket << 25U) | 800172e: 683b ldr r3, [r7, #0] 8001730: 7b9b ldrb r3, [r3, #14] 8001732: 065b lsls r3, r3, #25 ((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 23U) | 8001734: 683a ldr r2, [r7, #0] 8001736: 7c12 ldrb r2, [r2, #16] 8001738: 2a00 cmp r2, #0 800173a: d102 bne.n 8001742 800173c: f44f 0200 mov.w r2, #8388608 ; 0x800000 8001740: e000 b.n 8001744 8001742: 2200 movs r2, #0 tmpreg1 |= (uint32_t)(((uint32_t)macconf->CRCStripTypePacket << 25U) | 8001744: 4313 orrs r3, r2 ((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 22U) | 8001746: 683a ldr r2, [r7, #0] 8001748: 7c52 ldrb r2, [r2, #17] 800174a: 2a00 cmp r2, #0 800174c: d102 bne.n 8001754 800174e: f44f 0280 mov.w r2, #4194304 ; 0x400000 8001752: e000 b.n 8001756 8001754: 2200 movs r2, #0 ((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 23U) | 8001756: 431a orrs r2, r3 (uint32_t)macconf->InterPacketGapVal | 8001758: 683b ldr r3, [r7, #0] 800175a: 689b ldr r3, [r3, #8] ((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 22U) | 800175c: 431a orrs r2, r3 ((uint32_t)macconf->CarrierSenseDuringTransmit << 16U) | 800175e: 683b ldr r3, [r7, #0] 8001760: 7fdb ldrb r3, [r3, #31] 8001762: 041b lsls r3, r3, #16 (uint32_t)macconf->InterPacketGapVal | 8001764: 431a orrs r2, r3 macconf->Speed | 8001766: 683b ldr r3, [r7, #0] 8001768: 695b ldr r3, [r3, #20] ((uint32_t)macconf->CarrierSenseDuringTransmit << 16U) | 800176a: 4313 orrs r3, r2 ((uint32_t)((macconf->ReceiveOwn == DISABLE) ? 1U : 0U) << 13U) | 800176c: 683a ldr r2, [r7, #0] 800176e: 7f92 ldrb r2, [r2, #30] 8001770: 2a00 cmp r2, #0 8001772: d102 bne.n 800177a 8001774: f44f 5200 mov.w r2, #8192 ; 0x2000 8001778: e000 b.n 800177c 800177a: 2200 movs r2, #0 macconf->Speed | 800177c: 431a orrs r2, r3 ((uint32_t)macconf->LoopbackMode << 12U) | 800177e: 683b ldr r3, [r7, #0] 8001780: 7f1b ldrb r3, [r3, #28] 8001782: 031b lsls r3, r3, #12 ((uint32_t)((macconf->ReceiveOwn == DISABLE) ? 1U : 0U) << 13U) | 8001784: 431a orrs r2, r3 macconf->DuplexMode | 8001786: 683b ldr r3, [r7, #0] 8001788: 699b ldr r3, [r3, #24] ((uint32_t)macconf->LoopbackMode << 12U) | 800178a: 431a orrs r2, r3 ((uint32_t)macconf->ChecksumOffload << 10U) | 800178c: 683b ldr r3, [r7, #0] 800178e: 791b ldrb r3, [r3, #4] 8001790: 029b lsls r3, r3, #10 macconf->DuplexMode | 8001792: 4313 orrs r3, r2 ((uint32_t)((macconf->RetryTransmission == DISABLE) ? 1U : 0U) << 9U) | 8001794: 683a ldr r2, [r7, #0] 8001796: f892 2020 ldrb.w r2, [r2, #32] 800179a: 2a00 cmp r2, #0 800179c: d102 bne.n 80017a4 800179e: f44f 7200 mov.w r2, #512 ; 0x200 80017a2: e000 b.n 80017a6 80017a4: 2200 movs r2, #0 ((uint32_t)macconf->ChecksumOffload << 10U) | 80017a6: 431a orrs r2, r3 ((uint32_t)macconf->AutomaticPadCRCStrip << 7U) | 80017a8: 683b ldr r3, [r7, #0] 80017aa: 7bdb ldrb r3, [r3, #15] 80017ac: 01db lsls r3, r3, #7 ((uint32_t)((macconf->RetryTransmission == DISABLE) ? 1U : 0U) << 9U) | 80017ae: 431a orrs r2, r3 macconf->BackOffLimit | 80017b0: 683b ldr r3, [r7, #0] 80017b2: 6a5b ldr r3, [r3, #36] ; 0x24 ((uint32_t)macconf->AutomaticPadCRCStrip << 7U) | 80017b4: 431a orrs r2, r3 ((uint32_t)macconf->DeferralCheck << 4U)); 80017b6: 683b ldr r3, [r7, #0] 80017b8: f893 3028 ldrb.w r3, [r3, #40] ; 0x28 80017bc: 011b lsls r3, r3, #4 tmpreg1 |= (uint32_t)(((uint32_t)macconf->CRCStripTypePacket << 25U) | 80017be: 4313 orrs r3, r2 80017c0: 68fa ldr r2, [r7, #12] 80017c2: 4313 orrs r3, r2 80017c4: 60fb str r3, [r7, #12] /* Write to ETHERNET MACCR */ (heth->Instance)->MACCR = (uint32_t)tmpreg1; 80017c6: 687b ldr r3, [r7, #4] 80017c8: 681b ldr r3, [r3, #0] 80017ca: 68fa ldr r2, [r7, #12] 80017cc: 601a str r2, [r3, #0] /* Wait until the write operation will be taken into account : at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->MACCR; 80017ce: 687b ldr r3, [r7, #4] 80017d0: 681b ldr r3, [r3, #0] 80017d2: 681b ldr r3, [r3, #0] 80017d4: 60fb str r3, [r7, #12] HAL_Delay(ETH_REG_WRITE_DELAY); 80017d6: 2001 movs r0, #1 80017d8: f7ff fdf6 bl 80013c8 (heth->Instance)->MACCR = tmpreg1; 80017dc: 687b ldr r3, [r7, #4] 80017de: 681b ldr r3, [r3, #0] 80017e0: 68fa ldr r2, [r7, #12] 80017e2: 601a str r2, [r3, #0] /*----------------------- ETHERNET MACFCR Configuration --------------------*/ /* Get the ETHERNET MACFCR value */ tmpreg1 = (heth->Instance)->MACFCR; 80017e4: 687b ldr r3, [r7, #4] 80017e6: 681b ldr r3, [r3, #0] 80017e8: 699b ldr r3, [r3, #24] 80017ea: 60fb str r3, [r7, #12] /* Clear xx bits */ tmpreg1 &= ETH_MACFCR_CLEAR_MASK; 80017ec: 68fa ldr r2, [r7, #12] 80017ee: f64f 7341 movw r3, #65345 ; 0xff41 80017f2: 4013 ands r3, r2 80017f4: 60fb str r3, [r7, #12] tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) | 80017f6: 683b ldr r3, [r7, #0] 80017f8: 6c9b ldr r3, [r3, #72] ; 0x48 80017fa: 041b lsls r3, r3, #16 ((uint32_t)((macconf->ZeroQuantaPause == DISABLE) ? 1U : 0U) << 7U) | 80017fc: 683a ldr r2, [r7, #0] 80017fe: f892 204c ldrb.w r2, [r2, #76] ; 0x4c 8001802: 2a00 cmp r2, #0 8001804: d101 bne.n 800180a 8001806: 2280 movs r2, #128 ; 0x80 8001808: e000 b.n 800180c 800180a: 2200 movs r2, #0 tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) | 800180c: 431a orrs r2, r3 macconf->PauseLowThreshold | 800180e: 683b ldr r3, [r7, #0] 8001810: 6d1b ldr r3, [r3, #80] ; 0x50 ((uint32_t)((macconf->ZeroQuantaPause == DISABLE) ? 1U : 0U) << 7U) | 8001812: 4313 orrs r3, r2 ((uint32_t)((macconf->UnicastPausePacketDetect == ENABLE) ? 1U : 0U) << 3U) | 8001814: 683a ldr r2, [r7, #0] 8001816: f892 2055 ldrb.w r2, [r2, #85] ; 0x55 800181a: 2a01 cmp r2, #1 800181c: d101 bne.n 8001822 800181e: 2208 movs r2, #8 8001820: e000 b.n 8001824 8001822: 2200 movs r2, #0 macconf->PauseLowThreshold | 8001824: 4313 orrs r3, r2 ((uint32_t)((macconf->ReceiveFlowControl == ENABLE) ? 1U : 0U) << 2U) | 8001826: 683a ldr r2, [r7, #0] 8001828: f892 2056 ldrb.w r2, [r2, #86] ; 0x56 800182c: 2a01 cmp r2, #1 800182e: d101 bne.n 8001834 8001830: 2204 movs r2, #4 8001832: e000 b.n 8001836 8001834: 2200 movs r2, #0 ((uint32_t)((macconf->UnicastPausePacketDetect == ENABLE) ? 1U : 0U) << 3U) | 8001836: 4313 orrs r3, r2 ((uint32_t)((macconf->TransmitFlowControl == ENABLE) ? 1U : 0U) << 1U)); 8001838: 683a ldr r2, [r7, #0] 800183a: f892 2054 ldrb.w r2, [r2, #84] ; 0x54 800183e: 2a01 cmp r2, #1 8001840: d101 bne.n 8001846 8001842: 2202 movs r2, #2 8001844: e000 b.n 8001848 8001846: 2200 movs r2, #0 tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) | 8001848: 4313 orrs r3, r2 800184a: 68fa ldr r2, [r7, #12] 800184c: 4313 orrs r3, r2 800184e: 60fb str r3, [r7, #12] /* Write to ETHERNET MACFCR */ (heth->Instance)->MACFCR = (uint32_t)tmpreg1; 8001850: 687b ldr r3, [r7, #4] 8001852: 681b ldr r3, [r3, #0] 8001854: 68fa ldr r2, [r7, #12] 8001856: 619a str r2, [r3, #24] /* Wait until the write operation will be taken into account : at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->MACFCR; 8001858: 687b ldr r3, [r7, #4] 800185a: 681b ldr r3, [r3, #0] 800185c: 699b ldr r3, [r3, #24] 800185e: 60fb str r3, [r7, #12] HAL_Delay(ETH_REG_WRITE_DELAY); 8001860: 2001 movs r0, #1 8001862: f7ff fdb1 bl 80013c8 (heth->Instance)->MACFCR = tmpreg1; 8001866: 687b ldr r3, [r7, #4] 8001868: 681b ldr r3, [r3, #0] 800186a: 68fa ldr r2, [r7, #12] 800186c: 619a str r2, [r3, #24] } 800186e: bf00 nop 8001870: 3710 adds r7, #16 8001872: 46bd mov sp, r7 8001874: bd80 pop {r7, pc} 8001876: bf00 nop 8001878: fd20810f .word 0xfd20810f 0800187c : static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, const ETH_DMAConfigTypeDef *dmaconf) { 800187c: b580 push {r7, lr} 800187e: b084 sub sp, #16 8001880: af00 add r7, sp, #0 8001882: 6078 str r0, [r7, #4] 8001884: 6039 str r1, [r7, #0] uint32_t tmpreg1; /*----------------------- ETHERNET DMAOMR Configuration --------------------*/ /* Get the ETHERNET DMAOMR value */ tmpreg1 = (heth->Instance)->DMAOMR; 8001886: 687b ldr r3, [r7, #4] 8001888: 681b ldr r3, [r3, #0] 800188a: f503 5380 add.w r3, r3, #4096 ; 0x1000 800188e: 699b ldr r3, [r3, #24] 8001890: 60fb str r3, [r7, #12] /* Clear xx bits */ tmpreg1 &= ETH_DMAOMR_CLEAR_MASK; 8001892: 68fa ldr r2, [r7, #12] 8001894: 4b3d ldr r3, [pc, #244] ; (800198c ) 8001896: 4013 ands r3, r2 8001898: 60fb str r3, [r7, #12] tmpreg1 |= (uint32_t)(((uint32_t)((dmaconf->DropTCPIPChecksumErrorFrame == DISABLE) ? 1U : 0U) << 26U) | 800189a: 683b ldr r3, [r7, #0] 800189c: 7b1b ldrb r3, [r3, #12] 800189e: 2b00 cmp r3, #0 80018a0: d102 bne.n 80018a8 80018a2: f04f 6280 mov.w r2, #67108864 ; 0x4000000 80018a6: e000 b.n 80018aa 80018a8: 2200 movs r2, #0 ((uint32_t)dmaconf->ReceiveStoreForward << 25U) | 80018aa: 683b ldr r3, [r7, #0] 80018ac: 7b5b ldrb r3, [r3, #13] 80018ae: 065b lsls r3, r3, #25 tmpreg1 |= (uint32_t)(((uint32_t)((dmaconf->DropTCPIPChecksumErrorFrame == DISABLE) ? 1U : 0U) << 26U) | 80018b0: 4313 orrs r3, r2 ((uint32_t)((dmaconf->FlushRxPacket == DISABLE) ? 1U : 0U) << 20U) | 80018b2: 683a ldr r2, [r7, #0] 80018b4: 7f52 ldrb r2, [r2, #29] 80018b6: 2a00 cmp r2, #0 80018b8: d102 bne.n 80018c0 80018ba: f44f 1280 mov.w r2, #1048576 ; 0x100000 80018be: e000 b.n 80018c2 80018c0: 2200 movs r2, #0 ((uint32_t)dmaconf->ReceiveStoreForward << 25U) | 80018c2: 431a orrs r2, r3 ((uint32_t)dmaconf->TransmitStoreForward << 21U) | 80018c4: 683b ldr r3, [r7, #0] 80018c6: 7b9b ldrb r3, [r3, #14] 80018c8: 055b lsls r3, r3, #21 ((uint32_t)((dmaconf->FlushRxPacket == DISABLE) ? 1U : 0U) << 20U) | 80018ca: 431a orrs r2, r3 dmaconf->TransmitThresholdControl | 80018cc: 683b ldr r3, [r7, #0] 80018ce: 695b ldr r3, [r3, #20] ((uint32_t)dmaconf->TransmitStoreForward << 21U) | 80018d0: 431a orrs r2, r3 ((uint32_t)dmaconf->ForwardErrorFrames << 7U) | 80018d2: 683b ldr r3, [r7, #0] 80018d4: 7f1b ldrb r3, [r3, #28] 80018d6: 01db lsls r3, r3, #7 dmaconf->TransmitThresholdControl | 80018d8: 431a orrs r2, r3 ((uint32_t)dmaconf->ForwardUndersizedGoodFrames << 6U) | 80018da: 683b ldr r3, [r7, #0] 80018dc: 7f9b ldrb r3, [r3, #30] 80018de: 019b lsls r3, r3, #6 ((uint32_t)dmaconf->ForwardErrorFrames << 7U) | 80018e0: 431a orrs r2, r3 dmaconf->ReceiveThresholdControl | 80018e2: 683b ldr r3, [r7, #0] 80018e4: 6a1b ldr r3, [r3, #32] ((uint32_t)dmaconf->ForwardUndersizedGoodFrames << 6U) | 80018e6: 431a orrs r2, r3 ((uint32_t)dmaconf->SecondFrameOperate << 2U)); 80018e8: 683b ldr r3, [r7, #0] 80018ea: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 80018ee: 009b lsls r3, r3, #2 tmpreg1 |= (uint32_t)(((uint32_t)((dmaconf->DropTCPIPChecksumErrorFrame == DISABLE) ? 1U : 0U) << 26U) | 80018f0: 4313 orrs r3, r2 80018f2: 68fa ldr r2, [r7, #12] 80018f4: 4313 orrs r3, r2 80018f6: 60fb str r3, [r7, #12] /* Write to ETHERNET DMAOMR */ (heth->Instance)->DMAOMR = (uint32_t)tmpreg1; 80018f8: 687b ldr r3, [r7, #4] 80018fa: 681b ldr r3, [r3, #0] 80018fc: f503 5380 add.w r3, r3, #4096 ; 0x1000 8001900: 461a mov r2, r3 8001902: 68fb ldr r3, [r7, #12] 8001904: 6193 str r3, [r2, #24] /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->DMAOMR; 8001906: 687b ldr r3, [r7, #4] 8001908: 681b ldr r3, [r3, #0] 800190a: f503 5380 add.w r3, r3, #4096 ; 0x1000 800190e: 699b ldr r3, [r3, #24] 8001910: 60fb str r3, [r7, #12] HAL_Delay(ETH_REG_WRITE_DELAY); 8001912: 2001 movs r0, #1 8001914: f7ff fd58 bl 80013c8 (heth->Instance)->DMAOMR = tmpreg1; 8001918: 687b ldr r3, [r7, #4] 800191a: 681b ldr r3, [r3, #0] 800191c: f503 5380 add.w r3, r3, #4096 ; 0x1000 8001920: 461a mov r2, r3 8001922: 68fb ldr r3, [r7, #12] 8001924: 6193 str r3, [r2, #24] /*----------------------- ETHERNET DMABMR Configuration --------------------*/ (heth->Instance)->DMABMR = (uint32_t)(((uint32_t)dmaconf->AddressAlignedBeats << 25U) | 8001926: 683b ldr r3, [r7, #0] 8001928: 791b ldrb r3, [r3, #4] 800192a: 065a lsls r2, r3, #25 dmaconf->BurstMode | 800192c: 683b ldr r3, [r7, #0] 800192e: 689b ldr r3, [r3, #8] (heth->Instance)->DMABMR = (uint32_t)(((uint32_t)dmaconf->AddressAlignedBeats << 25U) | 8001930: 431a orrs r2, r3 dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or 8001932: 683b ldr r3, [r7, #0] 8001934: 699b ldr r3, [r3, #24] dmaconf->BurstMode | 8001936: 431a orrs r2, r3 Rx it is applied for the other */ dmaconf->TxDMABurstLength | 8001938: 683b ldr r3, [r7, #0] 800193a: 691b ldr r3, [r3, #16] dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or 800193c: 431a orrs r2, r3 ((uint32_t)dmaconf->EnhancedDescriptorFormat << 7U) | 800193e: 683b ldr r3, [r7, #0] 8001940: f893 3025 ldrb.w r3, [r3, #37] ; 0x25 8001944: 01db lsls r3, r3, #7 dmaconf->TxDMABurstLength | 8001946: 431a orrs r2, r3 (dmaconf->DescriptorSkipLength << 2U) | 8001948: 683b ldr r3, [r7, #0] 800194a: 6a9b ldr r3, [r3, #40] ; 0x28 800194c: 009b lsls r3, r3, #2 ((uint32_t)dmaconf->EnhancedDescriptorFormat << 7U) | 800194e: 431a orrs r2, r3 dmaconf->DMAArbitration | 8001950: 683b ldr r3, [r7, #0] 8001952: 681b ldr r3, [r3, #0] (dmaconf->DescriptorSkipLength << 2U) | 8001954: 4313 orrs r3, r2 (heth->Instance)->DMABMR = (uint32_t)(((uint32_t)dmaconf->AddressAlignedBeats << 25U) | 8001956: 687a ldr r2, [r7, #4] 8001958: 6812 ldr r2, [r2, #0] 800195a: f443 0300 orr.w r3, r3, #8388608 ; 0x800000 800195e: f502 5280 add.w r2, r2, #4096 ; 0x1000 8001962: 6013 str r3, [r2, #0] ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->DMABMR; 8001964: 687b ldr r3, [r7, #4] 8001966: 681b ldr r3, [r3, #0] 8001968: f503 5380 add.w r3, r3, #4096 ; 0x1000 800196c: 681b ldr r3, [r3, #0] 800196e: 60fb str r3, [r7, #12] HAL_Delay(ETH_REG_WRITE_DELAY); 8001970: 2001 movs r0, #1 8001972: f7ff fd29 bl 80013c8 (heth->Instance)->DMABMR = tmpreg1; 8001976: 687b ldr r3, [r7, #4] 8001978: 681b ldr r3, [r3, #0] 800197a: f503 5380 add.w r3, r3, #4096 ; 0x1000 800197e: 461a mov r2, r3 8001980: 68fb ldr r3, [r7, #12] 8001982: 6013 str r3, [r2, #0] } 8001984: bf00 nop 8001986: 3710 adds r7, #16 8001988: 46bd mov sp, r7 800198a: bd80 pop {r7, pc} 800198c: f8de3f23 .word 0xf8de3f23 08001990 : * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth) { 8001990: b580 push {r7, lr} 8001992: b0a6 sub sp, #152 ; 0x98 8001994: af00 add r7, sp, #0 8001996: 6078 str r0, [r7, #4] ETH_MACConfigTypeDef macDefaultConf; ETH_DMAConfigTypeDef dmaDefaultConf; /*--------------- ETHERNET MAC registers default Configuration --------------*/ macDefaultConf.Watchdog = ENABLE; 8001998: 2301 movs r3, #1 800199a: f887 3044 strb.w r3, [r7, #68] ; 0x44 macDefaultConf.Jabber = ENABLE; 800199e: 2301 movs r3, #1 80019a0: f887 3045 strb.w r3, [r7, #69] ; 0x45 macDefaultConf.InterPacketGapVal = ETH_INTERFRAMEGAP_96BIT; 80019a4: 2300 movs r3, #0 80019a6: 63fb str r3, [r7, #60] ; 0x3c macDefaultConf.CarrierSenseDuringTransmit = DISABLE; 80019a8: 2300 movs r3, #0 80019aa: f887 3053 strb.w r3, [r7, #83] ; 0x53 macDefaultConf.ReceiveOwn = ENABLE; 80019ae: 2301 movs r3, #1 80019b0: f887 3052 strb.w r3, [r7, #82] ; 0x52 macDefaultConf.LoopbackMode = DISABLE; 80019b4: 2300 movs r3, #0 80019b6: f887 3050 strb.w r3, [r7, #80] ; 0x50 macDefaultConf.CRCStripTypePacket = ENABLE; 80019ba: 2301 movs r3, #1 80019bc: f887 3042 strb.w r3, [r7, #66] ; 0x42 macDefaultConf.ChecksumOffload = ENABLE; 80019c0: 2301 movs r3, #1 80019c2: f887 3038 strb.w r3, [r7, #56] ; 0x38 macDefaultConf.RetryTransmission = DISABLE; 80019c6: 2300 movs r3, #0 80019c8: f887 3054 strb.w r3, [r7, #84] ; 0x54 macDefaultConf.AutomaticPadCRCStrip = DISABLE; 80019cc: 2300 movs r3, #0 80019ce: f887 3043 strb.w r3, [r7, #67] ; 0x43 macDefaultConf.BackOffLimit = ETH_BACKOFFLIMIT_10; 80019d2: 2300 movs r3, #0 80019d4: 65bb str r3, [r7, #88] ; 0x58 macDefaultConf.DeferralCheck = DISABLE; 80019d6: 2300 movs r3, #0 80019d8: f887 305c strb.w r3, [r7, #92] ; 0x5c macDefaultConf.PauseTime = 0x0U; 80019dc: 2300 movs r3, #0 80019de: 67fb str r3, [r7, #124] ; 0x7c macDefaultConf.ZeroQuantaPause = DISABLE; 80019e0: 2300 movs r3, #0 80019e2: f887 3080 strb.w r3, [r7, #128] ; 0x80 macDefaultConf.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4; 80019e6: 2300 movs r3, #0 80019e8: f8c7 3084 str.w r3, [r7, #132] ; 0x84 macDefaultConf.ReceiveFlowControl = DISABLE; 80019ec: 2300 movs r3, #0 80019ee: f887 308a strb.w r3, [r7, #138] ; 0x8a macDefaultConf.TransmitFlowControl = DISABLE; 80019f2: 2300 movs r3, #0 80019f4: f887 3088 strb.w r3, [r7, #136] ; 0x88 macDefaultConf.Speed = ETH_SPEED_100M; 80019f8: f44f 4380 mov.w r3, #16384 ; 0x4000 80019fc: 64bb str r3, [r7, #72] ; 0x48 macDefaultConf.DuplexMode = ETH_FULLDUPLEX_MODE; 80019fe: f44f 6300 mov.w r3, #2048 ; 0x800 8001a02: 64fb str r3, [r7, #76] ; 0x4c macDefaultConf.UnicastPausePacketDetect = DISABLE; 8001a04: 2300 movs r3, #0 8001a06: f887 3089 strb.w r3, [r7, #137] ; 0x89 /* MAC default configuration */ ETH_SetMACConfig(heth, &macDefaultConf); 8001a0a: f107 0334 add.w r3, r7, #52 ; 0x34 8001a0e: 4619 mov r1, r3 8001a10: 6878 ldr r0, [r7, #4] 8001a12: f7ff fe7f bl 8001714 /*--------------- ETHERNET DMA registers default Configuration --------------*/ dmaDefaultConf.DropTCPIPChecksumErrorFrame = ENABLE; 8001a16: 2301 movs r3, #1 8001a18: 753b strb r3, [r7, #20] dmaDefaultConf.ReceiveStoreForward = ENABLE; 8001a1a: 2301 movs r3, #1 8001a1c: 757b strb r3, [r7, #21] dmaDefaultConf.FlushRxPacket = ENABLE; 8001a1e: 2301 movs r3, #1 8001a20: f887 3025 strb.w r3, [r7, #37] ; 0x25 dmaDefaultConf.TransmitStoreForward = ENABLE; 8001a24: 2301 movs r3, #1 8001a26: 75bb strb r3, [r7, #22] dmaDefaultConf.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES; 8001a28: 2300 movs r3, #0 8001a2a: 61fb str r3, [r7, #28] dmaDefaultConf.ForwardErrorFrames = DISABLE; 8001a2c: 2300 movs r3, #0 8001a2e: f887 3024 strb.w r3, [r7, #36] ; 0x24 dmaDefaultConf.ForwardUndersizedGoodFrames = DISABLE; 8001a32: 2300 movs r3, #0 8001a34: f887 3026 strb.w r3, [r7, #38] ; 0x26 dmaDefaultConf.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES; 8001a38: 2300 movs r3, #0 8001a3a: 62bb str r3, [r7, #40] ; 0x28 dmaDefaultConf.SecondFrameOperate = ENABLE; 8001a3c: 2301 movs r3, #1 8001a3e: f887 302c strb.w r3, [r7, #44] ; 0x2c dmaDefaultConf.AddressAlignedBeats = ENABLE; 8001a42: 2301 movs r3, #1 8001a44: 733b strb r3, [r7, #12] dmaDefaultConf.BurstMode = ETH_BURSTLENGTH_FIXED; 8001a46: f44f 3380 mov.w r3, #65536 ; 0x10000 8001a4a: 613b str r3, [r7, #16] dmaDefaultConf.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT; 8001a4c: f44f 0380 mov.w r3, #4194304 ; 0x400000 8001a50: 623b str r3, [r7, #32] dmaDefaultConf.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT; 8001a52: f44f 5300 mov.w r3, #8192 ; 0x2000 8001a56: 61bb str r3, [r7, #24] dmaDefaultConf.EnhancedDescriptorFormat = ENABLE; 8001a58: 2301 movs r3, #1 8001a5a: f887 302d strb.w r3, [r7, #45] ; 0x2d dmaDefaultConf.DescriptorSkipLength = 0x0U; 8001a5e: 2300 movs r3, #0 8001a60: 633b str r3, [r7, #48] ; 0x30 dmaDefaultConf.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1; 8001a62: 2300 movs r3, #0 8001a64: 60bb str r3, [r7, #8] /* DMA default configuration */ ETH_SetDMAConfig(heth, &dmaDefaultConf); 8001a66: f107 0308 add.w r3, r7, #8 8001a6a: 4619 mov r1, r3 8001a6c: 6878 ldr r0, [r7, #4] 8001a6e: f7ff ff05 bl 800187c } 8001a72: bf00 nop 8001a74: 3798 adds r7, #152 ; 0x98 8001a76: 46bd mov sp, r7 8001a78: bd80 pop {r7, pc} ... 08001a7c : * @arg ETH_MAC_Address3: MAC Address3 * @param Addr Pointer to MAC address buffer data (6 bytes) * @retval HAL status */ static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr) { 8001a7c: b480 push {r7} 8001a7e: b087 sub sp, #28 8001a80: af00 add r7, sp, #0 8001a82: 60f8 str r0, [r7, #12] 8001a84: 60b9 str r1, [r7, #8] 8001a86: 607a str r2, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(heth); /* Calculate the selected MAC address high register */ tmpreg1 = ((uint32_t)Addr[5U] << 8U) | (uint32_t)Addr[4U]; 8001a88: 687b ldr r3, [r7, #4] 8001a8a: 3305 adds r3, #5 8001a8c: 781b ldrb r3, [r3, #0] 8001a8e: 021b lsls r3, r3, #8 8001a90: 687a ldr r2, [r7, #4] 8001a92: 3204 adds r2, #4 8001a94: 7812 ldrb r2, [r2, #0] 8001a96: 4313 orrs r3, r2 8001a98: 617b str r3, [r7, #20] /* Load the selected MAC address high register */ (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg1; 8001a9a: 68ba ldr r2, [r7, #8] 8001a9c: 4b11 ldr r3, [pc, #68] ; (8001ae4 ) 8001a9e: 4413 add r3, r2 8001aa0: 461a mov r2, r3 8001aa2: 697b ldr r3, [r7, #20] 8001aa4: 6013 str r3, [r2, #0] /* Calculate the selected MAC address low register */ tmpreg1 = ((uint32_t)Addr[3U] << 24U) | ((uint32_t)Addr[2U] << 16U) | ((uint32_t)Addr[1U] << 8U) | Addr[0U]; 8001aa6: 687b ldr r3, [r7, #4] 8001aa8: 3303 adds r3, #3 8001aaa: 781b ldrb r3, [r3, #0] 8001aac: 061a lsls r2, r3, #24 8001aae: 687b ldr r3, [r7, #4] 8001ab0: 3302 adds r3, #2 8001ab2: 781b ldrb r3, [r3, #0] 8001ab4: 041b lsls r3, r3, #16 8001ab6: 431a orrs r2, r3 8001ab8: 687b ldr r3, [r7, #4] 8001aba: 3301 adds r3, #1 8001abc: 781b ldrb r3, [r3, #0] 8001abe: 021b lsls r3, r3, #8 8001ac0: 4313 orrs r3, r2 8001ac2: 687a ldr r2, [r7, #4] 8001ac4: 7812 ldrb r2, [r2, #0] 8001ac6: 4313 orrs r3, r2 8001ac8: 617b str r3, [r7, #20] /* Load the selected MAC address low register */ (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg1; 8001aca: 68ba ldr r2, [r7, #8] 8001acc: 4b06 ldr r3, [pc, #24] ; (8001ae8 ) 8001ace: 4413 add r3, r2 8001ad0: 461a mov r2, r3 8001ad2: 697b ldr r3, [r7, #20] 8001ad4: 6013 str r3, [r2, #0] } 8001ad6: bf00 nop 8001ad8: 371c adds r7, #28 8001ada: 46bd mov sp, r7 8001adc: f85d 7b04 ldr.w r7, [sp], #4 8001ae0: 4770 bx lr 8001ae2: bf00 nop 8001ae4: 40028040 .word 0x40028040 8001ae8: 40028044 .word 0x40028044 08001aec : * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth) { 8001aec: b480 push {r7} 8001aee: b085 sub sp, #20 8001af0: af00 add r7, sp, #0 8001af2: 6078 str r0, [r7, #4] ETH_DMADescTypeDef *dmatxdesc; uint32_t i; /* Fill each DMATxDesc descriptor with the right values */ for (i = 0; i < (uint32_t)ETH_TX_DESC_CNT; i++) 8001af4: 2300 movs r3, #0 8001af6: 60fb str r3, [r7, #12] 8001af8: e03e b.n 8001b78 { dmatxdesc = heth->Init.TxDesc + i; 8001afa: 687b ldr r3, [r7, #4] 8001afc: 68d9 ldr r1, [r3, #12] 8001afe: 68fa ldr r2, [r7, #12] 8001b00: 4613 mov r3, r2 8001b02: 009b lsls r3, r3, #2 8001b04: 4413 add r3, r2 8001b06: 00db lsls r3, r3, #3 8001b08: 440b add r3, r1 8001b0a: 60bb str r3, [r7, #8] WRITE_REG(dmatxdesc->DESC0, 0x0U); 8001b0c: 68bb ldr r3, [r7, #8] 8001b0e: 2200 movs r2, #0 8001b10: 601a str r2, [r3, #0] WRITE_REG(dmatxdesc->DESC1, 0x0U); 8001b12: 68bb ldr r3, [r7, #8] 8001b14: 2200 movs r2, #0 8001b16: 605a str r2, [r3, #4] WRITE_REG(dmatxdesc->DESC2, 0x0U); 8001b18: 68bb ldr r3, [r7, #8] 8001b1a: 2200 movs r2, #0 8001b1c: 609a str r2, [r3, #8] WRITE_REG(dmatxdesc->DESC3, 0x0U); 8001b1e: 68bb ldr r3, [r7, #8] 8001b20: 2200 movs r2, #0 8001b22: 60da str r2, [r3, #12] WRITE_REG(heth->TxDescList.TxDesc[i], (uint32_t)dmatxdesc); 8001b24: 68b9 ldr r1, [r7, #8] 8001b26: 687b ldr r3, [r7, #4] 8001b28: 68fa ldr r2, [r7, #12] 8001b2a: 3206 adds r2, #6 8001b2c: f843 1022 str.w r1, [r3, r2, lsl #2] /* Set Second Address Chained bit */ SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_TCH); 8001b30: 68bb ldr r3, [r7, #8] 8001b32: 681b ldr r3, [r3, #0] 8001b34: f443 1280 orr.w r2, r3, #1048576 ; 0x100000 8001b38: 68bb ldr r3, [r7, #8] 8001b3a: 601a str r2, [r3, #0] if (i < ((uint32_t)ETH_TX_DESC_CNT - 1U)) 8001b3c: 68fb ldr r3, [r7, #12] 8001b3e: 2b02 cmp r3, #2 8001b40: d80c bhi.n 8001b5c { WRITE_REG(dmatxdesc->DESC3, (uint32_t)(heth->Init.TxDesc + i + 1U)); 8001b42: 687b ldr r3, [r7, #4] 8001b44: 68d9 ldr r1, [r3, #12] 8001b46: 68fb ldr r3, [r7, #12] 8001b48: 1c5a adds r2, r3, #1 8001b4a: 4613 mov r3, r2 8001b4c: 009b lsls r3, r3, #2 8001b4e: 4413 add r3, r2 8001b50: 00db lsls r3, r3, #3 8001b52: 440b add r3, r1 8001b54: 461a mov r2, r3 8001b56: 68bb ldr r3, [r7, #8] 8001b58: 60da str r2, [r3, #12] 8001b5a: e004 b.n 8001b66 } else { WRITE_REG(dmatxdesc->DESC3, (uint32_t)(heth->Init.TxDesc)); 8001b5c: 687b ldr r3, [r7, #4] 8001b5e: 68db ldr r3, [r3, #12] 8001b60: 461a mov r2, r3 8001b62: 68bb ldr r3, [r7, #8] 8001b64: 60da str r2, [r3, #12] } /* Set the DMA Tx descriptors checksum insertion */ SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL); 8001b66: 68bb ldr r3, [r7, #8] 8001b68: 681b ldr r3, [r3, #0] 8001b6a: f443 0240 orr.w r2, r3, #12582912 ; 0xc00000 8001b6e: 68bb ldr r3, [r7, #8] 8001b70: 601a str r2, [r3, #0] for (i = 0; i < (uint32_t)ETH_TX_DESC_CNT; i++) 8001b72: 68fb ldr r3, [r7, #12] 8001b74: 3301 adds r3, #1 8001b76: 60fb str r3, [r7, #12] 8001b78: 68fb ldr r3, [r7, #12] 8001b7a: 2b03 cmp r3, #3 8001b7c: d9bd bls.n 8001afa } heth->TxDescList.CurTxDesc = 0; 8001b7e: 687b ldr r3, [r7, #4] 8001b80: 2200 movs r2, #0 8001b82: 629a str r2, [r3, #40] ; 0x28 /* Set Transmit Descriptor List Address */ WRITE_REG(heth->Instance->DMATDLAR, (uint32_t) heth->Init.TxDesc); 8001b84: 687b ldr r3, [r7, #4] 8001b86: 68da ldr r2, [r3, #12] 8001b88: 687b ldr r3, [r7, #4] 8001b8a: 681b ldr r3, [r3, #0] 8001b8c: f503 5380 add.w r3, r3, #4096 ; 0x1000 8001b90: 611a str r2, [r3, #16] } 8001b92: bf00 nop 8001b94: 3714 adds r7, #20 8001b96: 46bd mov sp, r7 8001b98: f85d 7b04 ldr.w r7, [sp], #4 8001b9c: 4770 bx lr 08001b9e : * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth) { 8001b9e: b480 push {r7} 8001ba0: b085 sub sp, #20 8001ba2: af00 add r7, sp, #0 8001ba4: 6078 str r0, [r7, #4] ETH_DMADescTypeDef *dmarxdesc; uint32_t i; for (i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++) 8001ba6: 2300 movs r3, #0 8001ba8: 60fb str r3, [r7, #12] 8001baa: e048 b.n 8001c3e { dmarxdesc = heth->Init.RxDesc + i; 8001bac: 687b ldr r3, [r7, #4] 8001bae: 6919 ldr r1, [r3, #16] 8001bb0: 68fa ldr r2, [r7, #12] 8001bb2: 4613 mov r3, r2 8001bb4: 009b lsls r3, r3, #2 8001bb6: 4413 add r3, r2 8001bb8: 00db lsls r3, r3, #3 8001bba: 440b add r3, r1 8001bbc: 60bb str r3, [r7, #8] WRITE_REG(dmarxdesc->DESC0, 0x0U); 8001bbe: 68bb ldr r3, [r7, #8] 8001bc0: 2200 movs r2, #0 8001bc2: 601a str r2, [r3, #0] WRITE_REG(dmarxdesc->DESC1, 0x0U); 8001bc4: 68bb ldr r3, [r7, #8] 8001bc6: 2200 movs r2, #0 8001bc8: 605a str r2, [r3, #4] WRITE_REG(dmarxdesc->DESC2, 0x0U); 8001bca: 68bb ldr r3, [r7, #8] 8001bcc: 2200 movs r2, #0 8001bce: 609a str r2, [r3, #8] WRITE_REG(dmarxdesc->DESC3, 0x0U); 8001bd0: 68bb ldr r3, [r7, #8] 8001bd2: 2200 movs r2, #0 8001bd4: 60da str r2, [r3, #12] WRITE_REG(dmarxdesc->BackupAddr0, 0x0U); 8001bd6: 68bb ldr r3, [r7, #8] 8001bd8: 2200 movs r2, #0 8001bda: 621a str r2, [r3, #32] WRITE_REG(dmarxdesc->BackupAddr1, 0x0U); 8001bdc: 68bb ldr r3, [r7, #8] 8001bde: 2200 movs r2, #0 8001be0: 625a str r2, [r3, #36] ; 0x24 /* Set Own bit of the Rx descriptor Status */ dmarxdesc->DESC0 = ETH_DMARXDESC_OWN; 8001be2: 68bb ldr r3, [r7, #8] 8001be4: f04f 4200 mov.w r2, #2147483648 ; 0x80000000 8001be8: 601a str r2, [r3, #0] /* Set Buffer1 size and Second Address Chained bit */ dmarxdesc->DESC1 = heth->Init.RxBuffLen | ETH_DMARXDESC_RCH; 8001bea: 687b ldr r3, [r7, #4] 8001bec: 695b ldr r3, [r3, #20] 8001bee: f443 4280 orr.w r2, r3, #16384 ; 0x4000 8001bf2: 68bb ldr r3, [r7, #8] 8001bf4: 605a str r2, [r3, #4] /* Enable Ethernet DMA Rx Descriptor interrupt */ dmarxdesc->DESC1 &= ~ETH_DMARXDESC_DIC; 8001bf6: 68bb ldr r3, [r7, #8] 8001bf8: 685b ldr r3, [r3, #4] 8001bfa: f023 4200 bic.w r2, r3, #2147483648 ; 0x80000000 8001bfe: 68bb ldr r3, [r7, #8] 8001c00: 605a str r2, [r3, #4] /* Set Rx descritors addresses */ WRITE_REG(heth->RxDescList.RxDesc[i], (uint32_t)dmarxdesc); 8001c02: 68b9 ldr r1, [r7, #8] 8001c04: 687b ldr r3, [r7, #4] 8001c06: 68fa ldr r2, [r7, #12] 8001c08: 3212 adds r2, #18 8001c0a: f843 1022 str.w r1, [r3, r2, lsl #2] if (i < ((uint32_t)ETH_RX_DESC_CNT - 1U)) 8001c0e: 68fb ldr r3, [r7, #12] 8001c10: 2b02 cmp r3, #2 8001c12: d80c bhi.n 8001c2e { WRITE_REG(dmarxdesc->DESC3, (uint32_t)(heth->Init.RxDesc + i + 1U)); 8001c14: 687b ldr r3, [r7, #4] 8001c16: 6919 ldr r1, [r3, #16] 8001c18: 68fb ldr r3, [r7, #12] 8001c1a: 1c5a adds r2, r3, #1 8001c1c: 4613 mov r3, r2 8001c1e: 009b lsls r3, r3, #2 8001c20: 4413 add r3, r2 8001c22: 00db lsls r3, r3, #3 8001c24: 440b add r3, r1 8001c26: 461a mov r2, r3 8001c28: 68bb ldr r3, [r7, #8] 8001c2a: 60da str r2, [r3, #12] 8001c2c: e004 b.n 8001c38 } else { WRITE_REG(dmarxdesc->DESC3, (uint32_t)(heth->Init.RxDesc)); 8001c2e: 687b ldr r3, [r7, #4] 8001c30: 691b ldr r3, [r3, #16] 8001c32: 461a mov r2, r3 8001c34: 68bb ldr r3, [r7, #8] 8001c36: 60da str r2, [r3, #12] for (i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++) 8001c38: 68fb ldr r3, [r7, #12] 8001c3a: 3301 adds r3, #1 8001c3c: 60fb str r3, [r7, #12] 8001c3e: 68fb ldr r3, [r7, #12] 8001c40: 2b03 cmp r3, #3 8001c42: d9b3 bls.n 8001bac } } WRITE_REG(heth->RxDescList.RxDescIdx, 0U); 8001c44: 687b ldr r3, [r7, #4] 8001c46: 2200 movs r2, #0 8001c48: 65da str r2, [r3, #92] ; 0x5c WRITE_REG(heth->RxDescList.RxDescCnt, 0U); 8001c4a: 687b ldr r3, [r7, #4] 8001c4c: 2200 movs r2, #0 8001c4e: 661a str r2, [r3, #96] ; 0x60 WRITE_REG(heth->RxDescList.RxBuildDescIdx, 0U); 8001c50: 687b ldr r3, [r7, #4] 8001c52: 2200 movs r2, #0 8001c54: 669a str r2, [r3, #104] ; 0x68 WRITE_REG(heth->RxDescList.RxBuildDescCnt, 0U); 8001c56: 687b ldr r3, [r7, #4] 8001c58: 2200 movs r2, #0 8001c5a: 66da str r2, [r3, #108] ; 0x6c WRITE_REG(heth->RxDescList.ItMode, 0U); 8001c5c: 687b ldr r3, [r7, #4] 8001c5e: 2200 movs r2, #0 8001c60: 659a str r2, [r3, #88] ; 0x58 /* Set Receive Descriptor List Address */ WRITE_REG(heth->Instance->DMARDLAR, (uint32_t) heth->Init.RxDesc); 8001c62: 687b ldr r3, [r7, #4] 8001c64: 691a ldr r2, [r3, #16] 8001c66: 687b ldr r3, [r7, #4] 8001c68: 681b ldr r3, [r3, #0] 8001c6a: f503 5380 add.w r3, r3, #4096 ; 0x1000 8001c6e: 60da str r2, [r3, #12] } 8001c70: bf00 nop 8001c72: 3714 adds r7, #20 8001c74: 46bd mov sp, r7 8001c76: f85d 7b04 ldr.w r7, [sp], #4 8001c7a: 4770 bx lr 08001c7c : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8001c7c: b480 push {r7} 8001c7e: b089 sub sp, #36 ; 0x24 8001c80: af00 add r7, sp, #0 8001c82: 6078 str r0, [r7, #4] 8001c84: 6039 str r1, [r7, #0] uint32_t position; uint32_t ioposition = 0x00U; 8001c86: 2300 movs r3, #0 8001c88: 617b str r3, [r7, #20] uint32_t iocurrent = 0x00U; 8001c8a: 2300 movs r3, #0 8001c8c: 613b str r3, [r7, #16] uint32_t temp = 0x00U; 8001c8e: 2300 movs r3, #0 8001c90: 61bb str r3, [r7, #24] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ for(position = 0U; position < GPIO_NUMBER; position++) 8001c92: 2300 movs r3, #0 8001c94: 61fb str r3, [r7, #28] 8001c96: e177 b.n 8001f88 { /* Get the IO position */ ioposition = 0x01U << position; 8001c98: 2201 movs r2, #1 8001c9a: 69fb ldr r3, [r7, #28] 8001c9c: fa02 f303 lsl.w r3, r2, r3 8001ca0: 617b str r3, [r7, #20] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 8001ca2: 683b ldr r3, [r7, #0] 8001ca4: 681b ldr r3, [r3, #0] 8001ca6: 697a ldr r2, [r7, #20] 8001ca8: 4013 ands r3, r2 8001caa: 613b str r3, [r7, #16] if(iocurrent == ioposition) 8001cac: 693a ldr r2, [r7, #16] 8001cae: 697b ldr r3, [r7, #20] 8001cb0: 429a cmp r2, r3 8001cb2: f040 8166 bne.w 8001f82 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ 8001cb6: 683b ldr r3, [r7, #0] 8001cb8: 685b ldr r3, [r3, #4] 8001cba: f003 0303 and.w r3, r3, #3 8001cbe: 2b01 cmp r3, #1 8001cc0: d005 beq.n 8001cce (GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8001cc2: 683b ldr r3, [r7, #0] 8001cc4: 685b ldr r3, [r3, #4] 8001cc6: f003 0303 and.w r3, r3, #3 if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ 8001cca: 2b02 cmp r3, #2 8001ccc: d130 bne.n 8001d30 { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 8001cce: 687b ldr r3, [r7, #4] 8001cd0: 689b ldr r3, [r3, #8] 8001cd2: 61bb str r3, [r7, #24] temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); 8001cd4: 69fb ldr r3, [r7, #28] 8001cd6: 005b lsls r3, r3, #1 8001cd8: 2203 movs r2, #3 8001cda: fa02 f303 lsl.w r3, r2, r3 8001cde: 43db mvns r3, r3 8001ce0: 69ba ldr r2, [r7, #24] 8001ce2: 4013 ands r3, r2 8001ce4: 61bb str r3, [r7, #24] temp |= (GPIO_Init->Speed << (position * 2U)); 8001ce6: 683b ldr r3, [r7, #0] 8001ce8: 68da ldr r2, [r3, #12] 8001cea: 69fb ldr r3, [r7, #28] 8001cec: 005b lsls r3, r3, #1 8001cee: fa02 f303 lsl.w r3, r2, r3 8001cf2: 69ba ldr r2, [r7, #24] 8001cf4: 4313 orrs r3, r2 8001cf6: 61bb str r3, [r7, #24] GPIOx->OSPEEDR = temp; 8001cf8: 687b ldr r3, [r7, #4] 8001cfa: 69ba ldr r2, [r7, #24] 8001cfc: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 8001cfe: 687b ldr r3, [r7, #4] 8001d00: 685b ldr r3, [r3, #4] 8001d02: 61bb str r3, [r7, #24] temp &= ~(GPIO_OTYPER_OT_0 << position) ; 8001d04: 2201 movs r2, #1 8001d06: 69fb ldr r3, [r7, #28] 8001d08: fa02 f303 lsl.w r3, r2, r3 8001d0c: 43db mvns r3, r3 8001d0e: 69ba ldr r2, [r7, #24] 8001d10: 4013 ands r3, r2 8001d12: 61bb str r3, [r7, #24] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 8001d14: 683b ldr r3, [r7, #0] 8001d16: 685b ldr r3, [r3, #4] 8001d18: 091b lsrs r3, r3, #4 8001d1a: f003 0201 and.w r2, r3, #1 8001d1e: 69fb ldr r3, [r7, #28] 8001d20: fa02 f303 lsl.w r3, r2, r3 8001d24: 69ba ldr r2, [r7, #24] 8001d26: 4313 orrs r3, r2 8001d28: 61bb str r3, [r7, #24] GPIOx->OTYPER = temp; 8001d2a: 687b ldr r3, [r7, #4] 8001d2c: 69ba ldr r2, [r7, #24] 8001d2e: 605a str r2, [r3, #4] } if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 8001d30: 683b ldr r3, [r7, #0] 8001d32: 685b ldr r3, [r3, #4] 8001d34: f003 0303 and.w r3, r3, #3 8001d38: 2b03 cmp r3, #3 8001d3a: d017 beq.n 8001d6c { /* Check the parameters */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 8001d3c: 687b ldr r3, [r7, #4] 8001d3e: 68db ldr r3, [r3, #12] 8001d40: 61bb str r3, [r7, #24] temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); 8001d42: 69fb ldr r3, [r7, #28] 8001d44: 005b lsls r3, r3, #1 8001d46: 2203 movs r2, #3 8001d48: fa02 f303 lsl.w r3, r2, r3 8001d4c: 43db mvns r3, r3 8001d4e: 69ba ldr r2, [r7, #24] 8001d50: 4013 ands r3, r2 8001d52: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Pull) << (position * 2U)); 8001d54: 683b ldr r3, [r7, #0] 8001d56: 689a ldr r2, [r3, #8] 8001d58: 69fb ldr r3, [r7, #28] 8001d5a: 005b lsls r3, r3, #1 8001d5c: fa02 f303 lsl.w r3, r2, r3 8001d60: 69ba ldr r2, [r7, #24] 8001d62: 4313 orrs r3, r2 8001d64: 61bb str r3, [r7, #24] GPIOx->PUPDR = temp; 8001d66: 687b ldr r3, [r7, #4] 8001d68: 69ba ldr r2, [r7, #24] 8001d6a: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8001d6c: 683b ldr r3, [r7, #0] 8001d6e: 685b ldr r3, [r3, #4] 8001d70: f003 0303 and.w r3, r3, #3 8001d74: 2b02 cmp r3, #2 8001d76: d123 bne.n 8001dc0 { /* Check the Alternate function parameter */ assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; 8001d78: 69fb ldr r3, [r7, #28] 8001d7a: 08da lsrs r2, r3, #3 8001d7c: 687b ldr r3, [r7, #4] 8001d7e: 3208 adds r2, #8 8001d80: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8001d84: 61bb str r3, [r7, #24] temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; 8001d86: 69fb ldr r3, [r7, #28] 8001d88: f003 0307 and.w r3, r3, #7 8001d8c: 009b lsls r3, r3, #2 8001d8e: 220f movs r2, #15 8001d90: fa02 f303 lsl.w r3, r2, r3 8001d94: 43db mvns r3, r3 8001d96: 69ba ldr r2, [r7, #24] 8001d98: 4013 ands r3, r2 8001d9a: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U)); 8001d9c: 683b ldr r3, [r7, #0] 8001d9e: 691a ldr r2, [r3, #16] 8001da0: 69fb ldr r3, [r7, #28] 8001da2: f003 0307 and.w r3, r3, #7 8001da6: 009b lsls r3, r3, #2 8001da8: fa02 f303 lsl.w r3, r2, r3 8001dac: 69ba ldr r2, [r7, #24] 8001dae: 4313 orrs r3, r2 8001db0: 61bb str r3, [r7, #24] GPIOx->AFR[position >> 3U] = temp; 8001db2: 69fb ldr r3, [r7, #28] 8001db4: 08da lsrs r2, r3, #3 8001db6: 687b ldr r3, [r7, #4] 8001db8: 3208 adds r2, #8 8001dba: 69b9 ldr r1, [r7, #24] 8001dbc: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 8001dc0: 687b ldr r3, [r7, #4] 8001dc2: 681b ldr r3, [r3, #0] 8001dc4: 61bb str r3, [r7, #24] temp &= ~(GPIO_MODER_MODER0 << (position * 2U)); 8001dc6: 69fb ldr r3, [r7, #28] 8001dc8: 005b lsls r3, r3, #1 8001dca: 2203 movs r2, #3 8001dcc: fa02 f303 lsl.w r3, r2, r3 8001dd0: 43db mvns r3, r3 8001dd2: 69ba ldr r2, [r7, #24] 8001dd4: 4013 ands r3, r2 8001dd6: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 8001dd8: 683b ldr r3, [r7, #0] 8001dda: 685b ldr r3, [r3, #4] 8001ddc: f003 0203 and.w r2, r3, #3 8001de0: 69fb ldr r3, [r7, #28] 8001de2: 005b lsls r3, r3, #1 8001de4: fa02 f303 lsl.w r3, r2, r3 8001de8: 69ba ldr r2, [r7, #24] 8001dea: 4313 orrs r3, r2 8001dec: 61bb str r3, [r7, #24] GPIOx->MODER = temp; 8001dee: 687b ldr r3, [r7, #4] 8001df0: 69ba ldr r2, [r7, #24] 8001df2: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) != 0x00U) 8001df4: 683b ldr r3, [r7, #0] 8001df6: 685b ldr r3, [r3, #4] 8001df8: f403 3340 and.w r3, r3, #196608 ; 0x30000 8001dfc: 2b00 cmp r3, #0 8001dfe: f000 80c0 beq.w 8001f82 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8001e02: 2300 movs r3, #0 8001e04: 60fb str r3, [r7, #12] 8001e06: 4b66 ldr r3, [pc, #408] ; (8001fa0 ) 8001e08: 6c5b ldr r3, [r3, #68] ; 0x44 8001e0a: 4a65 ldr r2, [pc, #404] ; (8001fa0 ) 8001e0c: f443 4380 orr.w r3, r3, #16384 ; 0x4000 8001e10: 6453 str r3, [r2, #68] ; 0x44 8001e12: 4b63 ldr r3, [pc, #396] ; (8001fa0 ) 8001e14: 6c5b ldr r3, [r3, #68] ; 0x44 8001e16: f403 4380 and.w r3, r3, #16384 ; 0x4000 8001e1a: 60fb str r3, [r7, #12] 8001e1c: 68fb ldr r3, [r7, #12] temp = SYSCFG->EXTICR[position >> 2U]; 8001e1e: 4a61 ldr r2, [pc, #388] ; (8001fa4 ) 8001e20: 69fb ldr r3, [r7, #28] 8001e22: 089b lsrs r3, r3, #2 8001e24: 3302 adds r3, #2 8001e26: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8001e2a: 61bb str r3, [r7, #24] temp &= ~(0x0FU << (4U * (position & 0x03U))); 8001e2c: 69fb ldr r3, [r7, #28] 8001e2e: f003 0303 and.w r3, r3, #3 8001e32: 009b lsls r3, r3, #2 8001e34: 220f movs r2, #15 8001e36: fa02 f303 lsl.w r3, r2, r3 8001e3a: 43db mvns r3, r3 8001e3c: 69ba ldr r2, [r7, #24] 8001e3e: 4013 ands r3, r2 8001e40: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); 8001e42: 687b ldr r3, [r7, #4] 8001e44: 4a58 ldr r2, [pc, #352] ; (8001fa8 ) 8001e46: 4293 cmp r3, r2 8001e48: d037 beq.n 8001eba 8001e4a: 687b ldr r3, [r7, #4] 8001e4c: 4a57 ldr r2, [pc, #348] ; (8001fac ) 8001e4e: 4293 cmp r3, r2 8001e50: d031 beq.n 8001eb6 8001e52: 687b ldr r3, [r7, #4] 8001e54: 4a56 ldr r2, [pc, #344] ; (8001fb0 ) 8001e56: 4293 cmp r3, r2 8001e58: d02b beq.n 8001eb2 8001e5a: 687b ldr r3, [r7, #4] 8001e5c: 4a55 ldr r2, [pc, #340] ; (8001fb4 ) 8001e5e: 4293 cmp r3, r2 8001e60: d025 beq.n 8001eae 8001e62: 687b ldr r3, [r7, #4] 8001e64: 4a54 ldr r2, [pc, #336] ; (8001fb8 ) 8001e66: 4293 cmp r3, r2 8001e68: d01f beq.n 8001eaa 8001e6a: 687b ldr r3, [r7, #4] 8001e6c: 4a53 ldr r2, [pc, #332] ; (8001fbc ) 8001e6e: 4293 cmp r3, r2 8001e70: d019 beq.n 8001ea6 8001e72: 687b ldr r3, [r7, #4] 8001e74: 4a52 ldr r2, [pc, #328] ; (8001fc0